diff --git a/boards/Digilent DE0/README.md b/boards/Digilent DE0/README.md new file mode 100644 index 0000000..e57f316 --- /dev/null +++ b/boards/Digilent DE0/README.md @@ -0,0 +1,3 @@ +## Digilent DE0 board + +* Altera EP3C16F484C6 FPGA diff --git a/boards/Digilent DE0/Speech256_DE0.qpf b/boards/Digilent DE0/Speech256_DE0.qpf new file mode 100644 index 0000000..06ce1ec --- /dev/null +++ b/boards/Digilent DE0/Speech256_DE0.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 19:34:27 October 25, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "19:34:27 October 25, 2017" + +# Revisions + +PROJECT_REVISION = "Speech256_DE0" diff --git a/boards/Digilent DE0/Speech256_DE0.qsf b/boards/Digilent DE0/Speech256_DE0.qsf new file mode 100644 index 0000000..ae983c3 --- /dev/null +++ b/boards/Digilent DE0/Speech256_DE0.qsf @@ -0,0 +1,62 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 19:34:27 October 25, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Speech256_DE0_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C16F484C6 +set_global_assignment -name TOP_LEVEL_ENTITY Speech256_DE0 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:34:27 OCTOBER 25, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name VERILOG_FILE ../../verilog/controller/xlat.v +set_global_assignment -name VERILOG_FILE ../../verilog/controller/ctrlrom.v +set_global_assignment -name VERILOG_FILE ../../verilog/controller/controller.v +set_global_assignment -name VERILOG_FILE ../../verilog/filter/filter.v +set_global_assignment -name VERILOG_FILE ../../verilog/pwmdac/pwmdac.v +set_global_assignment -name VERILOG_FILE ../../verilog/source/source.v +set_global_assignment -name VERILOG_FILE ../../verilog/spmul/spmul.v +set_global_assignment -name VERILOG_FILE ../../verilog/speech256_top/speech256_top.v +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/verilog/controller/controller.v b/verilog/controller/controller.v index 315fd11..2a1717b 100644 --- a/verilog/controller/controller.v +++ b/verilog/controller/controller.v @@ -38,7 +38,6 @@ module CONTROLLER ( //////////// INPUTS ////////// input [5:0] data_in; input data_stb; - input source_stb_in; input period_done_in; // used for duration counting // internal counter and data registers