From 1c293f13e8319357ea49cc591b8dc2dfa8d4e35a Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@gmail.com>
Date: Thu, 26 Oct 2017 21:29:34 +0200
Subject: [PATCH] Added pre-emphasis to PWMDAC - works but not impressed

---
 verilog/pwmdac/pwmdac.v | 33 ++++++++++++++++++++++++++++-----
 verilog/source/source.v |  2 +-
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/verilog/pwmdac/pwmdac.v b/verilog/pwmdac/pwmdac.v
index 2a43b64..18042ab 100644
--- a/verilog/pwmdac/pwmdac.v
+++ b/verilog/pwmdac/pwmdac.v
@@ -30,11 +30,33 @@ module PWMDAC (
 	input signed [7:0] din;
     output reg din_ack;             // is high for 1 clock cycle after reading the din signal
 
-
     // internal counter and data registers
     reg signed [7:0] counter;
     reg signed [7:0] data;
 
+    // pre-emphasis filter
+    reg signed [7:0]   last_data;
+    reg signed [10:0]  sum1r_d;
+    reg signed [10:0]  sum1r;
+    wire signed [10:0] sum1;
+    wire signed [13:0] sum2;
+    reg signed [7:0]  quantdata;
+
+    assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data   - $signed({last_data, 2'b00});
+    assign sum2 = $signed({sum1r[10],{sum1r, 2'b00}}) + sum1r - $signed({sum1r_d, 2'b00});
+
+    // output saturation
+    always @(*)
+    begin        
+        if (sum2[13] ^ sum2[12] != 0)
+        begin
+            // saturation needed
+            quantdata = sum2[13] ?  8'h80 : 8'h7F;
+        end
+        else 
+            quantdata = sum2[12:5];
+    end
+
     always @(posedge clk, negedge rst_an)
     begin
         if (rst_an == 0)
@@ -52,7 +74,7 @@ module PWMDAC (
 
             // compare counter with data 
             // and set output accordingly.
-            if (data > counter)
+            if (quantdata > counter)
                 dacout <= 1;
             else
                 dacout <= 0;
@@ -61,13 +83,14 @@ module PWMDAC (
             // counter is 127
             if (counter == 8'h7F)
             begin
+                sum1r   <= sum1;
+                sum1r_d <= sum1r;
+                last_data <= data;
                 data <= din;
                 din_ack <= 1;        
             end
             else
-                din_ack <= 0;
-            
+                din_ack <= 0;            
         end
     end
-
 endmodule
diff --git a/verilog/source/source.v b/verilog/source/source.v
index f87f170..820b428 100644
--- a/verilog/source/source.v
+++ b/verilog/source/source.v
@@ -71,7 +71,7 @@ module SOURCE (
                     
                     // lfsr polynomial is X^17 + X^3 + 1
                     lfsr = {lfsr[15:0], lfsr[16] ^ lfsr[2]};
-                    source_out <= lfsr[0] ? {2'b00, amplitude[14:1]} : {2'b11, (~amplitude[14:1])};
+                    source_out <= lfsr[0] ? {1'b0, amplitude} : {1'b1, ~amplitude};
                 end
                 else
                 begin