From 1d624a482a5e519006c78ef25b11125ecf2d4f37 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@gmail.com>
Date: Tue, 10 Oct 2017 00:54:20 +0200
Subject: [PATCH] Updated PWMDAC test bench

---
 verilog/pwmdac/pwmdac.v    |  3 +++
 verilog/pwmdac/pwmdac_tb.v | 16 +++++++++++++++-
 verilog/pwmdac/run_tb.bat  |  2 +-
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/verilog/pwmdac/pwmdac.v b/verilog/pwmdac/pwmdac.v
index e3d5fb6..5fc4115 100644
--- a/verilog/pwmdac/pwmdac.v
+++ b/verilog/pwmdac/pwmdac.v
@@ -5,6 +5,9 @@
 // Niels Moseley - Moseley Instruments 2017
 // http://www.moseleyinstruments.com
 //
+//
+// For a 10 kHz output rate, the clock rate should be 2.560 MHz
+// 
 
 module PWMDAC (
         clk, 
diff --git a/verilog/pwmdac/pwmdac_tb.v b/verilog/pwmdac/pwmdac_tb.v
index b0eba6c..463af8f 100644
--- a/verilog/pwmdac/pwmdac_tb.v
+++ b/verilog/pwmdac/pwmdac_tb.v
@@ -10,6 +10,8 @@ module PWMDAC_TB;
     reg signed [0:7] din;
     wire dacout, din_ack;
 
+    real accu;
+
     PWMDAC u_pwmdac (
         .clk     (clk),
         .rst_an  (rst_an),
@@ -25,12 +27,24 @@ module PWMDAC_TB;
         clk = 0;
         rst_an = 0;
         din = 0;
+        accu = 0;
         #3
         rst_an = 1;
-        #10240      
+        #655360     
         $finish;
     end
 
+    always @(posedge clk)
+    begin
+        if (din_ack)
+        begin
+            accu = accu + 1.0/256.0;
+            if (accu > 1.0)
+                accu = -1.0;
+            din = $rtoi($sin(2.0*3.1415927*accu)*127.0);
+        end
+    end
+
     always
         #5 clk = !clk;
 
diff --git a/verilog/pwmdac/run_tb.bat b/verilog/pwmdac/run_tb.bat
index e5aef66..d3386c1 100644
--- a/verilog/pwmdac/run_tb.bat
+++ b/verilog/pwmdac/run_tb.bat
@@ -1,5 +1,5 @@
 mkdir bin
-C:\iverilog\bin\iverilog -o bin\pwmdac.vvp -g2005 -s PWMDAC_TB pwmdac.v pwmdac_tb.v
+C:\iverilog\bin\iverilog -o bin\pwmdac.vvp -m va_math -g2005 -s PWMDAC_TB pwmdac.v pwmdac_tb.v
 cd bin
 C:\iverilog\bin\vvp pwmdac.vvp
 cd ..