Added 8-bit to 10-bit coefficient expander

verilog/controller/controller.v

@@ -1,5 +1,5 @@
 // 
-// Speecht256 top level
+// Speech256 controller / sequencer
 //
 // Niels Moseley - Moseley Instruments 2017
 // http://www.moseleyinstruments.com
@@ -28,7 +28,7 @@ module CONTROLLER (
 	//////////// OUTPUTS //////////
     output reg ldq;
     output reg coeff_stb;
-    output reg signed [7:0] coeff_out;
+    output reg signed [9:0] coeff_out;
     output reg [15:0] amp_out;
     output reg [7:0]  period_out;
     //output reg [7:0]  dur_out;
@@ -76,8 +76,11 @@ module CONTROLLER (
     reg  [2:0]  coeff_cnt;
     reg  [1:0]  coeff_cnt_update;
 
+    wire  [9:0]  coeff10bit;
+
     wire done;
 
+    // control program ROM
     CTRLROM u_ctrlrom (
         .clk        (clk),
         .data       (rom_data),
@@ -94,7 +97,13 @@ module CONTROLLER (
     parameter COEFF_CNT_ZERO = 2'b00,   // zero coefficient counter
               COEFF_CNT_NOP  = 2'b01,   // do nothing
               COEFF_CNT_INC  = 2'b10;   // increment coefficient counter
-              
+
+    // 8-bit -> 10-bit coefficient expander
+    XLAT u_xlat (
+        .c8_in(rom_data),
+        .c10_out(coeff10bit)
+    );
+
     always @(posedge clk, negedge rst_an)
     begin
         if (rst_an == 0)
@@ -156,7 +165,7 @@ module CONTROLLER (
             if (serve_pitch_data)
             begin
                 duration   <= dur_tmp;
-                amp_out    <= amp_tmp;
+                amp_out    <= {4'b0000, amp_tmp[15:4]};
                 period_out <= period_tmp;
             end
 
@@ -332,7 +341,7 @@ module CONTROLLER (
                 // send F coefficient
                 begin
                     coeff_stb <= 1;
-                    coeff_out <= rom_data;
+                    coeff_out <= coeff10bit;
                     coeff_cnt_update <= COEFF_CNT_INC;
                     rom_addr_sel <= ROM_ADDR_INC;
                     next_state <= S_LOADCOEF2;
@@ -341,7 +350,7 @@ module CONTROLLER (
                 // send B coefficient
                 begin
                     coeff_stb <= 1;
-                    coeff_out <= rom_data;                    
+                    coeff_out <= coeff10bit;                    
                     if (coeff_cnt == 3'd6)
                         next_state <= S_CMDDECODE; // load next section
                     else

verilog/controller/controller_tb.v

@@ -1,5 +1,5 @@
 // 
-// PWMDAC testbench
+// Controller testbench
 //
 // Niels Moseley - Moseley Instruments 2017
 // http://www.moseleyinstruments.com
@@ -13,7 +13,7 @@ module CONTROLLER_TB;
     reg period_done;
     
     wire ldq;
-    wire signed [7:0] coeff;
+    wire [9:0] coeff;
     wire coeff_load;
     wire [7:0]  period;
     wire [15:0] amp;

verilog/controller/genctrlrom.py

@@ -51,10 +51,8 @@ def convertFilterCoeff(c):
     # 254 -> 2
     # 128 -> xxx
     # 0   -> 0
-    if (c == 0):
-        return 0
     
-    return (256-c);
+    return c;
 
 fout = open('ctrlrom.v','wt')
 

verilog/controller/run_tb.bat

@@ -1,7 +1,12 @@
 python genctrlrom.py
 mkdir bin
 del bin\controller.vvp
-C:\iverilog\bin\iverilog -o bin\controller.vvp -m va_math -g2005 -s CONTROLLER_TB controller.v controller_tb.v ctrlrom.v
+del bin\xlat.vvp
+C:\iverilog\bin\iverilog -o bin\xlat.vvp -m va_math -g2005 -s XLAT_TB xlat.v xlat_tb.v
+C:\iverilog\bin\iverilog -o bin\controller.vvp -m va_math -g2005 -s CONTROLLER_TB controller.v controller_tb.v ctrlrom.v xlat.v
 cd bin
+@echo --== Running XLAT testbench ==--
+C:\iverilog\bin\vvp xlat.vvp -lxt2
+@echo --== Running CONTROLLER testbench ==--
 C:\iverilog\bin\vvp controller.vvp -lxt2
 cd ..

verilog/controller/xlat.v

@@ -0,0 +1,40 @@
+//
+// 8-bit sign-magnitude to 10-bit sign-magnitude 
+// conversion block
+//
+// Niels Moseley - Moseley Instruments 2017
+// http://www.moseleyinstruments.com
+//
+//
+// C1: x*8
+// C2: 301 + (x-38)*4 = 301 - 152 + x*4 = 149 + x*4
+// C3: 425 + (x-69)*2 = 425 - 138 + x*2 = 287 + x*2
+// C4: 481 + (x-97)   = 481 - 97  + x   = 384 + x
+//
+//
+//
+//
+
+module XLAT (
+        c8_in, 
+        c10_out
+    );
+
+    input      [7:0] c8_in;
+    output reg [9:0] c10_out;
+    wire sign;
+
+    assign sign = ~c8_in[7];
+
+    always@(*)
+    begin
+        if (c8_in[6:0] < 38)
+            c10_out <= {sign, c8_in[5:0], 3'b000};
+        else if (c8_in[6:0] < 69)
+            c10_out <= {sign, {c8_in[6:0], 2'b00} + 9'd149};
+        else if (c8_in[6:0] < 97)
+            c10_out <= {sign, {{1'b0, c8_in[6:0]}, 1'b0} + 9'd287};
+        else
+            c10_out <= {sign, {{2'b00, c8_in[6:0]} + 9'd384}};
+    end
+endmodule

verilog/controller/xlat_tb.v

@@ -0,0 +1,31 @@
+// 
+// XLAT testbench
+//
+// Niels Moseley - Moseley Instruments 2017
+// http://www.moseleyinstruments.com
+//
+
+module XLAT_TB;    
+    reg [7:0]  c8_in;
+    wire [9:0] c10_out;
+
+    XLAT u_xlat (
+        c8_in, 
+        c10_out
+    );
+
+    integer i;
+    initial
+    begin
+        $dumpfile ("xlat.vcd");
+        $dumpvars;
+        c8_in[7] = 0;
+        for(i=0; i<128; i=i+1)
+        begin
+            c8_in[6:0] = i;
+            #10;
+        end
+        $finish;
+    end
+
+endmodule

verilog/pwmdac/pwmdac.v

@@ -58,7 +58,7 @@ module PWMDAC (
                 dacout <= 0;
 
             // load new data into DAC when
-            // counter is 255
+            // counter is 127
             if (counter == 8'h7F)
             begin
                 data <= din;

verilog/speech256_top/run_tb.bat

@@ -1,6 +1,6 @@
 mkdir bin
 del bin\speech256_top.vvp
-C:\iverilog\bin\iverilog -o bin\speech256_top.vvp -m va_math -g2005 -s SPEECH256_TOP_TB speech256_top.v speech256_top_tb.v ..\filter\filter.v ..\source\source.v ..\spmul\spmul.v ..\pwmdac\pwmdac.v ..\controller\controller.v ..\controller\ctrlrom.v
+C:\iverilog\bin\iverilog -o bin\speech256_top.vvp -m va_math -g2005 -s SPEECH256_TOP_TB speech256_top.v speech256_top_tb.v ..\filter\filter.v ..\source\source.v ..\spmul\spmul.v ..\pwmdac\pwmdac.v ..\controller\controller.v ..\controller\ctrlrom.v ..\controller\xlat.v
 cd bin
 C:\iverilog\bin\vvp speech256_top.vvp -lxt2
 cd ..

verilog/speech256_top/speech256_top.v

@@ -40,7 +40,7 @@ module SPEECH256_TOP (
     wire [7:0]  dur;
     wire [15:0] amp;
     
-    wire signed  [7:0]  coef_bus;
+    wire signed  [9:0]  coef_bus;
     wire                coef_load;
     
     wire done;
@@ -58,7 +58,7 @@ module SPEECH256_TOP (
     FILTER u_filter (
         .clk        (clk),
         .rst_an     (rst_an),
-        .coef_in    ({coef_bus, 1'b0}),
+        .coef_in    (coef_bus),
         .coef_load  (coef_load),
         .sig_in     (sig_source),
         .sig_out    (sig_filter),