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Added some links to technical information.

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Niels Moseley 2019-05-02 13:45:38 +02:00
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@ -8,6 +8,10 @@ An FPGA implementation of a classic 80ies speech synthesizer in Verilog.
[![IMAGE ALT TEXT HERE](http://img.youtube.com/vi/lbWPwb_cT0s/0.jpg)](http://www.youtube.com/watch?v=lbWPwb_cT0s) [![IMAGE ALT TEXT HERE](http://img.youtube.com/vi/lbWPwb_cT0s/0.jpg)](http://www.youtube.com/watch?v=lbWPwb_cT0s)
## Building
In order to build the FPGA bit stream for the Digitent DE0 board, you need [Quartus II 13.1](http://fpgasoftware.intel.com/13.0sp1/). If you have a different FPGA board, use the tools provided with that board but be aware the project will need to be adapted.
## FPGA requirements ## FPGA requirements
* 4 K ROM * 4 K ROM
@ -47,6 +51,9 @@ The second-order filter transfer function is H(z) = 1 / (1 - 2 * A1 * z^-1 - A2
### CONTROLLER ### CONTROLLER
The controller reads the allophones from the control bus and generates the necessary signals to drive the source and filter blocks. The parameters for the source and filter are encoded in a 4K ROM by means of high-level instructions. The controller reads the allophones from the control bus and generates the necessary signals to drive the source and filter blocks. The parameters for the source and filter are encoded in a 4K ROM by means of high-level instructions.
## More technical stuff
For more information on how this system works, see [http://www.cpcwiki.eu/index.php/SP0256#Technical](http://www.cpcwiki.eu/index.php/SP0256#Technical) and [http://spatula-city.org/~im14u2c/intv/tech/sp0256_instr_set.html](http://spatula-city.org/~im14u2c/intv/tech/sp0256_instr_set.html).
## License ## License
GPLv3. Please see the LICENSE file. GPLv3. Please see the LICENSE file.