mirror of
https://github.com/trcwm/Speech256.git
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non-working top level
This commit is contained in:
Niels Moseley
parent
2f89161c65
commit
704cd3d4cb
357
verilog/controller/controller.v
Normal file
357
verilog/controller/controller.v
Normal file
@ -0,0 +1,357 @@
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//
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// Speecht256 top level
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//
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// Niels Moseley - Moseley Instruments 2017
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// http://www.moseleyinstruments.com
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//
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//
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module CONTROLLER (
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clk, // global Speech256 clock
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rst_an,
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ldq, // load request, is high when new allophone can be loaded
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data_in, // allophone input
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data_stb, // allophone strobe input
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period_out, // pitch period output
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amp_out, // amplitude output
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coeff_out, // 8-bit coefficient data out
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coeff_stb, // '1' when coeff_out holds new coefficient data
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period_done_in // should be '1' when the source finished a period
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);
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//////////// CLOCK //////////
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input clk;
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//////////// RESET, ACTIVE LOW //////////
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input rst_an;
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//////////// OUTPUTS //////////
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output reg ldq;
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output reg coeff_stb;
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output reg signed [7:0] coeff_out;
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output reg [15:0] amp_out;
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output reg [7:0] period_out;
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//output reg [7:0] dur_out;
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//////////// INPUTS //////////
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input [5:0] data_in;
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input data_stb;
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input source_stb_in;
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input period_done_in; // used for duration counting
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// internal counter and data registers
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wire [7:0] rom_data;
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reg [11:0] rom_addr;
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reg [11:0] last_rom_addr;
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reg [2:0] rom_addr_sel;
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reg rom_en;
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reg [3:0] jmpmsb;
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reg jmpmsb_load;
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reg [5:0] cur_allo;
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reg [3:0] cur_cmd;
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reg [3:0] cur_state;
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reg [3:0] next_state;
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reg [5:0] data_in_buf;
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reg amp1_load, amp2_load;
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reg period_load;
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reg dur_load;
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reg allo_load;
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reg load_cur_cmd;
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reg serve_pitch_data;
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reg set_ldq, reset_ldq;
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reg dur_cnt_clear;
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wire serve_next_allo_data;
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reg [15:0] amp_tmp;
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reg [7:0] period_tmp;
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reg [7:0] dur_tmp;
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reg [7:0] duration;
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reg [7:0] dur_cnt;
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reg [2:0] coeff_cnt;
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reg [1:0] coeff_cnt_update;
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wire done;
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CTRLROM u_ctrlrom (
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.clk (clk),
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.data (rom_data),
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.addr (rom_addr),
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.en (rom_en)
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);
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parameter ROM_ADDR_ZERO = 3'b000, // zero the ROM address
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ROM_ADDR_INC = 3'b001, // increment the ROM address
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ROM_ADDR_JMP = 3'b010, // jump to code
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ROM_ADDR_ALLO = 3'b011, // read allophone jump address
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ROM_ADDR_NOP = 3'b100;
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parameter COEFF_CNT_ZERO = 2'b00, // zero coefficient counter
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COEFF_CNT_NOP = 2'b01, // do nothing
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COEFF_CNT_INC = 2'b10; // increment coefficient counter
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always @(posedge clk, negedge rst_an)
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begin
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if (rst_an == 0)
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begin
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// reset values
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amp_out <= 0;
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period_out <= 8'd1;
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rom_en <= 1;
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rom_addr <= 0;
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last_rom_addr <= 0;
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cur_state <= 0;
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cur_allo <= 0;
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cur_cmd <= 0;
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coeff_stb <= 0;
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coeff_out <= 0;
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coeff_cnt <= 0;
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jmpmsb <= 0;
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ldq <= 0;
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dur_cnt <= 0;
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duration <= 0;
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end
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else
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begin
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// clocked process
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cur_state <= next_state;
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case (coeff_cnt_update)
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COEFF_CNT_ZERO:
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coeff_cnt <= 0;
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COEFF_CNT_NOP:
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coeff_cnt <= coeff_cnt;
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COEFF_CNT_INC:
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coeff_cnt <= coeff_cnt + 1;
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default:
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coeff_cnt <= 0;
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endcase
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if (jmpmsb_load)
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jmpmsb <= rom_data[3:0];
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if (amp1_load)
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amp_tmp[7:0] <= rom_data;
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if (amp2_load)
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amp_tmp[15:8] <= rom_data;
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if (period_load)
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period_tmp <= rom_data;
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if (dur_load)
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dur_tmp <= rom_data;
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if (allo_load)
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cur_allo <= data_in;
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if (load_cur_cmd)
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cur_cmd <= rom_data[3:0];
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if (serve_pitch_data)
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begin
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duration <= dur_tmp;
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amp_out <= amp_tmp;
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period_out <= period_tmp;
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end
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if (set_ldq == 1)
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ldq <= 1;
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else if (reset_ldq == 1)
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ldq <= 0;
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if ((period_done_in == 1) && (!serve_next_allo_data))
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begin
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dur_cnt <= dur_cnt + 1;
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end
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if (dur_cnt_clear)
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begin
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dur_cnt <= 0;
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end
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last_rom_addr <= rom_addr;
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end
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end
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assign serve_next_allo_data = (dur_cnt == duration) ? 1 : 0;
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parameter S_IDLE = 4'd0,
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S_JMPADDR1 = 4'd1,
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S_JMPADDR2 = 4'd2,
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S_JMPADDR3 = 4'd3,
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S_CMDLOAD = 4'd4,
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S_CMDDECODE= 4'd5,
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S_LOADAMP1 = 4'd6,
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S_LOADAMP2 = 4'd7,
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S_LOADDUR = 4'd8,
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S_LOADPERIOD= 4'd9,
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S_SERVEGATE = 4'd10,
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S_LOADCOEF1 = 4'd11,
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S_LOADCOEF2 = 4'd12;
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always @(*)
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begin
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// rom address multiplexer
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case (rom_addr_sel)
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ROM_ADDR_ZERO:
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rom_addr <= 0;
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ROM_ADDR_INC:
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rom_addr <= last_rom_addr + 1;
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ROM_ADDR_JMP:
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rom_addr <= {jmpmsb, rom_data[7:0]};
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ROM_ADDR_ALLO:
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rom_addr <= {5'b00000, cur_allo, 1'b0};
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ROM_ADDR_NOP:
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rom_addr <= last_rom_addr;
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default:
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rom_addr <= 0;
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endcase
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end
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always @(*)
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begin
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// ---------------------------------------------
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// -------- MAIN FINITE STATE MACHINE ----------
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// ---------------------------------------------
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// FSM defaults:
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rom_addr_sel <= ROM_ADDR_INC;
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coeff_cnt_update <= COEFF_CNT_NOP;
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next_state <= cur_state;
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coeff_stb <= 0;
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jmpmsb_load <= 0;
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amp1_load <= 0;
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amp2_load <= 0;
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period_load <= 0;
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dur_load <= 0;
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allo_load <= 0;
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load_cur_cmd <= 0;
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set_ldq <= 0;
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reset_ldq <= 0;
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serve_pitch_data <= 0;
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dur_cnt_clear <= 0;
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case (cur_state)
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S_IDLE:
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begin
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set_ldq <= 1;
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if (serve_next_allo_data == 1)
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begin
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// we've run out of allophone data ..
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end
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if (data_stb == 1)
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begin
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allo_load <= 1;
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next_state <= S_JMPADDR1;
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end
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rom_addr_sel <= ROM_ADDR_ZERO;
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end
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S_JMPADDR1:
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begin
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// get MSB of allophone address code
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rom_addr_sel <= ROM_ADDR_ALLO;
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next_state <= S_JMPADDR2;
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end
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S_JMPADDR2:
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begin
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// get LSB of allophone address code
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jmpmsb_load <= 1;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_CMDLOAD;
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end
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S_JMPADDR3:
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begin
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next_state <= S_CMDLOAD;
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end
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S_CMDLOAD:
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begin
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// perform jmp
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rom_addr_sel <= ROM_ADDR_JMP;
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next_state <= S_CMDDECODE;
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reset_ldq <= 1;
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end
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S_CMDDECODE:
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begin
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// current command and
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// terminate sequencer if
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// CMD == 0xF
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if (rom_data == 4'hF)
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next_state <= S_IDLE; // end of command
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else
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begin
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_LOADAMP1;
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end
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load_cur_cmd <= 1;
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//cur_cmd <= rom_data;
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end
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S_LOADAMP1: // load 16-bit AMP
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begin
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amp1_load <= 1;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_LOADAMP2;
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end
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S_LOADAMP2:
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begin
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amp2_load <= 1;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_LOADDUR;
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end
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S_LOADDUR:
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begin
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dur_load <= 1;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_LOADPERIOD;
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end
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S_LOADPERIOD:
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begin
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period_load <= 1;
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coeff_cnt_update <= COEFF_CNT_ZERO;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_SERVEGATE;
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end
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S_SERVEGATE:
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begin
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rom_addr_sel <= ROM_ADDR_NOP;
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if (serve_next_allo_data == 1)
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begin
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serve_pitch_data <= 1;
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dur_cnt_clear <= 1;
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next_state <= (cur_cmd == 4'd2) ? S_LOADCOEF1 : S_CMDDECODE;
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end
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end
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S_LOADCOEF1:
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// send F coefficient
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begin
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coeff_stb <= 1;
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coeff_out <= rom_data;
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coeff_cnt_update <= COEFF_CNT_INC;
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rom_addr_sel <= ROM_ADDR_INC;
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next_state <= S_LOADCOEF2;
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end
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S_LOADCOEF2:
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// send B coefficient
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begin
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coeff_stb <= 1;
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coeff_out <= rom_data;
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if (coeff_cnt == 3'd6)
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next_state <= S_CMDDECODE; // load next section
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else
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next_state <= S_LOADCOEF1; // next command
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rom_addr_sel <= ROM_ADDR_INC;
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end
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default:
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next_state <= S_IDLE;
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endcase
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end
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endmodule
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64
verilog/controller/controller_tb.v
Normal file
64
verilog/controller/controller_tb.v
Normal file
@ -0,0 +1,64 @@
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//
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// PWMDAC testbench
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//
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// Niels Moseley - Moseley Instruments 2017
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// http://www.moseleyinstruments.com
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//
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module CONTROLLER_TB;
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reg clk, rst_an;
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reg [5:0] data_in;
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reg data_stb, serve_next;
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reg period_done;
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wire ldq;
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wire signed [7:0] coeff;
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wire coeff_load;
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wire [7:0] period;
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wire [15:0] amp;
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wire [7:0] dur;
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CONTROLLER u_controller (
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.clk (clk),
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.rst_an (rst_an),
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.ldq (ldq),
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.data_in (data_in),
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.data_stb (data_stb),
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.period_out (period),
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.amp_out (amp),
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.coeff_out (coeff),
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.coeff_stb (coeff_load),
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.period_done_in (period_done)
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);
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initial
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begin
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$dumpfile ("controller.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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data_in = 6;
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data_stb = 0;
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period_done = 0;
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#5
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rst_an = 1;
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#5
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// load allophone
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data_stb = 1;
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#10
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data_stb = 0;
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serve_next = 1;
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#300000
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$finish;
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end
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always @(posedge clk)
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begin
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;
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end
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always
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#5 clk = !clk;
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endmodule
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3995
verilog/controller/ctrlrom.hex
Normal file
3995
verilog/controller/ctrlrom.hex
Normal file
File diff suppressed because it is too large
Load Diff
4018
verilog/controller/ctrlrom.v
Normal file
4018
verilog/controller/ctrlrom.v
Normal file
File diff suppressed because it is too large
Load Diff
117
verilog/controller/genctrlrom.py
Normal file
117
verilog/controller/genctrlrom.py
Normal file
@ -0,0 +1,117 @@
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#
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# Generate control rom for Speech256 project
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#
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# Copyright N.A. Moseley 2017 / Moseley Instruments
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#
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# The control rom is in a slightly different format
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# than we need for the Verilog code, so in addition
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# to making a ROM directry, we massage it a bit...
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#
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VerilogHeader = """
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// This file was auto-generated,
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// do not modify by hand!
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module CTRLROM (
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clk,
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en,
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addr,
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data
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);
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input clk;
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input en;
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input [11:0] addr;
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output reg [7:0] data;
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always @(posedge clk)
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begin
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if (en)
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case(addr)
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"""
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||||
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||||
VerilogFooter = """ default: data <= 8'bXXXXXXXX;
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endcase
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end
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endmodule
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||||
"""
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||||
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||||
RomAddress = 0;
|
||||
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def emitRomByte(b):
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global RomAddress
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global fout
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fout.write(" 12'd"+str(RomAddress)+": data <= 8'd" + str(b) + ";\n")
|
||||
RomAddress = RomAddress + 1;
|
||||
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||||
def convertFilterCoeff(c):
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# turn c into negative 8-bit number
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||||
# 1 -> 255
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# 2 -> 254
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# 255 -> 1
|
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# 254 -> 2
|
||||
# 128 -> xxx
|
||||
# 0 -> 0
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if (c == 0):
|
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return 0
|
||||
|
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return (256-c);
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||||
|
||||
fout = open('ctrlrom.v','wt')
|
||||
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||||
with open('ctrlrom.hex', 'r') as fp:
|
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hex_list = fp.readlines()
|
||||
|
||||
|
||||
cmd_list = [int(c,16) for c in hex_list];
|
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||||
# generate header
|
||||
fout.write(VerilogHeader)
|
||||
|
||||
# generate jump table
|
||||
for I in range(0,0x7E):
|
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emitRomByte(cmd_list[I])
|
||||
|
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counter = 0x7E
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while (counter < len(cmd_list)):
|
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cmd = cmd_list[counter];
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if (cmd == 0): # JUMP INSTRUCTION
|
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print("?")
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elif (cmd == 1): # SET AMP AND PITCH
|
||||
emitRomByte(cmd)
|
||||
emitRomByte(cmd_list[counter+1]) # AMP LSB
|
||||
emitRomByte(cmd_list[counter+2]) # AMP MSB
|
||||
emitRomByte(cmd_list[counter+3]) # DUR
|
||||
emitRomByte(cmd_list[counter+4]) # PITCH
|
||||
counter = counter + 4
|
||||
#print("SET AMP+PITCH")
|
||||
elif (cmd == 2): # SET COEFFICIENTS
|
||||
emitRomByte(cmd)
|
||||
emitRomByte(cmd_list[counter+1]) # AMP LSB
|
||||
emitRomByte(cmd_list[counter+2]) # AMP MSB
|
||||
emitRomByte(cmd_list[counter+3]) # DUR
|
||||
emitRomByte(cmd_list[counter+4]) # PITCH
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+10])) # F6
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+10+6])) # B6
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+9])) # F5
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+9+6])) # B5
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+8])) # F4
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+8+6])) # B4
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+7])) # F3
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+7+6])) # B3
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+6])) # F2
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+6+6])) # B2
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+5])) # F1
|
||||
emitRomByte(convertFilterCoeff(cmd_list[counter+5+6])) # B1
|
||||
counter = counter + 4 + 12
|
||||
#print("SET COEFFS")
|
||||
elif (cmd == 15): # SET COEFFICIENTS: # END OF COMMAND / 15
|
||||
emitRomByte(cmd)
|
||||
else:
|
||||
print("*** ERROR ***")
|
||||
break
|
||||
counter = counter + 1
|
||||
|
||||
# generate footer
|
||||
fout.write(VerilogFooter)
|
||||
|
||||
fout.close()
|
||||
7
verilog/controller/run_tb.bat
Normal file
7
verilog/controller/run_tb.bat
Normal file
@ -0,0 +1,7 @@
|
||||
python genctrlrom.py
|
||||
mkdir bin
|
||||
del bin\controller.vvp
|
||||
C:\iverilog\bin\iverilog -o bin\controller.vvp -m va_math -g2005 -s CONTROLLER_TB controller.v controller_tb.v ctrlrom.v
|
||||
cd bin
|
||||
C:\iverilog\bin\vvp controller.vvp -lxt2
|
||||
cd ..
|
||||
@ -148,7 +148,7 @@ module FILTER (
|
||||
if (do_accu)
|
||||
begin
|
||||
if (double_mode)
|
||||
accu <= accu_in +{mul_result[14:0], 1'b0};
|
||||
accu <= accu_in + {mul_result[14:0], 1'b0};
|
||||
else
|
||||
accu <= accu_in + mul_result;
|
||||
end
|
||||
|
||||
@ -12,9 +12,9 @@
|
||||
module PWMDAC (
|
||||
clk,
|
||||
rst_an,
|
||||
din,
|
||||
din_ack,
|
||||
dacout
|
||||
din, // 16 bit signed data input
|
||||
din_ack, // is high for 1 clock cycle after reading the din signal
|
||||
dacout // 1-bit PWM output signal
|
||||
);
|
||||
|
||||
//////////// CLOCK //////////
|
||||
|
||||
@ -12,6 +12,7 @@ module SOURCE (
|
||||
period, // period in 10kHz samples
|
||||
amplitude, // unsigned 15-bit desired amplitude of source output
|
||||
strobe, // when strobe == '1' a new source_out will be generated
|
||||
period_done, // is set to '1' at the end of the period
|
||||
source_out // signed 16-bit source output
|
||||
);
|
||||
|
||||
@ -23,6 +24,7 @@ module SOURCE (
|
||||
|
||||
//////////// OUTPUTS //////////
|
||||
output reg signed [15:0] source_out;
|
||||
output reg period_done;
|
||||
|
||||
//////////// INPUTS //////////
|
||||
input [14:0] amplitude;
|
||||
@ -32,6 +34,7 @@ module SOURCE (
|
||||
// internal counter and data registers
|
||||
reg signed [7:0] periodcnt;
|
||||
reg [16:0] lfsr;
|
||||
reg last_strobe;
|
||||
|
||||
always @(posedge clk, negedge rst_an)
|
||||
begin
|
||||
@ -39,12 +42,17 @@ module SOURCE (
|
||||
begin
|
||||
// reset values
|
||||
periodcnt <= 0;
|
||||
period_done <= 1;
|
||||
source_out <= 0;
|
||||
last_strobe <= 0;
|
||||
lfsr <= 17'h1; //note: never reset the LFSR to zero!
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (strobe == 1)
|
||||
// default value
|
||||
period_done <= 0;
|
||||
|
||||
if ((strobe == 1) && (last_strobe == 0))
|
||||
begin
|
||||
// if period == 0, we need to generate noise
|
||||
// else we generate a pulse wave
|
||||
@ -54,7 +62,10 @@ module SOURCE (
|
||||
// LFSR NOISE GENERATOR
|
||||
// ------------------------------------------------------------
|
||||
if (periodcnt == 64)
|
||||
begin
|
||||
periodcnt <= 0;
|
||||
period_done <= 1;
|
||||
end
|
||||
else
|
||||
periodcnt <= periodcnt + 1;
|
||||
|
||||
@ -69,7 +80,10 @@ module SOURCE (
|
||||
// ------------------------------------------------------------
|
||||
// make periodcnt count from 0 .. period-1
|
||||
if (periodcnt == period)
|
||||
begin
|
||||
periodcnt <= 0;
|
||||
period_done <= 1;
|
||||
end
|
||||
else
|
||||
periodcnt <= periodcnt + 1;
|
||||
|
||||
@ -79,6 +93,7 @@ module SOURCE (
|
||||
source_out <= 16'h0000;
|
||||
end
|
||||
end
|
||||
last_strobe <= strobe;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@ module SOURCE_TB;
|
||||
reg [7:0] cnt;
|
||||
|
||||
wire signed [15:0] source_out;
|
||||
wire period_done;
|
||||
|
||||
SOURCE u_source (
|
||||
.clk (clk),
|
||||
@ -20,6 +21,7 @@ module SOURCE_TB;
|
||||
.period (period),
|
||||
.amplitude (amp),
|
||||
.strobe (strobe),
|
||||
.period_done (period_done)
|
||||
.source_out (source_out)
|
||||
);
|
||||
|
||||
|
||||
6
verilog/speech256_top/run_tb.bat
Normal file
6
verilog/speech256_top/run_tb.bat
Normal file
@ -0,0 +1,6 @@
|
||||
mkdir bin
|
||||
del bin\speech256_top.vvp
|
||||
C:\iverilog\bin\iverilog -o bin\speech256_top.vvp -m va_math -g2005 -s SPEECH256_TOP_TB speech256_top.v speech256_top_tb.v ..\filter\filter.v ..\source\source.v ..\spmul\spmul.v ..\pwmdac\pwmdac.v ..\controller\controller.v ..\controller\ctrlrom.v
|
||||
cd bin
|
||||
C:\iverilog\bin\vvp speech256_top.vvp -lxt2
|
||||
cd ..
|
||||
102
verilog/speech256_top/speech256_top.v
Normal file
102
verilog/speech256_top/speech256_top.v
Normal file
@ -0,0 +1,102 @@
|
||||
//
|
||||
// Speecht256 top level
|
||||
//
|
||||
// Niels Moseley - Moseley Instruments 2017
|
||||
// http://www.moseleyinstruments.com
|
||||
//
|
||||
//
|
||||
|
||||
module SPEECH256_TOP (
|
||||
clk, // global Speech256 clock
|
||||
rst_an,
|
||||
ldq, // load request, is high when new allophone can be loaded
|
||||
data_in, // allophone input
|
||||
data_stb, // allophone strobe input
|
||||
dac_out, // 1-bit PWM DAC output
|
||||
);
|
||||
|
||||
//////////// CLOCK //////////
|
||||
input clk;
|
||||
|
||||
//////////// RESET, ACTIVE LOW //////////
|
||||
input rst_an;
|
||||
|
||||
//////////// OUTPUTS //////////
|
||||
output dac_out;
|
||||
output ldq;
|
||||
|
||||
//////////// INPUTS //////////
|
||||
input [5:0] data_in;
|
||||
input data_stb;
|
||||
|
||||
|
||||
// internal counter and data registers
|
||||
wire pwmdac_ack, src_strobe;
|
||||
wire signed [15:0] sig_source;
|
||||
wire signed [15:0] sig_filter;
|
||||
wire period_done;
|
||||
|
||||
wire [7:0] period;
|
||||
wire [7:0] dur;
|
||||
wire [15:0] amp;
|
||||
|
||||
wire signed [7:0] coef_bus;
|
||||
wire coef_load;
|
||||
|
||||
wire done;
|
||||
|
||||
SOURCE u_source (
|
||||
.clk (clk),
|
||||
.rst_an (rst_an),
|
||||
.period (period),
|
||||
.amplitude (amp[14:0]),
|
||||
.strobe (src_strobe),
|
||||
.period_done (period_done),
|
||||
.source_out (sig_source)
|
||||
);
|
||||
|
||||
FILTER u_filter (
|
||||
.clk (clk),
|
||||
.rst_an (rst_an),
|
||||
.coef_in ({coef_bus, 1'b0}),
|
||||
.coef_load (coef_load),
|
||||
.sig_in (sig_source),
|
||||
.sig_out (sig_filter),
|
||||
.start (pwmdac_ack),
|
||||
.done (src_strobe)
|
||||
);
|
||||
|
||||
PWMDAC u_pwmdac (
|
||||
.clk (clk),
|
||||
.rst_an (rst_an),
|
||||
.din (sig_filter[15:8]),
|
||||
.din_ack (pwmdac_ack),
|
||||
.dacout (dac_out)
|
||||
);
|
||||
|
||||
CONTROLLER u_controller (
|
||||
.clk (clk),
|
||||
.rst_an (rst_an),
|
||||
.ldq (ldq),
|
||||
.data_in (data_in),
|
||||
.data_stb (data_stb),
|
||||
.period_out (period),
|
||||
.amp_out (amp),
|
||||
.coeff_out (coef_bus),
|
||||
.coeff_stb (coef_load),
|
||||
.period_done_in (period_done)
|
||||
);
|
||||
|
||||
always @(posedge clk, negedge rst_an)
|
||||
begin
|
||||
if (rst_an == 0)
|
||||
begin
|
||||
// reset values
|
||||
end
|
||||
else
|
||||
begin
|
||||
// clocked process
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
53
verilog/speech256_top/speech256_top_tb.v
Normal file
53
verilog/speech256_top/speech256_top_tb.v
Normal file
@ -0,0 +1,53 @@
|
||||
//
|
||||
// PWMDAC testbench
|
||||
//
|
||||
// Niels Moseley - Moseley Instruments 2017
|
||||
// http://www.moseleyinstruments.com
|
||||
//
|
||||
|
||||
module SPEECH256_TOP_TB;
|
||||
reg clk, rst_an;
|
||||
reg [5:0] data_in;
|
||||
reg data_stb;
|
||||
wire ldq,dac_out;
|
||||
|
||||
SPEECH256_TOP u_speech256_top (
|
||||
.clk (clk),
|
||||
.rst_an (rst_an),
|
||||
.ldq (ldq),
|
||||
.data_in (data_in),
|
||||
.data_stb (data_stb),
|
||||
.dac_out (dac_out)
|
||||
);
|
||||
|
||||
integer fd; // file descriptor
|
||||
|
||||
initial
|
||||
begin
|
||||
fd = $fopen("dacout.sw","wb");
|
||||
$dumpfile ("speech256_top.vcd");
|
||||
$dumpvars;
|
||||
clk = 0;
|
||||
rst_an = 0;
|
||||
data_stb = 0;
|
||||
#5
|
||||
rst_an = 1;
|
||||
#5
|
||||
data_in = 6;
|
||||
data_stb = 1;
|
||||
#5
|
||||
data_stb = 0;
|
||||
#300000
|
||||
//$fclose(fd);
|
||||
$finish;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
$fwrite(fd,"%u", {31'd0,dac_out});
|
||||
end
|
||||
|
||||
always
|
||||
#5 clk = !clk;
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user