From 8afd1af0a7764f60af9fca255246af14b7e1e3ad Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@gmail.com>
Date: Thu, 26 Oct 2017 17:07:37 +0200
Subject: [PATCH] update DE0 readme.md

---
 boards/Digilent DE0/README.md         | 15 +++++++++++++++
 verilog/speech256_top/speech256_top.v |  5 ++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/boards/Digilent DE0/README.md b/boards/Digilent DE0/README.md
index e57f316..52c6360 100644
--- a/boards/Digilent DE0/README.md	
+++ b/boards/Digilent DE0/README.md	
@@ -1,3 +1,18 @@
 ## Digilent DE0 board
 
 * Altera EP3C16F484C6 FPGA
+
+The DAC output is the UART_TX pin. It _really_ needs a 5kHz lowpass filter, otherwise you'll be deafened/greeted by a very loud 10kHz PWM carrier. Try a 330 ohm series resistor, followed by a 100nF capacitor to ground:
+
+```
+
+
+UART_TX pin ----RRRRR---------o OUTPUT
+                           |
+                           C
+                           C
+                           C
+                           |
+                          GND
+
+```
\ No newline at end of file
diff --git a/verilog/speech256_top/speech256_top.v b/verilog/speech256_top/speech256_top.v
index f7801cf..ee8c6eb 100644
--- a/verilog/speech256_top/speech256_top.v
+++ b/verilog/speech256_top/speech256_top.v
@@ -72,6 +72,9 @@ module SPEECH256_TOP (
         .done       (src_strobe)
     );
 
+    // Note: the sigma-delta DAC sounds bad because it needs
+    //       an interpolator/lowpass filter at the input.
+    //       
     `ifdef USE_SDDAC
     SD2DAC u_sd2dac (
         .clk        (clk),
@@ -84,7 +87,7 @@ module SPEECH256_TOP (
     PWMDAC u_pwmdac (
         .clk        (clk),
         .rst_an     (rst_an),
-        .din        (sig_filter[11:4]), // add +24dB gain .. FIXME: add saturation ??
+        .din        (sig_filter[12:5]), // add +18dB gain .. FIXME: add saturation ??
         .din_ack    (pwmdac_ack),
         .dacout     (pwm_out)
     );