From 8e3de97977a96fd1ed77295bfced9dbc2eead200 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@gmail.com>
Date: Tue, 10 Oct 2017 00:25:52 +0200
Subject: [PATCH] 8-bit PWM dac

---
 verilog/pwmdac/pwmdac.v    | 70 ++++++++++++++++++++++++++++++++++++++
 verilog/pwmdac/pwmdac_tb.v | 37 ++++++++++++++++++++
 verilog/pwmdac/run_tb.bat  |  5 +++
 3 files changed, 112 insertions(+)
 create mode 100644 verilog/pwmdac/pwmdac.v
 create mode 100644 verilog/pwmdac/pwmdac_tb.v
 create mode 100644 verilog/pwmdac/run_tb.bat

diff --git a/verilog/pwmdac/pwmdac.v b/verilog/pwmdac/pwmdac.v
new file mode 100644
index 0000000..e3d5fb6
--- /dev/null
+++ b/verilog/pwmdac/pwmdac.v
@@ -0,0 +1,70 @@
+// 
+// Very simple, i.e. 8-bit non noise-shaping pulse-width modulation (PWM) DAC.
+// The DAC has a pull interface.
+//
+// Niels Moseley - Moseley Instruments 2017
+// http://www.moseleyinstruments.com
+//
+
+module PWMDAC (
+        clk, 
+        rst_an, 
+        din, 
+        din_ack, 
+        dacout
+    );
+
+	//////////// CLOCK //////////
+	input clk;
+
+    //////////// RESET, ACTIVE LOW //////////
+    input rst_an;
+
+	//////////// DAC OUTPUT //////////
+	output reg dacout;
+
+	//////////// DATA BUS //////////
+	input signed [7:0] din;
+    output reg din_ack;             // is high for 1 clock cycle after reading the din signal
+
+
+    // internal counter and data registers
+    reg signed [7:0] counter;
+    reg signed [7:0] data;
+
+    always @(posedge clk, negedge rst_an)
+    begin
+        if (rst_an == 0)
+        begin
+            // reset values
+            counter <= 0;
+            dacout  <= 0;
+            din_ack <= 0;
+            data    <= 0;
+        end
+        else
+        begin
+            // increment counter
+            counter <= counter + 8'b00000001;
+
+            // compare counter with data 
+            // and set output accordingly.
+            if (data > counter)
+                dacout <= 1;
+            else
+                dacout <= 0;
+
+            // load new data into DAC when
+            // counter is 255
+            if (counter == 8'h7F)
+            begin
+                data <= din;
+                din_ack <= 1;        
+            end
+            else
+                din_ack <= 0;
+            
+        end
+    end
+
+endmodule
diff --git a/verilog/pwmdac/pwmdac_tb.v b/verilog/pwmdac/pwmdac_tb.v
new file mode 100644
index 0000000..b0eba6c
--- /dev/null
+++ b/verilog/pwmdac/pwmdac_tb.v
@@ -0,0 +1,37 @@
+// 
+// PWMDAC testbench
+//
+// Niels Moseley - Moseley Instruments 2017
+// http://www.moseleyinstruments.com
+//
+
+module PWMDAC_TB;
+    reg clk, rst_an; 
+    reg signed [0:7] din;
+    wire dacout, din_ack;
+
+    PWMDAC u_pwmdac (
+        .clk     (clk),
+        .rst_an  (rst_an),
+        .din     (din),
+        .din_ack (din_ack),
+        .dacout  (dacout)
+    );
+
+    initial
+    begin
+        $dumpfile ("pwmdac.vcd");
+        $dumpvars;
+        clk = 0;
+        rst_an = 0;
+        din = 0;
+        #3
+        rst_an = 1;
+        #10240      
+        $finish;
+    end
+
+    always
+        #5 clk = !clk;
+
+endmodule
\ No newline at end of file
diff --git a/verilog/pwmdac/run_tb.bat b/verilog/pwmdac/run_tb.bat
new file mode 100644
index 0000000..e5aef66
--- /dev/null
+++ b/verilog/pwmdac/run_tb.bat
@@ -0,0 +1,5 @@
+mkdir bin
+C:\iverilog\bin\iverilog -o bin\pwmdac.vvp -g2005 -s PWMDAC_TB pwmdac.v pwmdac_tb.v
+cd bin
+C:\iverilog\bin\vvp pwmdac.vvp
+cd ..