mirror of
https://github.com/trcwm/Speech256.git
synced 2025-06-07 16:48:32 +02:00
Added 2nd order sigma-delta DAC. Added changes suggested by Clifford Wolf.
This commit is contained in:
Niels Moseley
parent
45afdd3500
commit
a2432a5e55
@ -75,16 +75,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
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set_global_assignment -name PIN_FILE Speech256_de0.pin
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set_global_assignment -name VERILOG_FILE speech256_de0.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/xlat.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/ctrlrom.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/controller.v
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set_global_assignment -name VERILOG_FILE ../../verilog/filter/filter.v
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set_global_assignment -name VERILOG_FILE ../../verilog/pwmdac/pwmdac.v
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set_global_assignment -name VERILOG_FILE ../../verilog/source/source.v
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set_global_assignment -name VERILOG_FILE ../../verilog/spmul/spmul.v
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set_global_assignment -name VERILOG_FILE ../../verilog/speech256_top/speech256_top.v
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set_location_assignment PIN_B1 -to LEDG[9]
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set_location_assignment PIN_B2 -to LEDG[8]
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set_location_assignment PIN_C2 -to LEDG[7]
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@ -337,4 +327,15 @@ set_location_assignment PIN_C3 -to DRAM_ADDR[3]
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set_location_assignment PIN_B3 -to DRAM_ADDR[2]
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set_location_assignment PIN_A3 -to DRAM_ADDR[1]
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set_location_assignment PIN_C4 -to DRAM_ADDR[0]
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set_global_assignment -name PIN_FILE Speech256_de0.pin
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set_global_assignment -name VERILOG_FILE speech256_de0.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/xlat.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/ctrlrom.v
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set_global_assignment -name VERILOG_FILE ../../verilog/controller/controller.v
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set_global_assignment -name VERILOG_FILE ../../verilog/filter/filter.v
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set_global_assignment -name VERILOG_FILE ../../verilog/pwmdac/pwmdac.v
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set_global_assignment -name VERILOG_FILE ../../verilog/source/source.v
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set_global_assignment -name VERILOG_FILE ../../verilog/spmul/spmul.v
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set_global_assignment -name VERILOG_FILE ../../verilog/sd2dac/sd2dac.v
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set_global_assignment -name VERILOG_FILE ../../verilog/speech256_top/speech256_top.v
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -5,6 +5,8 @@
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// http://www.moseleyinstruments.com
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//
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`define USE_SDDAC
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module Speech256_DE0 (
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CLOCK_50,
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SW,
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@ -25,6 +27,10 @@ module Speech256_DE0 (
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reg [3:0] divcnt; // clock divider counter
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reg [2:0] cur_state, next_state;
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reg [2:0] rom_addr;
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reg [5:0] rom_data;
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reg inc_rom_addr;
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// debug signals for 16-bit DAC
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wire sample_stb;
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wire signed [15:0] sample_out;
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@ -36,7 +42,7 @@ module Speech256_DE0 (
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.clk (clk),
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.rst_an (rst_an),
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.ldq (ldq),
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.data_in (SW),
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.data_in (rom_data),
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.data_stb (data_stb),
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.pwm_out (UART_TXD),
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.sample_out (sample_out),
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@ -67,6 +73,8 @@ module Speech256_DE0 (
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always @(posedge clk)
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begin
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cur_state <= next_state;
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if (inc_rom_addr == 1)
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rom_addr <= rom_addr + 1;
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end
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//assign LEDG[9:0] = sample_out[15:6];
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@ -74,18 +82,23 @@ module Speech256_DE0 (
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assign LEDG[1] = ldq;
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assign LEDG[2] = SW[2];
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assign LEDG[3] = SW[3];
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assign LEDG[4] = 0;
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always @(*)
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begin
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// FSM defaults
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data_stb <= 0;
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inc_rom_addr <= 0;
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next_state <= cur_state;
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case(cur_state)
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S_IDLE:
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begin
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if ((ldq == 1) && (BUTTON[0] == 1))
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begin
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inc_rom_addr <= 1;
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next_state <= S_ALLOPHONE;
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end
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else
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next_state <= S_IDLE;
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end
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@ -97,13 +110,45 @@ module Speech256_DE0 (
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S_WAITDONE:
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begin
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if (ldq == 0)
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begin
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inc_rom_addr <= 1;
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next_state <= S_IDLE;
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end
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end
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default:
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begin
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next_state <= S_IDLE;
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end
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endcase
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// allophone ROM
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// hello, world
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case (rom_addr)
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3'd0:
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rom_data <= 6'h1B;
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3'd1:
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rom_data <= 6'h07;
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3'd2:
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rom_data <= 6'h2D;
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3'd3:
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rom_data <= 6'h35;
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3'd4:
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rom_data <= 6'h03;
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3'd5:
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rom_data <= 6'h2E;
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3'd6:
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rom_data <= 6'h1E;
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3'd7:
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rom_data <= 6'h33;
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3'd8:
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rom_data <= 6'h2D;
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3'd9:
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rom_data <= 6'h15;
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3'd10:
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rom_data <= 6'h03;
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default:
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rom_data <= 6'h00;
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endcase
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end
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endmodule
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@ -89,13 +89,13 @@ module CONTROLLER (
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.en (rom_en)
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);
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parameter ROM_ADDR_ZERO = 3'b000, // zero the ROM address
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localparam ROM_ADDR_ZERO = 3'b000, // zero the ROM address
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ROM_ADDR_INC = 3'b001, // increment the ROM address
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ROM_ADDR_JMP = 3'b010, // jump to code
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ROM_ADDR_ALLO = 3'b011, // read allophone jump address
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ROM_ADDR_NOP = 3'b100;
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parameter COEFF_CNT_ZERO = 2'b00, // zero coefficient counter
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localparam COEFF_CNT_ZERO = 2'b00, // zero coefficient counter
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COEFF_CNT_NOP = 2'b01, // do nothing
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COEFF_CNT_INC = 2'b10; // increment coefficient counter
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@ -192,7 +192,7 @@ module CONTROLLER (
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assign serve_next_allo_data = (dur_cnt == duration) ? 1 : 0;
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parameter S_IDLE = 4'd0,
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localparam S_IDLE = 4'd0,
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S_JMPADDR1 = 4'd1,
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S_JMPADDR2 = 4'd2,
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S_JMPADDR3 = 4'd3,
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@ -20,6 +20,7 @@ module FILTER (
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start, // trigger processing of the input signal
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done // goes to '1' when sig_out has valid data
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);
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parameter DEBUG = 0; //defult value
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//////////// CLOCK //////////
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@ -179,7 +180,7 @@ module FILTER (
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end
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// FSM states
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parameter S_IDLE = 4'b0000,
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localparam S_IDLE = 4'b0000,
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S_DUMMY1 = 4'b0001,
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S_WAITMUL1 = 4'b0010,
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S_UPDATEC1 = 4'b0011,
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6
verilog/sd2dac/run_tb.bat
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6
verilog/sd2dac/run_tb.bat
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@ -0,0 +1,6 @@
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mkdir bin
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del bin\sd2dac.vvp
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C:\iverilog\bin\iverilog -o bin\sd2dac.vvp -m va_math -g2005 -s SD2DAC_TB sd2dac.v sd2dac_tb.v
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cd bin
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C:\iverilog\bin\vvp sd2dac.vvp
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cd ..
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132
verilog/sd2dac/sd2dac.v
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132
verilog/sd2dac/sd2dac.v
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@ -0,0 +1,132 @@
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//
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// Second-order sigma-delta DAC
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// The DAC has a pull interface.
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//
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// Number of input bits used: 12
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//
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// Niels Moseley - Moseley Instruments 2017
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// http://www.moseleyinstruments.com
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//
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//
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// Designed for a clock rate of 2.5 MHz
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//
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module SD2DAC (
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clk,
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rst_an,
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din, // 16 bit signed data input
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din_ack, // is high for 1 clock cycle after reading the din signal
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dacout // 1-bit SD output signal
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);
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input signed [15:0] din;
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input rst_an, clk;
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output reg din_ack;
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output reg dacout;
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reg [15:0] din_reg; // data input register
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reg [15:0] last_din; // previous input sample
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//reg [15:0] delta;
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reg [7:0] counter; // sample counter
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reg signed [15:0] state1, state2; // integrator states
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reg signed [15:0] new_state1, new_state2;
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reg signed [15:0] state1_in, state2_in; // input to integrators
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wire signed [15:0] state1_a, state2_a; // output of integrator adders
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wire signed [16:0] quant_in;
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reg quant_out;
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always @(posedge clk or negedge rst_an)
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begin
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if (rst_an == 0)
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begin
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state1 <= 0;
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state2 <= 0;
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counter <= 0;
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din_reg <= 0;
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end
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else
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begin
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// clocked process
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state1 <= new_state1;
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state2 <= new_state2;
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dacout <= quant_out;
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counter <= counter + 1;
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if (din_ack == 1)
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begin
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last_din <= din_reg;
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din_reg <= {din[15], din[15:1]}; // div by 2!
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end
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end
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end
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assign state1_a = state1 + state1_in;
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assign state2_a = state2 + state2_in;
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assign quant_in = $signed( { {3{din_reg[15]}}, din_reg[15:2]} ) + state2;
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always @(*)
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begin
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// ------------------------------
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// calculate new state 1
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// ------------------------------
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if (quant_out == 1)
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// (din >> 2) - (quant_out >> 2)
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state1_in <= $signed( { {2{din_reg[15]}}, din_reg[15:2]} ) - $signed(16'h1FFF);
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else
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state1_in <= $signed( { {2{din_reg[15]}}, din_reg[15:2]} ) + $signed(16'h1FFF);
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// check for saturation:
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// if operand sign bits are the same
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// the result should have the same
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// sign bit, if not, we need to
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// saturate.
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//
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// 1000 + 1111 => 1000 (-8 + -1 saturates at -8)
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// 0111 + 0001 => 0111 (7 + 1 saturates at 7)
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//
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if (state1[15] == state1_in[15])
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begin
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if (state1[15] != state1_a[15])
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new_state1 <= state1[15] ? 16'h8000 : 16'h7FFF;
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else
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new_state1 <= state1_a;
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end
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else
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new_state1 <= state1_a;
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// ------------------------------
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// calculate new state 2
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// ------------------------------
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if (quant_out == 1)
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// state1 - (quant_out >> 1)
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state2_in <= state1 - $signed(16'h3FFF);
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else
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state2_in <= state1 + $signed(16'h3FFF);
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if (state2[15] == state2_in[15])
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begin
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if (state2[15] != state2_a[15])
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new_state2 <= state2[15] ? 16'h8000 : 16'h7FFF;
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else
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new_state2 <= state2_a;
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end
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else
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new_state2 <= state2_a;
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// ------------------------------
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// calculate quantizer
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// ------------------------------
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quant_out <= !quant_in[16];
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if (counter == 8'h0)
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din_ack <= 1;
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else
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din_ack <= 0;
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end
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endmodule
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59
verilog/sd2dac/sd2dac_tb.v
Normal file
59
verilog/sd2dac/sd2dac_tb.v
Normal file
@ -0,0 +1,59 @@
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//
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// PWMDAC testbench
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//
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// Niels Moseley - Moseley Instruments 2017
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// http://www.moseleyinstruments.com
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//
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module SD2DAC_TB;
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reg clk, rst_an;
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reg signed [15:0] din;
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wire dacout, din_ack;
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real accu;
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SD2DAC u_sd2dac (
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.clk (clk),
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.rst_an (rst_an),
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.din (din),
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.din_ack (din_ack),
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.dacout (dacout)
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);
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integer fd;
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initial
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begin
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fd = $fopen("dacout.sw","wb");
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$dumpfile ("sd2dac.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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din = 0;
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accu = 0;
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#3
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rst_an = 1;
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#1048576
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$fclose(fd);
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$finish;
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end
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always @(posedge clk)
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begin
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if (din_ack)
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begin
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accu = accu + 1.0/256.0;
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if (accu > 1.0)
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accu = -1.0;
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din = $rtoi($sin(2.0*3.1415927*accu)*10000.0);
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end
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if (dacout == 1)
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$fwrite(fd,"%u", 32'h7000_0000);
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else
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$fwrite(fd,"%u", 32'h9000_0000);
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end
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always
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#5 clk = !clk;
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endmodule
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19
verilog/sd2dac/show_tb_results.m
Normal file
19
verilog/sd2dac/show_tb_results.m
Normal file
@ -0,0 +1,19 @@
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%
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% Show testbench results for sd2dac
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%
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% This is a MATLAB file
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%
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fileID = fopen('bin/dacout.sw');
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A = fread(fileID,'*int32')';
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fclose(fileID);
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A = single(A)/2^31;
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clf;
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figure(1);
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X = fft(A.*blackman(length(A))') / (length(A)/4);
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semilogx(20*log10(abs(X)));
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grid on;
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axis([0 length(X)/2 -140 10]);
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@ -72,14 +72,23 @@ module SPEECH256_TOP (
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.done (src_strobe)
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);
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`ifdef USE_SDDAC
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SD2DAC u_sd2dac (
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.clk (clk),
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.rst_an (rst_an),
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.din ($signed({sig_filter[11:0],4'h0})), // add +24dB gain .. FIXME: add saturation ??
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.din_ack (pwmdac_ack),
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.dacout (pwm_out)
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);
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`else
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PWMDAC u_pwmdac (
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.clk (clk),
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.rst_an (rst_an),
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//.din (sig_filter[15:8]),
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.din (sig_filter[11:4]), // add +24dB gain .. FIXME: add saturation ??
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.din_ack (pwmdac_ack),
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.dacout (pwm_out)
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);
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`endif
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CONTROLLER u_controller (
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.clk (clk),
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