diff --git a/doc/filter_engine.ipe b/doc/filter_engine.ipe index c91e909..826d99f 100644 --- a/doc/filter_engine.ipe +++ b/doc/filter_engine.ipe @@ -1,7 +1,7 @@ - + @@ -344,221 +344,19 @@ h output input - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -56 712 m -168 712 l - -shift reg - - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -56 712 m -168 712 l - -shift reg - -$a_1$-states +$a_1$-states $a_2$-states 176 728 m 208 728 l -328 624 m -328 608 l -296 608 l -296 584 l -312 584 l - - 192 632 m 192 568 l 312 568 l - -296 468 m -32 468 l -32 632 l -48 632 l - - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -48 736 m -48 720 l -64 720 l -64 736 l -h - - -56 712 m -168 712 l - -shift reg - coefficients 336 712 m @@ -566,31 +364,228 @@ h 376 576 l 360 576 l - + 176 736 m 192 728 l 192 696 l 176 688 l h - + 192 712 m 208 712 l -1 - -376 672 m -160 672 l -160 696 l -176 696 l - -0 +1 +0 - + 176 720 m 160 720 l 144 720 l -coeff\_in +coeff\_in + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +56 712 m +168 712 l + +shift reg + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +56 712 m +168 712 l + +shift reg + +296 468 m +64 468 l +64 632 l +80 632 l + + +304 632 m +320 632 l +320 608 l +296 608 l +296 584 l +312 584 l + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +56 712 m +168 712 l + +shift reg + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +48 736 m +48 720 l +64 720 l +64 736 l +h + + +376 672 m +96 672 l +96 696 l +112 696 l + diff --git a/verilog/filter/filter.v b/verilog/filter/filter.v index 6a923ff..e66c78e 100644 --- a/verilog/filter/filter.v +++ b/verilog/filter/filter.v @@ -6,11 +6,6 @@ // http://www.moseleyinstruments.com // -// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -// NO, NO, NO, NO, NO, NO, NO, NO, NO, NO, NO, NO, NO, NO, .. -// this is all arse-backwards as fuck .. -// we should use a shift register for states + coefficients!! -// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! module FILTER ( clk, @@ -52,6 +47,7 @@ module FILTER ( reg state_sel; reg accu_sel; reg do_accu; + reg double_mode; reg update_states; reg update_coeffs; reg [3:0] cur_state; @@ -80,6 +76,7 @@ module FILTER ( assign mul_coeff = coefmem[11]; assign sig_out = accu; + // clocked stuff.. always @(posedge clk, negedge rst_an) begin if (rst_an == 0) @@ -102,6 +99,7 @@ module FILTER ( accu_sel <= 0; state_sel <= 0; do_accu <= 0; + double_mode <= 0; update_states <= 0; update_coeffs <= 0; @@ -149,7 +147,10 @@ module FILTER ( // update the accumulator if necessary if (do_accu) begin - accu <= accu_in + mul_result; + if (double_mode) + accu <= accu_in +{mul_result[14:0], 1'b0}; + else + accu <= accu_in + mul_result; end // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! @@ -162,6 +163,7 @@ module FILTER ( mul_start <= 0; state_sel <= 0; accu_sel <= 0; + double_mode <= 0; update_states <= 0; update_coeffs <= 0; case(cur_state) @@ -181,11 +183,6 @@ module FILTER ( // to reach a valid state begin cur_state <= 4'b0010; - //for(i=0; i<6; i=i+1) - //begin - // $display("s1[%d] = %x", i, state1[i]); - // $display("s2[%d] = %x", i, state2[i]); - //end end 4'b0010: // wait for multiplier to complete begin @@ -194,6 +191,7 @@ module FILTER ( cur_state <= 4'b0011; accu_sel <= 0; // accu = sig_in + mul_result do_accu <= 1; + double_mode <= 1; // a1 coefficient has double the weight end end 4'b0011: // update accu, 1st section only! @@ -252,6 +250,7 @@ module FILTER ( cur_state <= 4'b1011; accu_sel <= 1; // accu = accu + mul_result do_accu <= 1; + double_mode <= 1; // a1 coefficient has double the weight end end 4'b1011: // update accu, 2nd..5th section only! diff --git a/verilog/filter/filter_tb.v b/verilog/filter/filter_tb.v index 1d72da7..ed09378 100644 --- a/verilog/filter/filter_tb.v +++ b/verilog/filter/filter_tb.v @@ -46,7 +46,7 @@ module FILTER_TB; #10 coef_load = 1; // section 1 - coef_in = {1'b0, 9'd128}; // sign-magnitude a1 = -0.25 + coef_in = {1'b0, 9'd64}; // sign-magnitude a1 = -0.25 #10 coef_in = {1'b1, 9'd256}; // sign-magnitude a2 = 0.5 #10 diff --git a/verilog/filter/results.md b/verilog/filter/results.md index 3b3760e..acc0593 100644 --- a/verilog/filter/results.md +++ b/verilog/filter/results.md @@ -31,4 +31,4 @@ The testbench should approximately give the following step response results: - 205 - 205 -Note that there might be a few +/- 1 round-off errors. +Note that may be a few +/- 1 round-off errors.