mirror of
https://github.com/trcwm/Speech256.git
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80 lines
1.9 KiB
Verilog
80 lines
1.9 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Controller testbench
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//
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module CONTROLLER_TB;
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reg clk, rst_an;
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reg [5:0] data_in;
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reg data_stb, serve_next;
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reg period_done;
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wire clear_states;
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wire ldq;
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wire [9:0] coeff;
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wire coeff_load;
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wire [7:0] period;
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wire [15:0] amp;
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wire [7:0] dur;
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CONTROLLER u_controller (
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.clk (clk),
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.rst_an (rst_an),
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.ldq (ldq),
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.data_in (data_in),
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.data_stb (data_stb),
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.period_out (period),
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.amp_out (amp),
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.coeff_out (coeff),
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.coeff_stb (coeff_load),
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.clear_states (clear_states),
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.period_done_in (period_done)
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);
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initial
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begin
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$dumpfile ("controller.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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data_in = 6;
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data_stb = 0;
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period_done = 0;
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#5
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rst_an = 1;
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#5
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// load allophone
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data_stb = 1;
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#10
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data_stb = 0;
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serve_next = 1;
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#300000
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$finish;
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end
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always @(posedge clk)
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begin
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;
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end
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always
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#5 clk = !clk;
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endmodule
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