mirror of
https://github.com/trcwm/Speech256.git
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55 lines
1.5 KiB
Verilog
55 lines
1.5 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// 8-bit sign-magnitude to 10-bit sign-magnitude
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// conversion block
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//
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//
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// C1: x*8
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// C2: 301 + (x-38)*4 = 301 - 152 + x*4 = 149 + x*4
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// C3: 425 + (x-69)*2 = 425 - 138 + x*2 = 287 + x*2
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// C4: 481 + (x-97) = 481 - 97 + x = 384 + x
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//
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//
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//
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//
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module XLAT (
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c8_in,
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c10_out
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);
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input [7:0] c8_in;
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output reg [9:0] c10_out;
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wire sign;
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assign sign = ~c8_in[7];
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always@(*)
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begin
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if (c8_in[6:0] < 38)
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c10_out <= {sign, c8_in[5:0], 3'b000};
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else if (c8_in[6:0] < 69)
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c10_out <= {sign, {c8_in[6:0], 2'b00} + 9'd149};
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else if (c8_in[6:0] < 97)
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c10_out <= {sign, {{1'b0, c8_in[6:0]}, 1'b0} + 9'd287};
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else
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c10_out <= {sign, {{2'b00, c8_in[6:0]} + 9'd384}};
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end
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endmodule
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