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45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// XLAT testbench
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//
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module XLAT_TB;
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reg [7:0] c8_in;
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wire [9:0] c10_out;
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XLAT u_xlat (
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c8_in,
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c10_out
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);
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integer i;
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initial
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begin
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$dumpfile ("xlat.vcd");
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$dumpvars;
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c8_in[7] = 0;
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for(i=0; i<128; i=i+1)
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begin
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c8_in[6:0] = i;
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#10;
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end
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$finish;
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end
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endmodule
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