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https://github.com/trcwm/Speech256.git
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122 lines
3.5 KiB
Verilog
122 lines
3.5 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Very simple, i.e. 8-bit non noise-shaping pulse-width modulation (PWM) DAC.
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// The DAC has a pull interface.
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//
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// For a 10 kHz output rate, the clock rate should be 2.560 MHz
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//
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//`define USE_PREFILTER
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module PWMDAC (
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clk,
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rst_an,
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din, // 16 bit signed data input
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din_ack, // is high for 1 clock cycle after reading the din signal
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dacout // 1-bit PWM output signal
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);
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//////////// CLOCK //////////
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input clk;
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//////////// RESET, ACTIVE LOW //////////
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input rst_an;
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//////////// DAC OUTPUT //////////
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output reg dacout;
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//////////// DATA BUS //////////
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input signed [7:0] din;
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output reg din_ack; // is high for 1 clock cycle after reading the din signal
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// internal counter and data registers
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reg signed [7:0] counter;
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reg signed [7:0] data;
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// pre-emphasis filter
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reg signed [7:0] last_data;
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wire signed [10:0] sum1;
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// 7- bit signed quantization input
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// so we now have 20kHz carrier instead of 10kHz
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// ..
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reg signed [6:0] quantdata;
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assign sum1 = $signed({data[7] ,{data, 2'b00}}) + data - $signed({last_data, 2'b00});
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// output saturation
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always @(*)
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begin
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if (sum1[10] ^ sum1[9] != 0)
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begin
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// saturation needed
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quantdata = sum1[10] ? 8'h80 : 8'h7F;
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end
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else
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quantdata = sum1[9:3];
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end
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always @(posedge clk, negedge rst_an)
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begin
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if (rst_an == 0)
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begin
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// reset values
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counter <= 0;
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dacout <= 0;
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din_ack <= 0;
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data <= 0;
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end
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else
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begin
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// increment counter
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counter <= counter + 8'b00000001;
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// compare counter with data
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// and set output accordingly.
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//
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// Note, we use 7 bits of the counter
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// as a PWM waveform to get 2x 10 kHz carrier wave
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// but the counter itself needs to be 8 bits
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// so the sample rate is still 10ksps!
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`ifdef USE_PREFILTER
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if (quantdata > $signed(counter[6:0]))
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dacout <= 1;
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else
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dacout <= 0;
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`else
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if ($signed(data[7:1]) > $signed(counter[6:0]))
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dacout <= 1;
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else
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dacout <= 0;
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`endif
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// load new data into DAC when
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// counter is 127
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if (counter == 8'h7F)
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begin
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last_data <= data;
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data <= din;
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din_ack <= 1;
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end
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else
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din_ack <= 0;
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end
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end
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endmodule
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