mirror of
https://github.com/trcwm/Speech256.git
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81 lines
1.9 KiB
Verilog
81 lines
1.9 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// PWMDAC testbench
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//
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module SOURCE_TB;
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reg clk, rst_an, strobe;
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reg signed [14:0] amp;
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reg [7:0] period;
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reg [7:0] cnt;
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wire signed [15:0] source_out;
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wire period_done;
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SOURCE u_source (
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.clk (clk),
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.rst_an (rst_an),
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.period (period),
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.amplitude (amp),
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.strobe (strobe),
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.period_done (period_done),
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.source_out (source_out)
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);
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integer fd; // file descriptor
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initial
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begin
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fd = $fopen("audio.sw","wb");
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$dumpfile ("source.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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strobe = 0;
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period = 50;
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amp = 15000;
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cnt = 0;
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#3
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rst_an = 1;
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#300000
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period = 0; // switch to noise mode
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#300000
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$fclose(fd);
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$finish;
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end
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always @(posedge clk)
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begin
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if (cnt == 4)
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begin
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cnt <= 0;
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strobe <= 1;
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$fwrite(fd,"%u",{ {16{source_out[15]}} ,source_out});
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end
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else
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begin
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strobe <= 0;
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cnt <= cnt + 1;
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end
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end
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always
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#5 clk = !clk;
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endmodule |