mirror of
https://github.com/trcwm/Speech256.git
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120 lines
3.1 KiB
Verilog
120 lines
3.1 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Speech256 top level testbench
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//
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module SPEECH256_TOP_TB;
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reg clk, rst_an;
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reg [5:0] data_in;
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reg data_stb;
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wire sample_stb;
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wire signed [15:0] sample_out;
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wire ldq,pwm_out;
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reg [7:0] allophones[0:10];
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reg [3:0] allo_idx;
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SPEECH256_TOP u_speech256_top (
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.clk (clk),
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.rst_an (rst_an),
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.ldq (ldq),
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.data_in (data_in),
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.data_stb (data_stb),
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.pwm_out (pwm_out),
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.sample_out (sample_out),
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.sample_stb (sample_stb)
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);
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integer fd; // file descriptor
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initial
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begin
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`ifdef HELLOWORLD
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// hello, world
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allophones[0] = 6'h1B;
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allophones[1] = 6'h07;
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allophones[2] = 6'h2D;
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allophones[3] = 6'h35;
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allophones[4] = 6'h03;
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allophones[5] = 6'h2E;
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allophones[6] = 6'h1E;
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allophones[7] = 6'h33;
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allophones[8] = 6'h2D;
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allophones[9] = 6'h15;
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allophones[10] = 6'h03;
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allophones[11] = 6'h00;
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`else
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// E.T. phone
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allophones[0] = 6'h13;
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allophones[1] = 6'h02;
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allophones[2] = 6'h0D;
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allophones[3] = 6'h13;
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allophones[4] = 6'h03;
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allophones[5] = 6'h00;
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allophones[6] = 6'h00;
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allophones[7] = 6'h00;
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allophones[8] = 6'h00;
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allophones[9] = 6'h00;
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allophones[10] = 6'h00;
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allophones[11] = 6'h00;
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`endif
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fd = $fopen("dacout.sw","wb");
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$dumpfile ("speech256_top.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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allo_idx = 0;
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#5
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rst_an <= 1;
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//#5
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//#9000000
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//$fclose(fd);
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//$finish;
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end
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reg last_sample_stb;
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always @(posedge clk)
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begin
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// check for new output sample
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if ((sample_stb == 1) && (last_sample_stb != sample_stb))
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begin
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$fwrite(fd,"%u", $signed( {sample_out, 16'h0000} ));
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end
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last_sample_stb <= sample_stb;
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// check for next allophone
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if ((ldq == 1) && (data_stb == 0))
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begin
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data_stb <= 1;
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data_in <= allophones[allo_idx];
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$display("Allophone %d", allo_idx);
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allo_idx <= allo_idx + 1;
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if (allo_idx == 11)
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$finish;
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end
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else
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data_stb <= 0;
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end
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always
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#5 clk = !clk;
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endmodule
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