mirror of
https://github.com/trcwm/Speech256.git
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66 lines
1.6 KiB
Verilog
66 lines
1.6 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// SPMUL testbench
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//
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module SPMUL_TB;
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reg clk, rst_an, start;
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reg signed [15:0] sig;
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reg signed [9:0] coef;
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wire signed [15:0] result;
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wire done;
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SPMUL u_spmul (
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.clk (clk),
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.rst_an (rst_an),
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.sig_in (sig),
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.coef_in (coef),
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.result_out (result),
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.start (start),
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.done (done)
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);
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initial
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begin
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$dumpfile ("spmul.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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sig = 16'h7FFF;
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coef = 10'h3FF; // sign-magnitude
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start = 1;
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#3
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rst_an = 1;
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#10
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start = 0;
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#1024;
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end
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always
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#5 clk = !clk;
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always @(posedge done)
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begin
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if ((done == 1) && (start == 0))
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begin
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$display("Expected: %d, got %d", -32703 , result);
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$finish;
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end
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end
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endmodule
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