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60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
// 7-segment display driver for DE0 board
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//
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// Niels Moseley - Moseley Instruments 2017
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// http://www.moseleyinstruments.com
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//
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module segmentdisplay (
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clk,
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latch,
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hexdigit_in,
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display_out
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);
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input clk,latch;
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input [3:0] hexdigit_in;
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output reg [0:6] display_out;
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always @(posedge clk)
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begin
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if (latch == 1)
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begin
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case (hexdigit_in)
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4'b0000:
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display_out <= 7'b1000000;
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4'b0001:
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display_out <= 7'b1111001;
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4'b0010:
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display_out <= 7'b0100100;
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4'b0011:
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display_out <= 7'b0110000;
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4'b0100:
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display_out <= 7'b0011001;
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4'b0101:
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display_out <= 7'b0010010;
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4'b0110:
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display_out <= 7'b0000010;
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4'b0111:
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display_out <= 7'b1111000;
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4'b1000:
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display_out <= 7'b0000000;
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4'b1001:
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display_out <= 7'b0011000;
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4'b1010:
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display_out <= 7'b0001000;
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4'b1011:
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display_out <= 7'b0000011;
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4'b1100:
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display_out <= 7'b1000110;
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4'b1101:
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display_out <= 7'b0100001;
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4'b1110:
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display_out <= 7'b0000110;
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4'b1111:
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display_out <= 7'b0001110;
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endcase
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end
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end
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endmodule
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