mirror of
https://github.com/trcwm/Speech256.git
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73 lines
1.7 KiB
Verilog
73 lines
1.7 KiB
Verilog
// SPEECH 256
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// Copyright (C) 2017 Niels Moseley / Moseley Instruments
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// http://www.moseleyinstruments.com
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// PWMDAC testbench
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//
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module SD2DAC_TB;
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reg clk, rst_an;
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reg signed [15:0] din;
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wire dacout, din_ack;
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real accu;
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SD2DAC u_sd2dac (
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.clk (clk),
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.rst_an (rst_an),
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.din (din),
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.din_ack (din_ack),
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.dacout (dacout)
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);
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integer fd;
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initial
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begin
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fd = $fopen("dacout.sw","wb");
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$dumpfile ("sd2dac.vcd");
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$dumpvars;
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clk = 0;
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rst_an = 0;
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din = 0;
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accu = 0;
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#3
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rst_an = 1;
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#1048576
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$fclose(fd);
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$finish;
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end
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always @(posedge clk)
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begin
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if (din_ack)
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begin
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accu = accu + 1.0/256.0;
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if (accu > 1.0)
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accu = -1.0;
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din = $rtoi($sin(2.0*3.1415927*accu)*10000.0);
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end
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if (dacout == 1)
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$fwrite(fd,"%u", 32'h7000_0000);
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else
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$fwrite(fd,"%u", 32'h9000_0000);
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end
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always
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#5 clk = !clk;
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endmodule |