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stm32f3: i2c support increased. Now it works.

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- Several functions added (that only work on the f3)
- The data register now has a 8bit access counter part
  that is necessary for 8bit transmissions, together with
  the access functions.
- The init master functions doesn't work for the f3.
This commit is contained in:
Federico Ruiz Ugalde 2013-06-30 13:56:19 -06:00 committed by Piotr Esden-Tempski
parent 9b2873d874
commit 011124c33f
2 changed files with 61 additions and 1 deletions
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16
include/libopencm3/stm32/common/spi_common_all.h
View File

@ -137,6 +137,11 @@ specific memorymap.h header before including this header file.*/
@{*/
#if defined(STM32F3)
#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
#define SPI1_DR8 SPI_DR8(SPI1_BASE)
#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE)
#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE)
#define SPI_CR1_CRCL_8BIT (0 << 11)
#define SPI_CR1_CRCL_16BIT (1 << 11)
/**@}*/
@ -258,6 +263,7 @@ specific memorymap.h header before including this header file.*/
#define SPI_CR2_DS_14BIT (0xD << 8)
#define SPI_CR2_DS_15BIT (0xE << 8)
#define SPI_CR2_DS_16BIT (0xF << 8)
#define SPI_CR2_DS_MASK (0xF << 8)
/* NSSP: NSS pulse management */
@ -463,6 +469,16 @@ void spi_disable_tx_dma(uint32_t spi);
void spi_enable_rx_dma(uint32_t spi);
void spi_disable_rx_dma(uint32_t spi);
#ifdef STM32F3
void spi_set_data_size(uint32_t spi, uint16_t data_s);
void spi_fifo_reception_threshold_8bit(uint32_t spi);
void spi_fifo_reception_threshold_16bit(uint32_t spi);
void spi_i2s_mode_spi_mode(uint32_t spi);
void spi_send8(uint32_t spi, uint8_t data);
uint8_t spi_read8(uint32_t spi);
#endif
END_DECLS
/**@}*/

46
lib/stm32/common/spi_common_all.c
View File

@ -119,6 +119,8 @@ spi_lsbfirst.
@returns int. Error code.
*/
#ifndef STM32F3
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
uint32_t dff, uint32_t lsbfirst)
{
@ -142,6 +144,8 @@ int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
return 0; /* TODO */
}
#endif
/* TODO: Error handling? */
/*---------------------------------------------------------------------------*/
/** @brief SPI Enable.
@ -394,7 +398,47 @@ void spi_set_next_tx_from_crc(uint32_t spi)
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
#if !defined(STM32F3)
#ifdef STM32F3
void spi_send8(uint32_t spi, uint8_t data)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE));
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR8(spi) = data;
}
uint8_t spi_read8(uint32_t spi)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
return SPI_DR8(spi);
}
void spi_set_data_size(uint32_t spi, uint16_t data_s)
{
SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | (data_s & SPI_CR2_DS_MASK);
}
void spi_fifo_reception_threshold_8bit(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_FRXTH;
}
void spi_fifo_reception_threshold_16bit(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_FRXTH;
}
void spi_i2s_mode_spi_mode(uint32_t spi)
{
SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
}
#else /*STM32F3*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Data Frame Format to 8 bits