jackcartersmith/blackmagic
1
0
Fork 0
Code Issues Pull Requests Releases Activity

stm32f4: dcmi: doc: group register bit defns

Browse Source 
Makes the doxygen much much prettier and easier to follow.
This commit is contained in:
Karl Palsson 2017-10-23 21:30:19 +00:00
parent 3dbcd16ced
commit 0663341244
1 changed files with 54 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
include/libopencm3/stm32/f4/dcmi.h
View File

@ -44,6 +44,11 @@
* DCMI control register 1
*/
#define DCMI_CR MMIO32(DCMI_BASE + 0x0U)
/**
* @defgroup dcmi_cr_values DCMI_CR Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_CR_EN (1 << 14)
#define DCMI_CR_EDM1 (1 << 11)
#define DCMI_CR_EDM0 (1 << 10)
@ -57,6 +62,7 @@
#define DCMI_CR_CROP (1 << 2)
#define DCMI_CR_CM (1 << 1)
#define DCMI_CR_CAPTURE (1 << 0)
/**@}*/
/**
* DCMI status register
@ -71,11 +77,17 @@
* register value.
*/
#define DCMI_RIS MMIO32(DCMI_BASE + 0x08U)
/**
* @defgroup dcmi_ris_values DCMI_RIS Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_RIS_LINE (1 << 4)
#define DCMI_RIS_VSYNC (1 << 3)
#define DCMI_RIS_ERR (1 << 2)
#define DCMI_RIS_OVR (1 << 1)
#define DCMI_RIS_FRAME (1 << 0)
/**@}*/
/**
* DCMI interrupt enable register
@ -84,11 +96,17 @@
* the corresponding interrupt is enabled. This register is accessible in both read and write.
*/
#define DCMI_IER MMIO32(DCMI_BASE + 0x0CU)
/**
* @defgroup dcmi_ier_values DCMI_IER Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_IER_LINE (1 << 4)
#define DCMI_IER_VSYNC (1 << 3)
#define DCMI_IER_ERR (1 << 2)
#define DCMI_IER_OVR (1 << 1)
#define DCMI_IER_FRAME (1 << 0)
/**@}*/
/**
* DCMI masked interrupt status register
@ -99,11 +117,17 @@
* bit in DCMI_RIS is set.
*/
#define DCMI_MIS MMIO32(DCMI_BASE + 0x10U)
/**
* @defgroup dcmi_mis_values DCMI_MIS Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_MIS_LINE (1 << 4)
#define DCMI_MIS_VSYNC (1 << 3)
#define DCMI_MIS_ERR (1 << 2)
#define DCMI_MIS_OVR (1 << 1)
#define DCMI_MIS_FRAME (1 << 0)
/**@}*/
/**
* DCMI interrupt clear register
@ -112,16 +136,27 @@
* corresponding bit in the DCMI_RIS and DCMI_MIS registers. Writing a ‘0’ has no effect.
*/
#define DCMI_ICR MMIO32(DCMI_BASE + 0x14U)
/**
* @defgroup dcmi_icr_values DCMI_ICR Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_ICR_LINE (1 << 4)
#define DCMI_ICR_VSYNC (1 << 3)
#define DCMI_ICR_ERR (1 << 2)
#define DCMI_ICR_OVR (1 << 1)
#define DCMI_ICR_FRAME (1 << 0)
/**@}*/
/**
* DCMI embedded synchronization code register
*/
#define DCMI_ESCR MMIO32(DCMI_BASE + 0x18U)
/**
* @defgroup dcmi_escr_values DCMI_ESCR Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_ESCR_FEC_SHIFT 24
#define DCMI_ESCR_FEC_MASK 0xff
#define DCMI_ESCR_LEC_SHIFT 16
@ -130,12 +165,18 @@
#define DCMI_ESCR_LSC_MASK 0xff
#define DCMI_ESCR_FSC_SHIFT 0
#define DCMI_ESCR_FSC_MASK 0xff
/**@}*/
/**
* DCMI embedded synchronization unmask register
*/
#define DCMI_ESUR MMIO32(DCMI_BASE + 0x1CU)
/**
* @defgroup dcmi_esur_values DCMI_ESUR Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_ESUR_FEU_SHIFT 24
#define DCMI_ESUR_FEU_MASK 0xff
#define DCMI_ESUR_LEU_SHIFT 16
@ -144,24 +185,37 @@
#define DCMI_ESUR_LSU_MASK 0xff
#define DCMI_ESUR_FSU_SHIFT 0
#define DCMI_ESUR_FSU_MASK 0xff
/**@}*/
/**
* DCMI crop window start
*/
#define DCMI_CWSTRT MMIO32(DCMI_BASE + 0x20U)
/**
* @defgroup dcmi_cwstrt_values DCMI_CWSTRT Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_CWSTRT_VST_SHIFT 16
#define DCMI_CWSTRT_VST_MASK 0x1fff
#define DCMI_CWSTRT_HOFFCNT_SHIFT 0
#define DCMI_CWSTRT_HOFFCNT_MASK 0x3fff
/**@}*/
/**
* DCMI crop window size
*/
#define DCMI_CWSIZE MMIO32(DCMI_BASE + 0x24U)
/**
* @defgroup dcmi_cwsize_values DCMI_CWSIZE Values
* @ingroup dcmi_defines
* @{
*/
#define DCMI_CWSIZE_VLINE_SHIFT 16
#define DCMI_CWSIZE_VLINE_MASK 0x3fff
#define DCMI_CWSIZE_CAPCNT_SHIFT 0
#define DCMI_CWSIZE_CAPCNT_MASK 0x3fff
/**@}*/
/**
* DCMI data register