diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index ef7cb413..34517ffa 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -548,6 +548,7 @@ extern uint32_t rcc_apb2_frequency; typedef enum { CLOCK_3V3_48MHZ, + CLOCK_3V3_84MHZ, CLOCK_3V3_120MHZ, CLOCK_3V3_168MHZ, CLOCK_3V3_END diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 25a8d637..e7065053 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -64,6 +64,19 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, + { /* 84MHz */ + .pllm = 8, + .plln = 336, + .pllp = 4, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_2WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, { /* 120MHz */ .pllm = 8, .plln = 240, @@ -108,6 +121,19 @@ const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = { .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, + { /* 84MHz */ + .pllm = 12, + .plln = 336, + .pllp = 4, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_2WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, { /* 120MHz */ .pllm = 12, .plln = 240, @@ -152,6 +178,19 @@ const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = { .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, + { /* 84MHz */ + .pllm = 16, + .plln = 336, + .pllp = 4, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_2WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, { /* 120MHz */ .pllm = 16, .plln = 240, @@ -196,6 +235,19 @@ const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END] = { .apb1_frequency = 12000000, .apb2_frequency = 24000000, }, + { /* 84MHz */ + .pllm = 25, + .plln = 336, + .pllp = 4, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_2WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, { /* 120MHz */ .pllm = 25, .plln = 240,