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sgpio.csv

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This commit is contained in:
Michael Ossmann 2012-09-26 20:55:16 -06:00 committed by Piotr Esden-Tempski
parent ae9a6ae4af
commit 07ee98420c
1 changed files with 304 additions and 0 deletions
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304
scripts/data/lpc43xx/sgpio.csv Normal file
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SGPIO_OUT_MUX_CFG0,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG0,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG1,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG1,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG2,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG2,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG3,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG3,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG4,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG4,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG5,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG5,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG6,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG6,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG7,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG7,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG8,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG8,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG9,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG9,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG10,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG10,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG11,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG11,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG12,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG12,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG13,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG13,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG14,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG14,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_OUT_MUX_CFG15,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG15,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_MUX_CFG0,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG0,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG0,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG0,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG0,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG0,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG0,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG0,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG1,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG1,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG1,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG1,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG1,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG1,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG1,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG1,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG2,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG2,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG2,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG2,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG2,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG2,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG2,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG2,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG3,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG3,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG3,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG3,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG3,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG3,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG3,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG3,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG4,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG4,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG4,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG4,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG4,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG4,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG4,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG4,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG5,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG5,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG5,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG5,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG5,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG5,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG5,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG5,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG6,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG6,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG6,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG6,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG6,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG6,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG6,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG6,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG7,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG7,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG7,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG7,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG7,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG7,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG7,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG7,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG8,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG8,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG8,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG8,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG8,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG8,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG8,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG8,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG9,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG9,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG9,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG9,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG9,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG9,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG9,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG9,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG10,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG10,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG10,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG10,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG10,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG10,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG10,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG10,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG11,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG11,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG11,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG11,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG11,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG11,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG11,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG11,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG12,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG12,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG12,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG12,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG12,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG12,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG12,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG12,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG13,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG13,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG13,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG13,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG13,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG13,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG13,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG13,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG14,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG14,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG14,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG14,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG14,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG14,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG14,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG14,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG15,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG15,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG15,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG15,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG15,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG15,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
SGPIO_MUX_CFG15,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG15,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_SLICE_MUX_CFG0,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG0,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG0,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG0,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG0,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG0,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG0,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG1,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG1,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG1,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG1,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG1,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG1,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG1,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG2,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG2,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG2,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG2,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG2,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG2,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG2,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG3,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG3,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG3,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG3,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG3,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG3,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG3,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG4,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG4,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG4,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG4,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG4,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG4,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG4,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG5,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG5,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG5,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG5,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG5,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG5,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG5,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG6,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG6,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG6,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG6,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG6,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG6,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG6,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG7,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG7,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG7,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG7,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG7,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG7,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG7,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG8,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG8,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG8,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG8,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG8,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG8,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG8,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG9,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG9,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG9,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG9,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG9,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG9,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG9,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG10,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG10,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG10,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG10,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG10,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG10,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG10,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG11,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG11,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG11,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG11,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG11,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG11,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG11,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG12,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG12,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG12,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG12,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG12,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG12,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG12,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG13,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG13,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG13,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG13,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG13,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG13,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG13,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG14,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG14,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG14,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG14,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG14,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG14,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG14,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_SLICE_MUX_CFG15,0,1,MATCH_MODE,Match mode,0,rw
SGPIO_SLICE_MUX_CFG15,1,1,CLK_CAPTURE_MODE,Capture clock mode,0,rw
SGPIO_SLICE_MUX_CFG15,2,1,CLKGEN_MODE,Clock generation mode,0,rw
SGPIO_SLICE_MUX_CFG15,3,1,INV_OUT_CLK,Invert output clock,0,rw
SGPIO_SLICE_MUX_CFG15,4,2,DATA_CAPTURE_MODE,Condition for input bit match interrupt,0,rw
SGPIO_SLICE_MUX_CFG15,6,2,PARALLEL_MODE,Parallel mode,0,rw
SGPIO_SLICE_MUX_CFG15,8,1,INV_QUALIFIER,Inversion qualifier,0,rw
SGPIO_POS0,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS0,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS1,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS1,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS2,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS2,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS3,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS3,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS4,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS4,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS5,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS5,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS6,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS6,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS7,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS7,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS8,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS8,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS9,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS9,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS10,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS10,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS11,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS11,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS12,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS12,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS13,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS13,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS14,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS14,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
SGPIO_POS15,0,8,POS,Each time COUNT reaches 0x0 POS counts down,0,rw
SGPIO_POS15,8,8,POS_RESET,Reload value for POS after POS reaches 0x0,0,rw
1 SGPIO_OUT_MUX_CFG0 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
2 SGPIO_OUT_MUX_CFG0 4 3 P_OE_CFG Output enable source 0 rw
3 SGPIO_OUT_MUX_CFG1 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
4 SGPIO_OUT_MUX_CFG1 4 3 P_OE_CFG Output enable source 0 rw
5 SGPIO_OUT_MUX_CFG2 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
6 SGPIO_OUT_MUX_CFG2 4 3 P_OE_CFG Output enable source 0 rw
7 SGPIO_OUT_MUX_CFG3 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
8 SGPIO_OUT_MUX_CFG3 4 3 P_OE_CFG Output enable source 0 rw
9 SGPIO_OUT_MUX_CFG4 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
10 SGPIO_OUT_MUX_CFG4 4 3 P_OE_CFG Output enable source 0 rw
11 SGPIO_OUT_MUX_CFG5 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
12 SGPIO_OUT_MUX_CFG5 4 3 P_OE_CFG Output enable source 0 rw
13 SGPIO_OUT_MUX_CFG6 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
14 SGPIO_OUT_MUX_CFG6 4 3 P_OE_CFG Output enable source 0 rw
15 SGPIO_OUT_MUX_CFG7 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
16 SGPIO_OUT_MUX_CFG7 4 3 P_OE_CFG Output enable source 0 rw
17 SGPIO_OUT_MUX_CFG8 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
18 SGPIO_OUT_MUX_CFG8 4 3 P_OE_CFG Output enable source 0 rw
19 SGPIO_OUT_MUX_CFG9 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
20 SGPIO_OUT_MUX_CFG9 4 3 P_OE_CFG Output enable source 0 rw
21 SGPIO_OUT_MUX_CFG10 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
22 SGPIO_OUT_MUX_CFG10 4 3 P_OE_CFG Output enable source 0 rw
23 SGPIO_OUT_MUX_CFG11 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
24 SGPIO_OUT_MUX_CFG11 4 3 P_OE_CFG Output enable source 0 rw
25 SGPIO_OUT_MUX_CFG12 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
26 SGPIO_OUT_MUX_CFG12 4 3 P_OE_CFG Output enable source 0 rw
27 SGPIO_OUT_MUX_CFG13 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
28 SGPIO_OUT_MUX_CFG13 4 3 P_OE_CFG Output enable source 0 rw
29 SGPIO_OUT_MUX_CFG14 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
30 SGPIO_OUT_MUX_CFG14 4 3 P_OE_CFG Output enable source 0 rw
31 SGPIO_OUT_MUX_CFG15 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
32 SGPIO_OUT_MUX_CFG15 4 3 P_OE_CFG Output enable source 0 rw
33 SGPIO_MUX_CFG0 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
34 SGPIO_MUX_CFG0 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
35 SGPIO_MUX_CFG0 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
36 SGPIO_MUX_CFG0 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
37 SGPIO_MUX_CFG0 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
38 SGPIO_MUX_CFG0 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
39 SGPIO_MUX_CFG0 11 1 CONCAT_ENABLE Enable concatenation 0 rw
40 SGPIO_MUX_CFG0 12 2 CONCAT_ORDER Select concatenation order 0 rw
41 SGPIO_MUX_CFG1 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
42 SGPIO_MUX_CFG1 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
43 SGPIO_MUX_CFG1 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
44 SGPIO_MUX_CFG1 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
45 SGPIO_MUX_CFG1 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
46 SGPIO_MUX_CFG1 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
47 SGPIO_MUX_CFG1 11 1 CONCAT_ENABLE Enable concatenation 0 rw
48 SGPIO_MUX_CFG1 12 2 CONCAT_ORDER Select concatenation order 0 rw
49 SGPIO_MUX_CFG2 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
50 SGPIO_MUX_CFG2 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
51 SGPIO_MUX_CFG2 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
52 SGPIO_MUX_CFG2 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
53 SGPIO_MUX_CFG2 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
54 SGPIO_MUX_CFG2 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
55 SGPIO_MUX_CFG2 11 1 CONCAT_ENABLE Enable concatenation 0 rw
56 SGPIO_MUX_CFG2 12 2 CONCAT_ORDER Select concatenation order 0 rw
57 SGPIO_MUX_CFG3 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
58 SGPIO_MUX_CFG3 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
59 SGPIO_MUX_CFG3 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
60 SGPIO_MUX_CFG3 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
61 SGPIO_MUX_CFG3 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
62 SGPIO_MUX_CFG3 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
63 SGPIO_MUX_CFG3 11 1 CONCAT_ENABLE Enable concatenation 0 rw
64 SGPIO_MUX_CFG3 12 2 CONCAT_ORDER Select concatenation order 0 rw
65 SGPIO_MUX_CFG4 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
66 SGPIO_MUX_CFG4 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
67 SGPIO_MUX_CFG4 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
68 SGPIO_MUX_CFG4 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
69 SGPIO_MUX_CFG4 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
70 SGPIO_MUX_CFG4 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
71 SGPIO_MUX_CFG4 11 1 CONCAT_ENABLE Enable concatenation 0 rw
72 SGPIO_MUX_CFG4 12 2 CONCAT_ORDER Select concatenation order 0 rw
73 SGPIO_MUX_CFG5 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
74 SGPIO_MUX_CFG5 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
75 SGPIO_MUX_CFG5 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
76 SGPIO_MUX_CFG5 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
77 SGPIO_MUX_CFG5 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
78 SGPIO_MUX_CFG5 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
79 SGPIO_MUX_CFG5 11 1 CONCAT_ENABLE Enable concatenation 0 rw
80 SGPIO_MUX_CFG5 12 2 CONCAT_ORDER Select concatenation order 0 rw
81 SGPIO_MUX_CFG6 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
82 SGPIO_MUX_CFG6 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
83 SGPIO_MUX_CFG6 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
84 SGPIO_MUX_CFG6 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
85 SGPIO_MUX_CFG6 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
86 SGPIO_MUX_CFG6 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
87 SGPIO_MUX_CFG6 11 1 CONCAT_ENABLE Enable concatenation 0 rw
88 SGPIO_MUX_CFG6 12 2 CONCAT_ORDER Select concatenation order 0 rw
89 SGPIO_MUX_CFG7 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
90 SGPIO_MUX_CFG7 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
91 SGPIO_MUX_CFG7 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
92 SGPIO_MUX_CFG7 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
93 SGPIO_MUX_CFG7 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
94 SGPIO_MUX_CFG7 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
95 SGPIO_MUX_CFG7 11 1 CONCAT_ENABLE Enable concatenation 0 rw
96 SGPIO_MUX_CFG7 12 2 CONCAT_ORDER Select concatenation order 0 rw
97 SGPIO_MUX_CFG8 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
98 SGPIO_MUX_CFG8 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
99 SGPIO_MUX_CFG8 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
100 SGPIO_MUX_CFG8 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
101 SGPIO_MUX_CFG8 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
102 SGPIO_MUX_CFG8 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
103 SGPIO_MUX_CFG8 11 1 CONCAT_ENABLE Enable concatenation 0 rw
104 SGPIO_MUX_CFG8 12 2 CONCAT_ORDER Select concatenation order 0 rw
105 SGPIO_MUX_CFG9 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
106 SGPIO_MUX_CFG9 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
107 SGPIO_MUX_CFG9 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
108 SGPIO_MUX_CFG9 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
109 SGPIO_MUX_CFG9 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
110 SGPIO_MUX_CFG9 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
111 SGPIO_MUX_CFG9 11 1 CONCAT_ENABLE Enable concatenation 0 rw
112 SGPIO_MUX_CFG9 12 2 CONCAT_ORDER Select concatenation order 0 rw
113 SGPIO_MUX_CFG10 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
114 SGPIO_MUX_CFG10 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
115 SGPIO_MUX_CFG10 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
116 SGPIO_MUX_CFG10 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
117 SGPIO_MUX_CFG10 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
118 SGPIO_MUX_CFG10 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
119 SGPIO_MUX_CFG10 11 1 CONCAT_ENABLE Enable concatenation 0 rw
120 SGPIO_MUX_CFG10 12 2 CONCAT_ORDER Select concatenation order 0 rw
121 SGPIO_MUX_CFG11 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
122 SGPIO_MUX_CFG11 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
123 SGPIO_MUX_CFG11 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
124 SGPIO_MUX_CFG11 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
125 SGPIO_MUX_CFG11 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
126 SGPIO_MUX_CFG11 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
127 SGPIO_MUX_CFG11 11 1 CONCAT_ENABLE Enable concatenation 0 rw
128 SGPIO_MUX_CFG11 12 2 CONCAT_ORDER Select concatenation order 0 rw
129 SGPIO_MUX_CFG12 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
130 SGPIO_MUX_CFG12 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
131 SGPIO_MUX_CFG12 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
132 SGPIO_MUX_CFG12 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
133 SGPIO_MUX_CFG12 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
134 SGPIO_MUX_CFG12 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
135 SGPIO_MUX_CFG12 11 1 CONCAT_ENABLE Enable concatenation 0 rw
136 SGPIO_MUX_CFG12 12 2 CONCAT_ORDER Select concatenation order 0 rw
137 SGPIO_MUX_CFG13 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
138 SGPIO_MUX_CFG13 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
139 SGPIO_MUX_CFG13 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
140 SGPIO_MUX_CFG13 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
141 SGPIO_MUX_CFG13 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
142 SGPIO_MUX_CFG13 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
143 SGPIO_MUX_CFG13 11 1 CONCAT_ENABLE Enable concatenation 0 rw
144 SGPIO_MUX_CFG13 12 2 CONCAT_ORDER Select concatenation order 0 rw
145 SGPIO_MUX_CFG14 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
146 SGPIO_MUX_CFG14 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
147 SGPIO_MUX_CFG14 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
148 SGPIO_MUX_CFG14 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
149 SGPIO_MUX_CFG14 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
150 SGPIO_MUX_CFG14 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
151 SGPIO_MUX_CFG14 11 1 CONCAT_ENABLE Enable concatenation 0 rw
152 SGPIO_MUX_CFG14 12 2 CONCAT_ORDER Select concatenation order 0 rw
153 SGPIO_MUX_CFG15 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
154 SGPIO_MUX_CFG15 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
155 SGPIO_MUX_CFG15 4 3 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
156 SGPIO_MUX_CFG15 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
157 SGPIO_MUX_CFG15 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
158 SGPIO_MUX_CFG15 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
159 SGPIO_MUX_CFG15 11 1 CONCAT_ENABLE Enable concatenation 0 rw
160 SGPIO_MUX_CFG15 12 2 CONCAT_ORDER Select concatenation order 0 rw
161 SGPIO_SLICE_MUX_CFG0 0 1 MATCH_MODE Match mode 0 rw
162 SGPIO_SLICE_MUX_CFG0 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
163 SGPIO_SLICE_MUX_CFG0 2 1 CLKGEN_MODE Clock generation mode 0 rw
164 SGPIO_SLICE_MUX_CFG0 3 1 INV_OUT_CLK Invert output clock 0 rw
165 SGPIO_SLICE_MUX_CFG0 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
166 SGPIO_SLICE_MUX_CFG0 6 2 PARALLEL_MODE Parallel mode 0 rw
167 SGPIO_SLICE_MUX_CFG0 8 1 INV_QUALIFIER Inversion qualifier 0 rw
168 SGPIO_SLICE_MUX_CFG1 0 1 MATCH_MODE Match mode 0 rw
169 SGPIO_SLICE_MUX_CFG1 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
170 SGPIO_SLICE_MUX_CFG1 2 1 CLKGEN_MODE Clock generation mode 0 rw
171 SGPIO_SLICE_MUX_CFG1 3 1 INV_OUT_CLK Invert output clock 0 rw
172 SGPIO_SLICE_MUX_CFG1 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
173 SGPIO_SLICE_MUX_CFG1 6 2 PARALLEL_MODE Parallel mode 0 rw
174 SGPIO_SLICE_MUX_CFG1 8 1 INV_QUALIFIER Inversion qualifier 0 rw
175 SGPIO_SLICE_MUX_CFG2 0 1 MATCH_MODE Match mode 0 rw
176 SGPIO_SLICE_MUX_CFG2 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
177 SGPIO_SLICE_MUX_CFG2 2 1 CLKGEN_MODE Clock generation mode 0 rw
178 SGPIO_SLICE_MUX_CFG2 3 1 INV_OUT_CLK Invert output clock 0 rw
179 SGPIO_SLICE_MUX_CFG2 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
180 SGPIO_SLICE_MUX_CFG2 6 2 PARALLEL_MODE Parallel mode 0 rw
181 SGPIO_SLICE_MUX_CFG2 8 1 INV_QUALIFIER Inversion qualifier 0 rw
182 SGPIO_SLICE_MUX_CFG3 0 1 MATCH_MODE Match mode 0 rw
183 SGPIO_SLICE_MUX_CFG3 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
184 SGPIO_SLICE_MUX_CFG3 2 1 CLKGEN_MODE Clock generation mode 0 rw
185 SGPIO_SLICE_MUX_CFG3 3 1 INV_OUT_CLK Invert output clock 0 rw
186 SGPIO_SLICE_MUX_CFG3 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
187 SGPIO_SLICE_MUX_CFG3 6 2 PARALLEL_MODE Parallel mode 0 rw
188 SGPIO_SLICE_MUX_CFG3 8 1 INV_QUALIFIER Inversion qualifier 0 rw
189 SGPIO_SLICE_MUX_CFG4 0 1 MATCH_MODE Match mode 0 rw
190 SGPIO_SLICE_MUX_CFG4 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
191 SGPIO_SLICE_MUX_CFG4 2 1 CLKGEN_MODE Clock generation mode 0 rw
192 SGPIO_SLICE_MUX_CFG4 3 1 INV_OUT_CLK Invert output clock 0 rw
193 SGPIO_SLICE_MUX_CFG4 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
194 SGPIO_SLICE_MUX_CFG4 6 2 PARALLEL_MODE Parallel mode 0 rw
195 SGPIO_SLICE_MUX_CFG4 8 1 INV_QUALIFIER Inversion qualifier 0 rw
196 SGPIO_SLICE_MUX_CFG5 0 1 MATCH_MODE Match mode 0 rw
197 SGPIO_SLICE_MUX_CFG5 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
198 SGPIO_SLICE_MUX_CFG5 2 1 CLKGEN_MODE Clock generation mode 0 rw
199 SGPIO_SLICE_MUX_CFG5 3 1 INV_OUT_CLK Invert output clock 0 rw
200 SGPIO_SLICE_MUX_CFG5 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
201 SGPIO_SLICE_MUX_CFG5 6 2 PARALLEL_MODE Parallel mode 0 rw
202 SGPIO_SLICE_MUX_CFG5 8 1 INV_QUALIFIER Inversion qualifier 0 rw
203 SGPIO_SLICE_MUX_CFG6 0 1 MATCH_MODE Match mode 0 rw
204 SGPIO_SLICE_MUX_CFG6 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
205 SGPIO_SLICE_MUX_CFG6 2 1 CLKGEN_MODE Clock generation mode 0 rw
206 SGPIO_SLICE_MUX_CFG6 3 1 INV_OUT_CLK Invert output clock 0 rw
207 SGPIO_SLICE_MUX_CFG6 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
208 SGPIO_SLICE_MUX_CFG6 6 2 PARALLEL_MODE Parallel mode 0 rw
209 SGPIO_SLICE_MUX_CFG6 8 1 INV_QUALIFIER Inversion qualifier 0 rw
210 SGPIO_SLICE_MUX_CFG7 0 1 MATCH_MODE Match mode 0 rw
211 SGPIO_SLICE_MUX_CFG7 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
212 SGPIO_SLICE_MUX_CFG7 2 1 CLKGEN_MODE Clock generation mode 0 rw
213 SGPIO_SLICE_MUX_CFG7 3 1 INV_OUT_CLK Invert output clock 0 rw
214 SGPIO_SLICE_MUX_CFG7 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
215 SGPIO_SLICE_MUX_CFG7 6 2 PARALLEL_MODE Parallel mode 0 rw
216 SGPIO_SLICE_MUX_CFG7 8 1 INV_QUALIFIER Inversion qualifier 0 rw
217 SGPIO_SLICE_MUX_CFG8 0 1 MATCH_MODE Match mode 0 rw
218 SGPIO_SLICE_MUX_CFG8 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
219 SGPIO_SLICE_MUX_CFG8 2 1 CLKGEN_MODE Clock generation mode 0 rw
220 SGPIO_SLICE_MUX_CFG8 3 1 INV_OUT_CLK Invert output clock 0 rw
221 SGPIO_SLICE_MUX_CFG8 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
222 SGPIO_SLICE_MUX_CFG8 6 2 PARALLEL_MODE Parallel mode 0 rw
223 SGPIO_SLICE_MUX_CFG8 8 1 INV_QUALIFIER Inversion qualifier 0 rw
224 SGPIO_SLICE_MUX_CFG9 0 1 MATCH_MODE Match mode 0 rw
225 SGPIO_SLICE_MUX_CFG9 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
226 SGPIO_SLICE_MUX_CFG9 2 1 CLKGEN_MODE Clock generation mode 0 rw
227 SGPIO_SLICE_MUX_CFG9 3 1 INV_OUT_CLK Invert output clock 0 rw
228 SGPIO_SLICE_MUX_CFG9 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
229 SGPIO_SLICE_MUX_CFG9 6 2 PARALLEL_MODE Parallel mode 0 rw
230 SGPIO_SLICE_MUX_CFG9 8 1 INV_QUALIFIER Inversion qualifier 0 rw
231 SGPIO_SLICE_MUX_CFG10 0 1 MATCH_MODE Match mode 0 rw
232 SGPIO_SLICE_MUX_CFG10 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
233 SGPIO_SLICE_MUX_CFG10 2 1 CLKGEN_MODE Clock generation mode 0 rw
234 SGPIO_SLICE_MUX_CFG10 3 1 INV_OUT_CLK Invert output clock 0 rw
235 SGPIO_SLICE_MUX_CFG10 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
236 SGPIO_SLICE_MUX_CFG10 6 2 PARALLEL_MODE Parallel mode 0 rw
237 SGPIO_SLICE_MUX_CFG10 8 1 INV_QUALIFIER Inversion qualifier 0 rw
238 SGPIO_SLICE_MUX_CFG11 0 1 MATCH_MODE Match mode 0 rw
239 SGPIO_SLICE_MUX_CFG11 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
240 SGPIO_SLICE_MUX_CFG11 2 1 CLKGEN_MODE Clock generation mode 0 rw
241 SGPIO_SLICE_MUX_CFG11 3 1 INV_OUT_CLK Invert output clock 0 rw
242 SGPIO_SLICE_MUX_CFG11 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
243 SGPIO_SLICE_MUX_CFG11 6 2 PARALLEL_MODE Parallel mode 0 rw
244 SGPIO_SLICE_MUX_CFG11 8 1 INV_QUALIFIER Inversion qualifier 0 rw
245 SGPIO_SLICE_MUX_CFG12 0 1 MATCH_MODE Match mode 0 rw
246 SGPIO_SLICE_MUX_CFG12 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
247 SGPIO_SLICE_MUX_CFG12 2 1 CLKGEN_MODE Clock generation mode 0 rw
248 SGPIO_SLICE_MUX_CFG12 3 1 INV_OUT_CLK Invert output clock 0 rw
249 SGPIO_SLICE_MUX_CFG12 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
250 SGPIO_SLICE_MUX_CFG12 6 2 PARALLEL_MODE Parallel mode 0 rw
251 SGPIO_SLICE_MUX_CFG12 8 1 INV_QUALIFIER Inversion qualifier 0 rw
252 SGPIO_SLICE_MUX_CFG13 0 1 MATCH_MODE Match mode 0 rw
253 SGPIO_SLICE_MUX_CFG13 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
254 SGPIO_SLICE_MUX_CFG13 2 1 CLKGEN_MODE Clock generation mode 0 rw
255 SGPIO_SLICE_MUX_CFG13 3 1 INV_OUT_CLK Invert output clock 0 rw
256 SGPIO_SLICE_MUX_CFG13 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
257 SGPIO_SLICE_MUX_CFG13 6 2 PARALLEL_MODE Parallel mode 0 rw
258 SGPIO_SLICE_MUX_CFG13 8 1 INV_QUALIFIER Inversion qualifier 0 rw
259 SGPIO_SLICE_MUX_CFG14 0 1 MATCH_MODE Match mode 0 rw
260 SGPIO_SLICE_MUX_CFG14 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
261 SGPIO_SLICE_MUX_CFG14 2 1 CLKGEN_MODE Clock generation mode 0 rw
262 SGPIO_SLICE_MUX_CFG14 3 1 INV_OUT_CLK Invert output clock 0 rw
263 SGPIO_SLICE_MUX_CFG14 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
264 SGPIO_SLICE_MUX_CFG14 6 2 PARALLEL_MODE Parallel mode 0 rw
265 SGPIO_SLICE_MUX_CFG14 8 1 INV_QUALIFIER Inversion qualifier 0 rw
266 SGPIO_SLICE_MUX_CFG15 0 1 MATCH_MODE Match mode 0 rw
267 SGPIO_SLICE_MUX_CFG15 1 1 CLK_CAPTURE_MODE Capture clock mode 0 rw
268 SGPIO_SLICE_MUX_CFG15 2 1 CLKGEN_MODE Clock generation mode 0 rw
269 SGPIO_SLICE_MUX_CFG15 3 1 INV_OUT_CLK Invert output clock 0 rw
270 SGPIO_SLICE_MUX_CFG15 4 2 DATA_CAPTURE_MODE Condition for input bit match interrupt 0 rw
271 SGPIO_SLICE_MUX_CFG15 6 2 PARALLEL_MODE Parallel mode 0 rw
272 SGPIO_SLICE_MUX_CFG15 8 1 INV_QUALIFIER Inversion qualifier 0 rw
273 SGPIO_POS0 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
274 SGPIO_POS0 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
275 SGPIO_POS1 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
276 SGPIO_POS1 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
277 SGPIO_POS2 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
278 SGPIO_POS2 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
279 SGPIO_POS3 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
280 SGPIO_POS3 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
281 SGPIO_POS4 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
282 SGPIO_POS4 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
283 SGPIO_POS5 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
284 SGPIO_POS5 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
285 SGPIO_POS6 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
286 SGPIO_POS6 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
287 SGPIO_POS7 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
288 SGPIO_POS7 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
289 SGPIO_POS8 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
290 SGPIO_POS8 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
291 SGPIO_POS9 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
292 SGPIO_POS9 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
293 SGPIO_POS10 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
294 SGPIO_POS10 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
295 SGPIO_POS11 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
296 SGPIO_POS11 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
297 SGPIO_POS12 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
298 SGPIO_POS12 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
299 SGPIO_POS13 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
300 SGPIO_POS13 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
301 SGPIO_POS14 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
302 SGPIO_POS14 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw
303 SGPIO_POS15 0 8 POS Each time COUNT reaches 0x0 POS counts down 0 rw
304 SGPIO_POS15 8 8 POS_RESET Reload value for POS after POS reaches 0x0 0 rw