lib/stm32/f4: Coding-style fixes.

lib/stm32/f4/exti.c

@@ -132,15 +132,15 @@ void exti_select_source(u32 exti, u32 gpioport)
 	/* Ensure that only valid EXTI lines are used. */
 	if (exti < EXTI4) {
 		SYSCFG_EXTICR1 &= ~(0x000F << shift);
-		SYSCFG_EXTICR1 |= (~bits   << shift);
+		SYSCFG_EXTICR1 |= (~bits << shift);
 	} else if (exti < EXTI8) {
 		SYSCFG_EXTICR2 &= ~(0x000F << shift);
-		SYSCFG_EXTICR2 |= (~bits   << shift);
+		SYSCFG_EXTICR2 |= (~bits << shift);
 	} else if (exti < EXTI12) {
 		SYSCFG_EXTICR3 &= ~(0x000F << shift);
-		SYSCFG_EXTICR3 |= (~bits   << shift);
+		SYSCFG_EXTICR3 |= (~bits << shift);
 	} else if (exti < EXTI16) {
 		SYSCFG_EXTICR4 &= ~(0x000F << shift);
-		SYSCFG_EXTICR4 |= (~bits   << shift);
+		SYSCFG_EXTICR4 |= (~bits << shift);
 	}
 }

lib/stm32/f4/gpio.c

@@ -30,7 +30,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
 	 */
 	moder = GPIO_MODER(gpioport);
 	pupd = GPIO_PUPDR(gpioport);
-	
+
 	for (i = 0; i < 16; i++) {
 		if (!((1 << i) & gpios))
 			continue;
@@ -57,7 +57,7 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
 		GPIO_OTYPER(gpioport) &= ~gpios;
 
 	ospeedr = GPIO_OSPEEDR(gpioport);
-	
+
 	for (i = 0; i < 16; i++) {
 		if (!((1 << i) & gpios))
 			continue;
@@ -86,8 +86,8 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
 	for (i = 8; i < 16; i++) {
 		if (!((1 << i) & gpios))
 			continue;
-		afrl &= GPIO_AFR_MASK(i-8);
+		afrl &= GPIO_AFR_MASK(i - 8);
-		afrh |= GPIO_AFR(i-8, alt_func_num);
+		afrh |= GPIO_AFR(i - 8, alt_func_num);
 	}
 
 	GPIO_AFRL(gpioport) = afrl;
@@ -134,6 +134,6 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
 	GPIO_LCKR(gpioport) = GPIO_LCKK | gpios;	/* Set LCKK. */
 	reg32 = GPIO_LCKR(gpioport);			/* Read LCKK. */
 	reg32 = GPIO_LCKR(gpioport);			/* Read LCKK again. */
-	
+
 	/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
 }

lib/stm32/f4/rcc.c

@@ -23,7 +23,7 @@
 #include <libopencm3/stm32/f4/pwr.h>
 #include <libopencm3/stm32/f4/flash.h>
 
-/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
+/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
 u32 rcc_ppre1_frequency = 16000000;
 u32 rcc_ppre2_frequency = 16000000;
 

lib/stm32/f4/timer.c

@@ -126,9 +126,7 @@ void timer_set_mode(u32 timer_peripheral, u8 clock_div,
 
 	cr1 = TIM_CR1(timer_peripheral);
 
-	cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK |
+	cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
-		 TIM_CR1_CMS_MASK |
-		 TIM_CR1_DIR_DOWN);
 
 	cr1 |= clock_div | alignment | direction;
 
@@ -398,7 +396,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
 			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
 			break;
 		case TIM_OCM_FORCE_HIGH:
-			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH;
+			TIM_CCMR1(timer_peripheral) |=
+			    TIM_CCMR1_OC1M_FORCE_HIGH;
 			break;
 		case TIM_OCM_PWM1:
 			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
@@ -429,7 +428,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
 			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
 			break;
 		case TIM_OCM_FORCE_HIGH:
-			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH;
+			TIM_CCMR1(timer_peripheral) |=
+			    TIM_CCMR1_OC2M_FORCE_HIGH;
 			break;
 		case TIM_OCM_PWM1:
 			TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
@@ -460,7 +460,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
 			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
 			break;
 		case TIM_OCM_FORCE_HIGH:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH;
+			TIM_CCMR2(timer_peripheral) |=
+			    TIM_CCMR2_OC3M_FORCE_HIGH;
 			break;
 		case TIM_OCM_PWM1:
 			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
@@ -491,7 +492,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
 			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
 			break;
 		case TIM_OCM_FORCE_HIGH:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH;
+			TIM_CCMR2(timer_peripheral) |=
+			    TIM_CCMR2_OC4M_FORCE_HIGH;
 			break;
 		case TIM_OCM_PWM1:
 			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;
@@ -916,13 +918,10 @@ u32 timer_get_counter(u32 timer_peripheral)
 
 void timer_set_option(u32 timer_peripheral, u32 option)
 {
-	if (timer_peripheral == TIM2)
+	if (timer_peripheral == TIM2) {
-	{
 		TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK;
 		TIM_OR(timer_peripheral) |= option;
-	}
+	} else if (timer_peripheral == TIM5) {
-	else if (timer_peripheral == TIM5)
-	{
 		TIM_OR(timer_peripheral) &= ~TIM5_OR_TI4_RMP_MASK;
 		TIM_OR(timer_peripheral) |= option;
 	}

lib/stm32/f4/vector.c

@@ -20,7 +20,7 @@
 
 #define WEAK __attribute__ ((weak))
 
-/* Symbols exported by linker script */
+/* Symbols exported by the linker script(s): */
 extern unsigned _etext, _data, _edata, _ebss, _stack;
 
 void main(void);
@@ -122,7 +122,7 @@ void WEAK hash_rng_isr(void);
 
 __attribute__ ((section(".vectors")))
 void (*const vector_table[]) (void) = {
-	(void*)&_stack,
+	(void *)&_stack,
 	reset_handler,
 	nmi_handler,
 	hard_fault_handler,
@@ -206,10 +206,10 @@ void (*const vector_table[]) (void) = {
 	dma2_stream5_isr,
 	dma2_stream6_isr,
 	dma2_stream7_isr,
-  usart6_isr,
+	usart6_isr,
 	i2c3_ev_isr,
 	i2c3_er_isr,
-  otg_hs_ep1_out_isr,
+	otg_hs_ep1_out_isr,
 	otg_hs_ep1_in_isr,
 	otg_hs_wkup_isr,
 	otg_hs_isr,
@@ -221,7 +221,8 @@ void (*const vector_table[]) (void) = {
 void reset_handler(void)
 {
 	volatile unsigned *src, *dest;
-	asm("MSR msp, %0" : : "r"(&_stack));
+
+	__asm__("MSR msp, %0" : : "r"(&_stack));
 
 	for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
 		*dest = *src;
@@ -333,4 +334,3 @@ void null_handler(void)
 #pragma weak dcmi_isr = null_handler
 #pragma weak cryp_isr = null_handler
 #pragma weak hash_rng_isr = null_handler
-