lpc43: Use uint*_t instead of u*
This commit is contained in:
Ben Gamari
Piotr Esden-Tempski
parent
26162762b7
commit
0d29b1d2d6
@ -25,6 +25,6 @@
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void ipc_halt_m0(void);
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void ipc_start_m0(u32 cm0_baseaddr);
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void ipc_start_m0(uint32_t cm0_baseaddr);
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#endif
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@ -1954,51 +1954,51 @@ LGPL License Terms @ref lgpl_license
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/* SGPIO structure for faster/better code generation (especially when optimized with -O2/-O3) */
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/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 September 2012 */
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typedef struct {
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volatile u32 OUT_MUX_CFG[16]; /* Pin multiplexer configuration registers. RW */
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volatile u32 SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. RW */
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volatile u32 SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. RW */
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volatile u32 REG[16]; /* Slice data registers. RW */
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volatile u32 REG_SS[16]; /* Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG. RW */
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volatile u32 PRESET[16]; /* Reload registers. Counter reload value; loaded when COUNT reaches 0x0 RW */
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volatile u32 COUNT[16]; /* Down counter registers, counts down each shift clock cycle. RW */
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volatile u32 POS[16]; /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. POS_RESET Reload value for POS after POS reaches 0x0. RW */
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volatile u32 MASK_A; /* Slice A mask register. Mask for pattern match function of slice A. RW */
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volatile u32 MASK_H; /* Slice H mask register. Mask for pattern match function of slice H. RW */
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volatile u32 MASK_I; /* Slice I mask register. Mask for pattern match function of slice I. RW */
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volatile u32 MASK_P; /* Slice P mask register. Mask for pattern match function of slice P. RW */
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volatile u32 GPIO_INREG; /* GPIO input status register. R */
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volatile u32 GPIO_OUTREG; /* GPIO output control register. RW */
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volatile u32 GPIO_OENREG; /* GPIO output enable register. RW */
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volatile u32 CTRL_ENABLE; /* Slice count enable register. RW */
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volatile u32 CTRL_DISABLE; /* Slice count disable register. RW */
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volatile u32 RES0[823];
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volatile u32 CLR_EN_0; /* Shift clock interrupt clear mask register. W */
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volatile u32 SET_EN_0; /* Shift clock interrupt set mask register. W */
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volatile u32 ENABLE_0; /* Shift clock interrupt enable register. R */
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volatile u32 STATUS_0; /* Shift clock interrupt status register. R */
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volatile u32 CLR_STATUS_0; /* Shift clock interrupt clear status register. W */
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volatile u32 SET_STATUS_0; /* Shift clock interrupt set status register. W */
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volatile u32 RES1[2];
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volatile u32 CLR_EN_1; /* Exchange clock interrupt clear mask register. W */
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volatile u32 SET_EN_1; /* Exchange clock interrupt set mask register. W */
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volatile u32 ENABLE_1; /* Exchange clock interrupt enable. R */
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volatile u32 STATUS_1; /* Exchange clock interrupt status register. R */
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volatile u32 CLR_STATUS_1; /* Exchange clock interrupt clear status register. W */
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volatile u32 SET_STATUS_1; /* Exchange clock interrupt set status register. W */
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volatile u32 RES2[2];
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volatile u32 CLR_EN_2; /* Pattern match interrupt clear mask register. W */
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volatile u32 SET_EN_2; /* Pattern match interrupt set mask register. W */
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volatile u32 ENABLE_2; /* Pattern match interrupt enable register. R */
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volatile u32 STATUS_2; /* Pattern match interrupt status register. R */
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volatile u32 CLR_STATUS_2; /* Pattern match interrupt clear status register. W */
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volatile u32 SET_STATUS_2; /* Pattern match interrupt set status register. W */
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volatile u32 RES3[2];
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volatile u32 CLR_EN_3; /* Input interrupt clear mask register. W */
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volatile u32 SET_EN_3; /* Input bit match interrupt set mask register. W */
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volatile u32 ENABLE_3; /* Input bit match interrupt enable register. R */
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volatile u32 STATUS_3; /* Input bit match interrupt status register. R */
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volatile u32 CLR_STATUS_3; /* Input bit match interrupt clear status register. W */
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volatile u32 SET_STATUS_3; /* Input bit match interrupt set status register. W */
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volatile uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configuration registers. RW */
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volatile uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. RW */
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volatile uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. RW */
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volatile uint32_t REG[16]; /* Slice data registers. RW */
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volatile uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG. RW */
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volatile uint32_t PRESET[16]; /* Reload registers. Counter reload value; loaded when COUNT reaches 0x0 RW */
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volatile uint32_t COUNT[16]; /* Down counter registers, counts down each shift clock cycle. RW */
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volatile uint32_t POS[16]; /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. POS_RESET Reload value for POS after POS reaches 0x0. RW */
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volatile uint32_t MASK_A; /* Slice A mask register. Mask for pattern match function of slice A. RW */
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volatile uint32_t MASK_H; /* Slice H mask register. Mask for pattern match function of slice H. RW */
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volatile uint32_t MASK_I; /* Slice I mask register. Mask for pattern match function of slice I. RW */
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volatile uint32_t MASK_P; /* Slice P mask register. Mask for pattern match function of slice P. RW */
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volatile uint32_t GPIO_INREG; /* GPIO input status register. R */
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volatile uint32_t GPIO_OUTREG; /* GPIO output control register. RW */
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volatile uint32_t GPIO_OENREG; /* GPIO output enable register. RW */
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volatile uint32_t CTRL_ENABLE; /* Slice count enable register. RW */
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volatile uint32_t CTRL_DISABLE; /* Slice count disable register. RW */
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volatile uint32_t RES0[823];
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volatile uint32_t CLR_EN_0; /* Shift clock interrupt clear mask register. W */
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volatile uint32_t SET_EN_0; /* Shift clock interrupt set mask register. W */
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volatile uint32_t ENABLE_0; /* Shift clock interrupt enable register. R */
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volatile uint32_t STATUS_0; /* Shift clock interrupt status register. R */
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volatile uint32_t CLR_STATUS_0; /* Shift clock interrupt clear status register. W */
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volatile uint32_t SET_STATUS_0; /* Shift clock interrupt set status register. W */
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volatile uint32_t RES1[2];
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volatile uint32_t CLR_EN_1; /* Exchange clock interrupt clear mask register. W */
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volatile uint32_t SET_EN_1; /* Exchange clock interrupt set mask register. W */
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volatile uint32_t ENABLE_1; /* Exchange clock interrupt enable. R */
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volatile uint32_t STATUS_1; /* Exchange clock interrupt status register. R */
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volatile uint32_t CLR_STATUS_1; /* Exchange clock interrupt clear status register. W */
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volatile uint32_t SET_STATUS_1; /* Exchange clock interrupt set status register. W */
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volatile uint32_t RES2[2];
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volatile uint32_t CLR_EN_2; /* Pattern match interrupt clear mask register. W */
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volatile uint32_t SET_EN_2; /* Pattern match interrupt set mask register. W */
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volatile uint32_t ENABLE_2; /* Pattern match interrupt enable register. R */
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volatile uint32_t STATUS_2; /* Pattern match interrupt status register. R */
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volatile uint32_t CLR_STATUS_2; /* Pattern match interrupt clear status register. W */
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volatile uint32_t SET_STATUS_2; /* Pattern match interrupt set status register. W */
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volatile uint32_t RES3[2];
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volatile uint32_t CLR_EN_3; /* Input interrupt clear mask register. W */
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volatile uint32_t SET_EN_3; /* Input bit match interrupt set mask register. W */
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volatile uint32_t ENABLE_3; /* Input bit match interrupt enable register. R */
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volatile uint32_t STATUS_3; /* Input bit match interrupt status register. R */
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volatile uint32_t CLR_STATUS_3; /* Input bit match interrupt clear status register. W */
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volatile uint32_t SET_STATUS_3; /* Input bit match interrupt set status register. W */
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} sgpio_t;
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/* Global access to SGPIO structure */
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@ -102,171 +102,171 @@
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Receiver Buffer Register
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**********************************************************************/
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#define UART_RBR_MASKBIT ((u8)0xFF) /* UART Received Buffer mask bit (8 bits) */
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#define UART_RBR_MASKBIT ((uint8_t)0xFF) /* UART Received Buffer mask bit (8 bits) */
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Transmit Holding Register
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**********************************************************************/
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#define UART_THR_MASKBIT ((u8)0xFF) /* UART Transmit Holding mask bit (8 bits) */
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#define UART_THR_MASKBIT ((uint8_t)0xFF) /* UART Transmit Holding mask bit (8 bits) */
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Divisor Latch LSB register
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**********************************************************************/
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#define UART_LOAD_DLL(div) ((div) & 0xFF) /* Macro for loading least significant halfs of divisors */
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#define UART_DLL_MASKBIT ((u8)0xFF) /* Divisor latch LSB bit mask */
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#define UART_DLL_MASKBIT ((uint8_t)0xFF) /* Divisor latch LSB bit mask */
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/***********************************************************************
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* Macro defines for Macro defines for UARTn Divisor Latch MSB register
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**********************************************************************/
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#define UART_DLM_MASKBIT ((u8)0xFF) /* Divisor latch MSB bit mask */
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#define UART_DLM_MASKBIT ((uint8_t)0xFF) /* Divisor latch MSB bit mask */
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#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /* Macro for loading most significant halfs of divisors */
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/***********************************************************************
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* Macro defines for Macro defines for UART interrupt enable register
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**********************************************************************/
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#define UART_IER_RBRINT_EN ((u32)(BIT0)) /* RBR Interrupt enable*/
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#define UART_IER_THREINT_EN ((u32)(BIT1)) /* THR Interrupt enable*/
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#define UART_IER_RLSINT_EN ((u32)(BIT2)) /* RX line status interrupt enable*/
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#define UART1_IER_MSINT_EN ((u32)(BIT3)) /* Modem status interrupt enable */
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#define UART1_IER_CTSINT_EN ((u32)(BIT7)) /* CTS1 signal transition interrupt enable */
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#define UART_IER_ABEOINT_EN ((u32)(BIT8)) /* Enables the end of auto-baud interrupt */
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#define UART_IER_ABTOINT_EN ((u32)(BIT9)) /* Enables the auto-baud time-out interrupt */
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#define UART_IER_BITMASK ((u32)(0x307)) /* UART interrupt enable register bit mask */
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#define UART1_IER_BITMASK ((u32)(0x38F)) /* UART1 interrupt enable register bit mask */
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#define UART_IER_RBRINT_EN ((uint32_t)(BIT0)) /* RBR Interrupt enable*/
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#define UART_IER_THREINT_EN ((uint32_t)(BIT1)) /* THR Interrupt enable*/
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#define UART_IER_RLSINT_EN ((uint32_t)(BIT2)) /* RX line status interrupt enable*/
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#define UART1_IER_MSINT_EN ((uint32_t)(BIT3)) /* Modem status interrupt enable */
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#define UART1_IER_CTSINT_EN ((uint32_t)(BIT7)) /* CTS1 signal transition interrupt enable */
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#define UART_IER_ABEOINT_EN ((uint32_t)(BIT8)) /* Enables the end of auto-baud interrupt */
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#define UART_IER_ABTOINT_EN ((uint32_t)(BIT9)) /* Enables the auto-baud time-out interrupt */
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#define UART_IER_BITMASK ((uint32_t)(0x307)) /* UART interrupt enable register bit mask */
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#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /* UART1 interrupt enable register bit mask */
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/**********************************************************************
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* Macro defines for Macro defines for UART interrupt identification register
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**********************************************************************/
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#define UART_IIR_INTSTAT_PEND ((u32)(BIT0)) /* Interrupt Status - Active low */
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#define UART_IIR_INTID_RDA ((u32)(2<<1)) /* Interrupt identification: Receive data available*/
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#define UART_IIR_INTID_RLS ((u32)(3<<1)) /* Interrupt identification: Receive line status*/
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#define UART_IIR_INTID_CTI ((u32)(6<<1)) /* Interrupt identification: Character time-out indicator*/
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#define UART_IIR_INTID_THRE ((u32)(BIT1)) /* Interrupt identification: THRE interrupt*/
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#define UART1_IIR_INTID_MODEM ((u32)(0<<1)) /* Interrupt identification: Modem interrupt*/
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#define UART_IIR_INTID_MASK ((u32)(7<<1)) /* Interrupt identification: Interrupt ID mask */
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#define UART_IIR_FIFO_EN ((u32)(3<<6)) /* These bits are equivalent to UnFCR[0] */
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#define UART_IIR_ABEO_INT ((u32)(BIT8)) /* End of auto-baud interrupt */
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#define UART_IIR_ABTO_INT ((u32)(BIT9)) /* Auto-baud time-out interrupt */
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#define UART_IIR_BITMASK ((u32)(0x3CF)) /* UART interrupt identification register bit mask */
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#define UART_IIR_INTSTAT_PEND ((uint32_t)(BIT0)) /* Interrupt Status - Active low */
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#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /* Interrupt identification: Receive data available*/
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#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /* Interrupt identification: Receive line status*/
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#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /* Interrupt identification: Character time-out indicator*/
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#define UART_IIR_INTID_THRE ((uint32_t)(BIT1)) /* Interrupt identification: THRE interrupt*/
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#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /* Interrupt identification: Modem interrupt*/
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#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /* Interrupt identification: Interrupt ID mask */
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#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /* These bits are equivalent to UnFCR[0] */
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#define UART_IIR_ABEO_INT ((uint32_t)(BIT8)) /* End of auto-baud interrupt */
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#define UART_IIR_ABTO_INT ((uint32_t)(BIT9)) /* Auto-baud time-out interrupt */
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#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /* UART interrupt identification register bit mask */
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/**********************************************************************
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* Macro defines for Macro defines for UART FIFO control register
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**********************************************************************/
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#define UART_FCR_FIFO_EN ((u8)(BIT0)) /* UART FIFO enable */
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#define UART_FCR_RX_RS ((u8)(BIT1)) /* UART FIFO RX reset */
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#define UART_FCR_TX_RS ((u8)(BIT2)) /* UART FIFO TX reset */
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#define UART_FCR_DMAMODE_SEL ((u8)(BIT3)) /* UART DMA mode selection */
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#define UART_FCR_TRG_LEV0 ((u8)(0)) /* UART FIFO trigger level 0: 1 character */
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#define UART_FCR_TRG_LEV1 ((u8)(BIT6)) /* UART FIFO trigger level 1: 4 character */
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#define UART_FCR_TRG_LEV2 ((u8)(2<<6)) /* UART FIFO trigger level 2: 8 character */
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#define UART_FCR_TRG_LEV3 ((u8)(3<<6)) /* UART FIFO trigger level 3: 14 character */
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#define UART_FCR_BITMASK ((u8)(0xCF)) /* UART FIFO control bit mask */
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#define UART_FCR_FIFO_EN ((uint8_t)(BIT0)) /* UART FIFO enable */
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#define UART_FCR_RX_RS ((uint8_t)(BIT1)) /* UART FIFO RX reset */
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#define UART_FCR_TX_RS ((uint8_t)(BIT2)) /* UART FIFO TX reset */
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#define UART_FCR_DMAMODE_SEL ((uint8_t)(BIT3)) /* UART DMA mode selection */
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#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /* UART FIFO trigger level 0: 1 character */
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#define UART_FCR_TRG_LEV1 ((uint8_t)(BIT6)) /* UART FIFO trigger level 1: 4 character */
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#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /* UART FIFO trigger level 2: 8 character */
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#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /* UART FIFO trigger level 3: 14 character */
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#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /* UART FIFO control bit mask */
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#define UART_TX_FIFO_SIZE (16)
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/**********************************************************************
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* Macro defines for Macro defines for UART line control register
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**********************************************************************/
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#define UART_LCR_WLEN5 ((u8)(0)) /* UART 5 bit data mode */
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#define UART_LCR_WLEN6 ((u8)(1)) /* UART 6 bit data mode */
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#define UART_LCR_WLEN7 ((u8)(2)) /* UART 7 bit data mode */
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#define UART_LCR_WLEN8 ((u8)(3)) /* UART 8 bit data mode */
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#define UART_LCR_ONE_STOPBIT ((u8)(0)) /* UART One Stop Bits */
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#define UART_LCR_TWO_STOPBIT ((u8)(BIT2)) /* UART Two Stop Bits */
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#define UART_LCR_NO_PARITY ((u8)(0)) /* UART Parity Disabled / No Parity */
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#define UART_LCR_PARITY_EN ((u8)(BIT3)) /* UART Parity Enable */
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#define UART_LCR_PARITY_ODD ((u8)(0)) /* UART Odd Parity Select */
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#define UART_LCR_PARITY_EVEN ((u8)(BIT4)) /* UART Even Parity Select */
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#define UART_LCR_PARITY_SP_1 ((u8)(0x20)) /* UART force 1 stick parity */
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#define UART_LCR_PARITY_SP_0 ((u8)(0x30)) /* UART force 0 stick parity */
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#define UART_LCR_BREAK_EN ((u8)(BIT6)) /* UART Transmission Break enable */
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#define UART_LCR_DLAB_EN ((u8)(BIT7)) /* UART Divisor Latches Access bit enable */
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#define UART_LCR_BITMASK ((u8)(0xFF)) /* UART line control bit mask */
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#define UART_LCR_WLEN5 ((uint8_t)(0)) /* UART 5 bit data mode */
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#define UART_LCR_WLEN6 ((uint8_t)(1)) /* UART 6 bit data mode */
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#define UART_LCR_WLEN7 ((uint8_t)(2)) /* UART 7 bit data mode */
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#define UART_LCR_WLEN8 ((uint8_t)(3)) /* UART 8 bit data mode */
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#define UART_LCR_ONE_STOPBIT ((uint8_t)(0)) /* UART One Stop Bits */
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#define UART_LCR_TWO_STOPBIT ((uint8_t)(BIT2)) /* UART Two Stop Bits */
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#define UART_LCR_NO_PARITY ((uint8_t)(0)) /* UART Parity Disabled / No Parity */
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#define UART_LCR_PARITY_EN ((uint8_t)(BIT3)) /* UART Parity Enable */
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#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /* UART Odd Parity Select */
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#define UART_LCR_PARITY_EVEN ((uint8_t)(BIT4)) /* UART Even Parity Select */
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#define UART_LCR_PARITY_SP_1 ((uint8_t)(0x20)) /* UART force 1 stick parity */
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#define UART_LCR_PARITY_SP_0 ((uint8_t)(0x30)) /* UART force 0 stick parity */
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#define UART_LCR_BREAK_EN ((uint8_t)(BIT6)) /* UART Transmission Break enable */
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#define UART_LCR_DLAB_EN ((uint8_t)(BIT7)) /* UART Divisor Latches Access bit enable */
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#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /* UART line control bit mask */
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/**********************************************************************
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* Macro defines for Macro defines for UART line status register
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**********************************************************************/
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#define UART_LSR_RDR ((u8)(BIT0)) /* Line status register: Receive data ready */
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#define UART_LSR_OE ((u8)(BIT1)) /* Line status register: Overrun error */
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#define UART_LSR_PE ((u8)(BIT2)) /* Line status register: Parity error */
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#define UART_LSR_FE ((u8)(BIT3)) /* Line status register: Framing error */
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#define UART_LSR_BI ((u8)(BIT4)) /* Line status register: Break interrupt */
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#define UART_LSR_THRE ((u8)(BIT5)) /* Line status register: Transmit holding register empty */
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#define UART_LSR_TEMT ((u8)(BIT6)) /* Line status register: Transmitter empty */
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#define UART_LSR_RXFE ((u8)(BIT7)) /* Error in RX FIFO */
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#define UART_LSR_BITMASK ((u8)(0xFF)) /* UART Line status bit mask */
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#define UART_LSR_RDR ((uint8_t)(BIT0)) /* Line status register: Receive data ready */
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#define UART_LSR_OE ((uint8_t)(BIT1)) /* Line status register: Overrun error */
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#define UART_LSR_PE ((uint8_t)(BIT2)) /* Line status register: Parity error */
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#define UART_LSR_FE ((uint8_t)(BIT3)) /* Line status register: Framing error */
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#define UART_LSR_BI ((uint8_t)(BIT4)) /* Line status register: Break interrupt */
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#define UART_LSR_THRE ((uint8_t)(BIT5)) /* Line status register: Transmit holding register empty */
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#define UART_LSR_TEMT ((uint8_t)(BIT6)) /* Line status register: Transmitter empty */
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#define UART_LSR_RXFE ((uint8_t)(BIT7)) /* Error in RX FIFO */
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#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /* UART Line status bit mask */
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#define UART_LSR_ERROR_MASK (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_BI|UART_LSR_RXFE)
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/**********************************************************************
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* Macro defines for Macro defines for UART Scratch Pad Register
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**********************************************************************/
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#define UART_SCR_BIMASK ((u8)(0xFF)) /* UART Scratch Pad bit mask */
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#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /* UART Scratch Pad bit mask */
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/***********************************************************************
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* Macro defines for Macro defines for UART Auto baudrate control register
|
||||
**********************************************************************/
|
||||
#define UART_ACR_START ((u32)(BIT0)) /* UART Auto-baud start */
|
||||
#define UART_ACR_MODE ((u32)(BIT1)) /* UART Auto baudrate Mode 1 */
|
||||
#define UART_ACR_AUTO_RESTART ((u32)(BIT2)) /* UART Auto baudrate restart */
|
||||
#define UART_ACR_ABEOINT_CLR ((u32)(BIT8)) /* UART End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINT_CLR ((u32)(BIT9)) /* UART Auto-baud time-out interrupt clear */
|
||||
#define UART_ACR_BITMASK ((u32)(0x307)) /* UART Auto Baudrate register bit mask */
|
||||
#define UART_ACR_START ((uint32_t)(BIT0)) /* UART Auto-baud start */
|
||||
#define UART_ACR_MODE ((uint32_t)(BIT1)) /* UART Auto baudrate Mode 1 */
|
||||
#define UART_ACR_AUTO_RESTART ((uint32_t)(BIT2)) /* UART Auto baudrate restart */
|
||||
#define UART_ACR_ABEOINT_CLR ((uint32_t)(BIT8)) /* UART End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINT_CLR ((uint32_t)(BIT9)) /* UART Auto-baud time-out interrupt clear */
|
||||
#define UART_ACR_BITMASK ((uint32_t)(0x307)) /* UART Auto Baudrate register bit mask */
|
||||
|
||||
/*********************************************************************
|
||||
* Macro defines for Macro defines for UART IrDA control register
|
||||
**********************************************************************/
|
||||
#define UART_ICR_IRDAEN ((u32)(BIT0)) /* IrDA mode enable */
|
||||
#define UART_ICR_IRDAINV ((u32)(BIT1)) /* IrDA serial input inverted */
|
||||
#define UART_ICR_FIXPULSE_EN ((u32)(BIT2)) /* IrDA fixed pulse width mode */
|
||||
#define UART_ICR_PULSEDIV(n) ((u32)((n&0x07)<<3)) /* PulseDiv - Configures the pulse when FixPulseEn = 1 */
|
||||
#define UART_ICR_BITMASK ((u32)(0x3F)) /* UART IRDA bit mask */
|
||||
#define UART_ICR_IRDAEN ((uint32_t)(BIT0)) /* IrDA mode enable */
|
||||
#define UART_ICR_IRDAINV ((uint32_t)(BIT1)) /* IrDA serial input inverted */
|
||||
#define UART_ICR_FIXPULSE_EN ((uint32_t)(BIT2)) /* IrDA fixed pulse width mode */
|
||||
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /* PulseDiv - Configures the pulse when FixPulseEn = 1 */
|
||||
#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /* UART IRDA bit mask */
|
||||
|
||||
/**********************************************************************
|
||||
* Macro defines for Macro defines for UART half duplex register
|
||||
**********************************************************************/
|
||||
#define UART_HDEN_HDEN ((u32)(BIT0)) /* enable half-duplex mode*/
|
||||
#define UART_HDEN_HDEN ((uint32_t)(BIT0)) /* enable half-duplex mode*/
|
||||
|
||||
/**********************************************************************
|
||||
* Macro defines for Macro defines for UART smart card interface control register
|
||||
**********************************************************************/
|
||||
#define UART_SCICTRL_SCIEN ((u32)(BIT0)) /* enable asynchronous half-duplex smart card interface*/
|
||||
#define UART_SCICTRL_NACKDIS ((u32)(BIT1)) /* NACK response is inhibited*/
|
||||
#define UART_SCICTRL_PROTSEL_T1 ((u32)(BIT2)) /* ISO7816-3 protocol T1 is selected*/
|
||||
#define UART_SCICTRL_TXRETRY(n) ((u32)((n&0x07)<<5)) /* number of retransmission*/
|
||||
#define UART_SCICTRL_GUARDTIME(n) ((u32)((n&0xFF)<<8)) /* Extra guard time*/
|
||||
#define UART_SCICTRL_SCIEN ((uint32_t)(BIT0)) /* enable asynchronous half-duplex smart card interface*/
|
||||
#define UART_SCICTRL_NACKDIS ((uint32_t)(BIT1)) /* NACK response is inhibited*/
|
||||
#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(BIT2)) /* ISO7816-3 protocol T1 is selected*/
|
||||
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /* number of retransmission*/
|
||||
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /* Extra guard time*/
|
||||
|
||||
/*********************************************************************
|
||||
* Macro defines for Macro defines for UART synchronous control register
|
||||
**********************************************************************/
|
||||
#define UART_SYNCCTRL_SYNC ((u32)(BIT0)) /* enable synchronous mode*/
|
||||
#define UART_SYNCCTRL_CSRC_MASTER ((u32)(BIT1)) /* synchronous master mode*/
|
||||
#define UART_SYNCCTRL_FES ((u32)(BIT2)) /* sample on falling edge*/
|
||||
#define UART_SYNCCTRL_TSBYPASS ((u32)(BIT3)) /* to be defined*/
|
||||
#define UART_SYNCCTRL_CSCEN ((u32)(BIT4)) /* continuous running clock enable (master mode only) */
|
||||
#define UART_SYNCCTRL_NOSTARTSTOP ((u32)(BIT5)) /* Do not send start/stop bit */
|
||||
#define UART_SYNCCTRL_CCCLR ((u32)(BIT6)) /* stop continuous clock */
|
||||
#define UART_SYNCCTRL_SYNC ((uint32_t)(BIT0)) /* enable synchronous mode*/
|
||||
#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(BIT1)) /* synchronous master mode*/
|
||||
#define UART_SYNCCTRL_FES ((uint32_t)(BIT2)) /* sample on falling edge*/
|
||||
#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(BIT3)) /* to be defined*/
|
||||
#define UART_SYNCCTRL_CSCEN ((uint32_t)(BIT4)) /* continuous running clock enable (master mode only) */
|
||||
#define UART_SYNCCTRL_NOSTARTSTOP ((uint32_t)(BIT5)) /* Do not send start/stop bit */
|
||||
#define UART_SYNCCTRL_CCCLR ((uint32_t)(BIT6)) /* stop continuous clock */
|
||||
|
||||
/*********************************************************************
|
||||
* Macro defines for Macro defines for UART Fractional divider register
|
||||
**********************************************************************/
|
||||
#define UART_FDR_DIVADDVAL(n) ((u32)(n&0x0F)) /* Baud-rate generation pre-scaler divisor */
|
||||
#define UART_FDR_MULVAL(n) ((u32)((n<<4)&0xF0)) /* Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_BITMASK ((u32)(0xFF)) /* UART Fractional Divider register bit mask */
|
||||
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /* Baud-rate generation pre-scaler divisor */
|
||||
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /* Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /* UART Fractional Divider register bit mask */
|
||||
|
||||
/*********************************************************************
|
||||
* Macro defines for Macro defines for UART Tx Enable register
|
||||
**********************************************************************/
|
||||
#define UART1_TER_TXEN ((u8)(BIT7)) /* Transmit enable bit */
|
||||
#define UART1_TER_BITMASK ((u8)(0x80)) /* UART Transmit Enable Register bit mask */
|
||||
#define UART1_TER_TXEN ((uint8_t)(BIT7)) /* Transmit enable bit */
|
||||
#define UART1_TER_BITMASK ((uint8_t)(0x80)) /* UART Transmit Enable Register bit mask */
|
||||
|
||||
#define UART0_2_3_TER_TXEN ((u8)(BIT0)) /* Transmit enable bit */
|
||||
#define UART0_2_3_TER_BITMASK ((u8)(0x01)) /* UART Transmit Enable Register bit mask */
|
||||
#define UART0_2_3_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */
|
||||
#define UART0_2_3_TER_BITMASK ((uint8_t)(0x01)) /* UART Transmit Enable Register bit mask */
|
||||
|
||||
/**********************************************************************
|
||||
* Macro defines for Macro defines for UART FIFO Level register
|
||||
**********************************************************************/
|
||||
#define UART_FIFOLVL_RX(n) ((u32)(n&0x0F)) /* Reflects the current level of the UART receiver FIFO */
|
||||
#define UART_FIFOLVL_TX(n) ((u32)((n>>8)&0x0F)) /* Reflects the current level of the UART transmitter FIFO */
|
||||
#define UART_FIFOLVL_BITMASK ((u32)(0x0F0F)) /* UART FIFO Level Register bit mask */
|
||||
#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) /* Reflects the current level of the UART receiver FIFO */
|
||||
#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) /* Reflects the current level of the UART transmitter FIFO */
|
||||
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /* UART FIFO Level Register bit mask */
|
||||
|
||||
/*********************************************************************
|
||||
* UART enum
|
||||
@ -328,17 +328,17 @@ void uart_init(uart_num_t uart_num,
|
||||
uart_databit_t data_nb_bits,
|
||||
uart_stopbit_t data_nb_stop,
|
||||
uart_parity_t data_parity,
|
||||
u16 uart_divisor,
|
||||
u8 uart_divaddval,
|
||||
u8 uart_mulval);
|
||||
uint16_t uart_divisor,
|
||||
uint8_t uart_divaddval,
|
||||
uint8_t uart_mulval);
|
||||
|
||||
uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num);
|
||||
|
||||
u8 uart_read(uart_num_t uart_num);
|
||||
uint8_t uart_read(uart_num_t uart_num);
|
||||
|
||||
u8 uart_read_timeout(uart_num_t uart_num, u32 rx_timeout_nb_cycles, uart_error_t* error);
|
||||
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error);
|
||||
|
||||
void uart_write(uart_num_t uart_num, u8 data);
|
||||
void uart_write(uart_num_t uart_num, uint8_t data);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
/* Set M0 in reset mode */
|
||||
void ipc_halt_m0(void)
|
||||
{
|
||||
volatile u32 rst_active_status1;
|
||||
volatile uint32_t rst_active_status1;
|
||||
|
||||
/* Check if M0 is reset by reading status */
|
||||
rst_active_status1 = RESET_ACTIVE_STATUS1;
|
||||
@ -37,9 +37,9 @@ void ipc_halt_m0(void)
|
||||
}
|
||||
}
|
||||
|
||||
void ipc_start_m0(u32 cm0_baseaddr)
|
||||
void ipc_start_m0(uint32_t cm0_baseaddr)
|
||||
{
|
||||
volatile u32 rst_active_status1;
|
||||
volatile uint32_t rst_active_status1;
|
||||
|
||||
/* Set M0 memory mapping to point to start of M0 image */
|
||||
CREG_M0APPMEMMAP = cm0_baseaddr;
|
||||
|
||||
@ -103,7 +103,7 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num)
|
||||
}
|
||||
|
||||
/* This Function Wait Data TX Ready, and Write Data to SSP */
|
||||
u16 ssp_transfer(ssp_num_t ssp_num, u16 data)
|
||||
uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data)
|
||||
{
|
||||
uint32_t ssp_port;
|
||||
|
||||
|
||||
@ -38,7 +38,7 @@
|
||||
#define UART_CGU_AUTOBLOCK_CLOCK_BIT 11
|
||||
#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
|
||||
|
||||
u32 dummy_read;
|
||||
uint32_t dummy_read;
|
||||
|
||||
/*
|
||||
* UART Init function
|
||||
@ -47,12 +47,12 @@ void uart_init(uart_num_t uart_num,
|
||||
uart_databit_t data_nb_bits,
|
||||
uart_stopbit_t data_nb_stop,
|
||||
uart_parity_t data_parity,
|
||||
u16 uart_divisor,
|
||||
u8 uart_divaddval,
|
||||
u8 uart_mulval)
|
||||
uint16_t uart_divisor,
|
||||
uint8_t uart_divaddval,
|
||||
uint8_t uart_mulval)
|
||||
{
|
||||
u32 lcr_config;
|
||||
u32 uart_port;
|
||||
uint32_t lcr_config;
|
||||
uint32_t uart_port;
|
||||
|
||||
uart_port = uart_num;
|
||||
|
||||
@ -167,8 +167,8 @@ void uart_init(uart_num_t uart_num,
|
||||
*/
|
||||
uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num)
|
||||
{
|
||||
u32 uart_port;
|
||||
u8 uart_status;
|
||||
uint32_t uart_port;
|
||||
uint8_t uart_status;
|
||||
uart_rx_data_ready_t data_ready;
|
||||
|
||||
uart_port = uart_num;
|
||||
@ -198,10 +198,10 @@ uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num)
|
||||
/*
|
||||
* This Function Wait until Data RX Ready, and return Data Read from UART.
|
||||
*/
|
||||
u8 uart_read(uart_num_t uart_num)
|
||||
uint8_t uart_read(uart_num_t uart_num)
|
||||
{
|
||||
u32 uart_port;
|
||||
u8 uart_val;
|
||||
uint32_t uart_port;
|
||||
uint8_t uart_val;
|
||||
|
||||
uart_port = uart_num;
|
||||
|
||||
@ -216,11 +216,11 @@ u8 uart_read(uart_num_t uart_num)
|
||||
/*
|
||||
* This Function Wait until Data RX Ready, and return Data Read from UART.
|
||||
*/
|
||||
u8 uart_read_timeout(uart_num_t uart_num, u32 rx_timeout_nb_cycles, uart_error_t* error)
|
||||
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error)
|
||||
{
|
||||
u32 uart_port;
|
||||
u8 uart_val;
|
||||
u32 counter;
|
||||
uint32_t uart_port;
|
||||
uint8_t uart_val;
|
||||
uint32_t counter;
|
||||
|
||||
uart_port = uart_num;
|
||||
|
||||
@ -250,9 +250,9 @@ u8 uart_read_timeout(uart_num_t uart_num, u32 rx_timeout_nb_cycles, uart_error_t
|
||||
/* This Function Wait Data TX Ready, and Write Data to UART
|
||||
if rx_timeout_nb_cycles = 0 Infinite wait
|
||||
*/
|
||||
void uart_write(uart_num_t uart_num, u8 data)
|
||||
void uart_write(uart_num_t uart_num, uint8_t data)
|
||||
{
|
||||
u32 uart_port;
|
||||
uint32_t uart_port;
|
||||
|
||||
uart_port = uart_num;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user