diff --git a/include/libopencm3/stm32f1/timer.h b/include/libopencm3/stm32_common/timer.h
similarity index 99%
rename from include/libopencm3/stm32f1/timer.h
rename to include/libopencm3/stm32_common/timer.h
index 7b5df860..c1eac99a 100644
--- a/include/libopencm3/stm32f1/timer.h
+++ b/include/libopencm3/stm32_common/timer.h
@@ -20,7 +20,7 @@
 #ifndef LIBOPENCM3_TIMER_H
 #define LIBOPENCM3_TIMER_H
 
-#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/stm32_common/memorymap.h>
 #include <libopencm3/cm3/common.h>
 
 /* --- Convenience macros -------------------------------------------------- */
diff --git a/include/libopencm3/stm32f2/timer.h b/include/libopencm3/stm32f2/timer.h
new file mode 100644
index 00000000..f7c82aef
--- /dev/null
+++ b/include/libopencm3/stm32f2/timer.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TIMER_F2_H
+#define LIBOPENCM3_TIMER_F2_H
+
+#include <libopencm3/stm32/timer.h>
+
+
+/* 
+ * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
+ * CNT, ARR, CCR1, CCR2, CCR3, CCR4
+ */
+
+/* Timer 2/5 option register (TIMx_OR) */
+#define TIM_OR(tim_base)              MMIO32(tim_base + 0x50)
+#define TIM2_OR                       TIM_OR(TIM2)
+#define TIM5_OR                       TIM_OR(TIM5)
+
+/* --- TIM2_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT    (0x0 << 10)
+#define TIM2_OR_ITR1_RMP_PTP            (0x1 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_FS_SOF     (0x2 << 10)
+#define TIM2_OR_ITR1_RMP_OTG_HS_SOF     (0x3 << 10)
+#define TIM2_OR_ITR1_RMP_MASK           (0x3 << 10)
+
+/* --- TIM5_OR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM5_OR_TI4_RMP_GPIO    (0x0 << 6)
+#define TIM5_OR_TI4_RMP_LSI     (0x1 << 6)
+#define TIM5_OR_TI4_RMP_LSE     (0x2 << 6)
+#define TIM5_OR_TI4_RMP_RTC     (0x3 << 6)
+#define TIM5_OR_TI4_RMP_MASK    (0x3 << 6)
+
+#endif