STM32F0: Add RCC API for I2C1 clock source
* Providing API to set/clear RCC_CFGR3_I2C1SW on STM32F0, duplicated from STM32F3 applies only to I2C1.
This commit is contained in:
parent
68fce5a0ab
commit
0d5e51a8a7
@ -533,6 +533,9 @@ void rcc_set_ppre(uint32_t ppre);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_prediv(uint32_t prediv);
|
||||
enum rcc_osc rcc_system_clock_source(void);
|
||||
void rcc_set_i2c_clock_hsi(uint32_t i2c);
|
||||
void rcc_set_i2c_clock_sysclk(uint32_t i2c);
|
||||
uint32_t rcc_get_i2c_clocks(void);
|
||||
enum rcc_osc rcc_usb_clock_source(void);
|
||||
void rcc_clock_setup_in_hse_8mhz_out_48mhz(void);
|
||||
void rcc_clock_setup_in_hsi_out_48mhz(void);
|
||||
|
@ -39,6 +39,7 @@
|
||||
#include <libopencm3/cm3/assert.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
#include <libopencm3/stm32/flash.h>
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
|
||||
/* Set the default clock frequencies */
|
||||
uint32_t rcc_ahb_frequency = 8000000; /* 8MHz after reset */
|
||||
@ -520,6 +521,25 @@ enum rcc_osc rcc_system_clock_source(void)
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
void rcc_set_i2c_clock_hsi(uint32_t i2c)
|
||||
{
|
||||
if (i2c == I2C1) {
|
||||
RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_set_i2c_clock_sysclk(uint32_t i2c)
|
||||
{
|
||||
if (i2c == I2C1) {
|
||||
RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t rcc_get_i2c_clocks(void)
|
||||
{
|
||||
return RCC_CFGR3 & RCC_CFGR3_I2C1SW;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief RCC Get the USB Clock Source.
|
||||
*
|
||||
|
Loading…
x
Reference in New Issue
Block a user