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stm32f3: rcc: Set prescalers properly.

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Copypasta from f4 rcc code was only modified to shift the result, but not clear
the existing settings properly. Add mask/shift definitions and use them
properly.
This commit is contained in:
Karl Palsson 2015-10-22 22:34:29 +00:00
parent ce9dab2a92
commit 10ef294e5d
2 changed files with 9 additions and 6 deletions
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3
include/libopencm3/stm32/f3/rcc.h
View File

@ -124,6 +124,7 @@
/* PPRE2: APB high-speed prescaler (APB2) */ /* PPRE2: APB high-speed prescaler (APB2) */
#define RCC_CFGR_PPRE2_SHIFT 11 #define RCC_CFGR_PPRE2_SHIFT 11
#define RCC_CFGR_PPRE2_MASK 0x7
/* 0XX: HCLK not divided */ /* 0XX: HCLK not divided */
#define RCC_CFGR_PPRE2_DIV_NONE 0x0 #define RCC_CFGR_PPRE2_DIV_NONE 0x0
@ -134,6 +135,7 @@
/* PPRE1:APB Low-speed prescaler (APB1) */ /* PPRE1:APB Low-speed prescaler (APB1) */
#define RCC_CFGR_PPRE1_SHIFT 8 #define RCC_CFGR_PPRE1_SHIFT 8
#define RCC_CFGR_PPRE1_MASK 0x7
/* 0XX: HCLK not divided */ /* 0XX: HCLK not divided */
#define RCC_CFGR_PPRE1_DIV_NONE 0x0 #define RCC_CFGR_PPRE1_DIV_NONE 0x0
#define RCC_CFGR_PPRE1_DIV_2 0x4 #define RCC_CFGR_PPRE1_DIV_2 0x4
@ -143,6 +145,7 @@
/* HPRE: HLCK prescaler */ /* HPRE: HLCK prescaler */
#define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_MASK 0xf
/* 0XXX: SYSCLK not divided */ /* 0XXX: SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV_NONE 0x0 #define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 0x8 #define RCC_CFGR_HPRE_DIV_2 0x8

12
lib/stm32/f3/rcc.c
View File

@ -343,8 +343,8 @@ void rcc_set_ppre2(uint32_t ppre2)
uint32_t reg32; uint32_t reg32;
reg32 = RCC_CFGR; reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << 11)); RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
} }
void rcc_set_ppre1(uint32_t ppre1) void rcc_set_ppre1(uint32_t ppre1)
@ -352,8 +352,8 @@ void rcc_set_ppre1(uint32_t ppre1)
uint32_t reg32; uint32_t reg32;
reg32 = RCC_CFGR; reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << 8)); RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
} }
void rcc_set_hpre(uint32_t hpre) void rcc_set_hpre(uint32_t hpre)
@ -361,8 +361,8 @@ void rcc_set_hpre(uint32_t hpre)
uint32_t reg32; uint32_t reg32;
reg32 = RCC_CFGR; reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << 4)); RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
} }