stm32f7: pwr: added basic support for pwr (VOS and overdrive)
This commit is contained in:
Matthew Lai
Karl Palsson
parent
2c0e71b3c7
commit
17553da946
282
include/libopencm3/stm32/f7/pwr.h
Normal file
282
include/libopencm3/stm32/f7/pwr.h
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@ -0,0 +1,282 @@
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/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32F7xx Power Control</b>
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@ingroup STM32F7xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2017 Matthew Lai <m@matthewlai.ca>
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@date 12 March 2017
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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/**@{*/
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR1) */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR1) */
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#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04)
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/* Power control register 2 (PWR_CR2) */
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08)
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/* Power control/status register 2 (PWR_CSR2) */
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#define PWR_CSR2 MMIO32(POWER_CONTROL_BASE + 0x0c)
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/* --- PWR_CR1 values ------------------------------------------------------- */
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/* Bits [31:20]: Reserved, must be kept at reset value. */
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/* UDEN[19:18]: Under-drive enable in stop mode */
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#define PWR_CR1_UDEN_LSB 18
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/** @defgroup pwr_uden Under-drive enable in stop mode
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR1_UDEN_DISABLED (0x0 << PWR_CR1_UDEN_LSB)
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#define PWR_CR1_UDEN_ENABLED (0x3 << PWR_CR1_UDEN_LSB)
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/**@}*/
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#define PWR_CR1_UDEN_MASK (0x3 << PWR_CR1_UDEN_LSB)
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/* ODSWEN: Over-drive switching enabled */
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#define PWR_CR1_ODSWEN (1 << 17)
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/* ODEN: Over-drive enable */
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#define PWR_CR1_ODEN (1 << 16)
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/* VOS[15:14]: Regulator voltage scaling output selection */
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#define PWR_CR1_VOS_LSB 14
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/** @defgroup pwr_vos Regulator voltage scaling output selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR1_VOS_SCALE_3 (0x1 << PWR_CR1_VOS_LSB)
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#define PWR_CR1_VOS_SCALE_2 (0x2 << PWR_CR1_VOS_LSB)
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#define PWR_CR1_VOS_SCALE_1 (0x3 << PWR_CR1_VOS_LSB)
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/**@}*/
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#define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_LSB)
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/* ADCDC1: Masks extra flash accesses by prefetch (see AN4073) */
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#define PWR_CR1_ADCDC1 (1 << 13)
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/* Bit 12: Reserved, must be kept at reset value. */
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/* MRUDS: Main regulator in deepsleep under-drive mode */
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#define PWR_CR1_MRUDS (1 << 11)
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/* LPUDS: Low-power regulator in deepsleep under-drive mode */
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#define PWR_CR1_LPUDS (1 << 10)
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/* FPDS: Flash power-down in Stop mode */
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#define PWR_CR1_FPDS (1 << 9)
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/* DBP: Disable backup domain write protection */
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#define PWR_CR1_DBP (1 << 8)
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/* PLS[7:5]: PVD level selection */
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#define PWR_CR1_PLS_LSB 5
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/** @defgroup pwr_pls PVD level selection
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CR1_PLS_2V0 (0x0 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V1 (0x1 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V3 (0x2 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
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#define PWR_CR1_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
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/**@}*/
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#define PWR_CR1_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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/* PVDE: Power voltage detector enable */
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#define PWR_CR1_PVDE (1 << 4)
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/* CSBF: Clear standby flag */
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#define PWR_CR1_CSBF (1 << 3)
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/* Bit 2: Reserved, must be kept at reset value. */
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/* PDDS: Power down deepsleep */
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#define PWR_CR1_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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#define PWR_CR1_LPDS (1 << 0)
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/* --- PWR_CSR1 values ------------------------------------------------------ */
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/* Bits [31:20]: Reserved, must be kept at reset value. */
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/* UDRDY[19:18]: Under-drive ready flag */
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#define PWR_CSR1_UDRDY_LSB 18
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/** @defgroup pwr_udrdy Under-drive ready flag
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@ingroup STM32F_pwr_defines
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@{*/
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#define PWR_CSR1_UDRDY_DISABLED (0x0 << PWR_CSR1_UDRDY_LSB)
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#define PWR_CSR1_UDRDY_ACTIVATED (0x3 << PWR_CSR1_UDRDY_LSB)
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/**@}*/
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#define PWR_CSR1_UDRDY_MASK (0x3 << PWR_CSR1_UDRDY_LSB)
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/* ODSWRDY: Over-drive mode switching ready */
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#define PWR_CSR1_ODSWRDY (1 << 17)
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/* ODRDY: Over-drive mode ready */
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#define PWR_CSR1_ODRDY (1 << 16)
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/* Bit 15: Reserved, must be kept at reset value. */
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/* VOSRDY: Regulator voltage scaling output selection ready bit */
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#define PWR_CSR1_VOSRDY (1 << 14)
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/* Bits [13:10]: Reserved, must be kept at reset value. */
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/* BRE: Backup regulator enable */
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#define PWR_CSR1_BRE (1 << 9)
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/* EIWUP: Enable internal wakeup */
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#define PWR_CSR1_EIWUP (1 << 8)
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/* Bits [7:4]: Reserved, must be kept at reset value. */
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/* BRR: Backup regulator ready */
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#define PWR_CSR1_BRR (1 << 3)
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/* PVDO: PVD output */
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#define PWR_CSR1_PVDO (1 << 2)
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/* SBF: Standby flag */
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#define PWR_CSR1_SBF (1 << 1)
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/* WUIF: Wakeup internal flag */
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#define PWR_CSR1_WUIF (1 << 0)
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/* --- PWR_CR2 values ------------------------------------------------------ */
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/* Bits [31:14]: Reserved, must be kept at reset value. */
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/* WUPP6: Wakeup pin polarity bit for PI11 */
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#define PWR_CR2_WUPP6 (1 << 13)
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/* WUPP5: Wakeup pin polarity bit for PI8 */
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#define PWR_CR2_WUPP5 (1 << 12)
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/* WUPP4: Wakeup pin polarity bit for PC13 */
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#define PWR_CR2_WUPP4 (1 << 11)
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/* WUPP3: Wakeup pin polarity bit for PC1 */
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#define PWR_CR2_WUPP3 (1 << 10)
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/* WUPP2: Wakeup pin polarity bit for PA2 */
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#define PWR_CR2_WUPP2 (1 << 9)
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/* WUPP1: Wakeup pin polarity bit for PA0 */
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#define PWR_CR2_WUPP1 (1 << 8)
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/* Bits [7:6]: Reserved, must be kept at reset value. */
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/* CWUPF6: Clear Wakeup Pin flag for PI11 */
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#define PWR_CR2_CWUPF6 (1 << 5)
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/* CWUPF5: Clear Wakeup Pin flag for PI8 */
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#define PWR_CR2_CWUPF5 (1 << 4)
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/* CWUPF4: Clear Wakeup Pin flag for PC13 */
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#define PWR_CR2_CWUPF4 (1 << 3)
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/* CWUPF3: Clear Wakeup Pin flag for PC1 */
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#define PWR_CR2_CWUPF3 (1 << 2)
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/* CWUPF2: Clear Wakeup Pin flag for PA2 */
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#define PWR_CR2_CWUPF2 (1 << 1)
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/* CWUPF1: Clear Wakeup Pin flag for PA0 */
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#define PWR_CR2_CWUPF1 (1 << 0)
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/* --- PWR_CSR2 values ------------------------------------------------------ */
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/* Bits [31:14]: Reserved, must be kept at reset value. */
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/* EWUP6: Enable Wakeup pin for PI11 */
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#define PWR_CSR2_EWUP6 (1 << 13)
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/* EWUP5: Enable Wakeup pin for PI8 */
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#define PWR_CSR2_EWUP5 (1 << 12)
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/* EWUP4: Enable Wakeup pin for PC13 */
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#define PWR_CSR2_EWUP4 (1 << 11)
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/* EWUP3: Enable Wakeup pin for PC1 */
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#define PWR_CSR2_EWUP3 (1 << 10)
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/* EWUP2: Enable Wakeup pin for PA2 */
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#define PWR_CSR2_EWUP2 (1 << 19)
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/* EWUP1: Enable Wakeup pin for PA0 */
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#define PWR_CSR2_EWUP1 (1 << 18)
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/* Bits [7:6]: Reserved, must be kept at reset value. */
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/* WUPF6: Wakeup Pin flag for PI11 */
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#define PWR_CSR2_WUPF6 (1 << 5)
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/* WUPF5: Wakeup Pin flag for PI8 */
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#define PWR_CSR2_WUPF5 (1 << 4)
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/* WUPF4: Wakeup Pin flag for PC13 */
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#define PWR_CSR2_WUPF4 (1 << 3)
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/* WUPF3: Wakeup Pin flag for PC1 */
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#define PWR_CSR2_WUPF3 (1 << 2)
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/* WUPF2: Wakeup Pin flag for PA2 */
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#define PWR_CSR2_WUPF2 (1 << 1)
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/* WUPF1: Wakeup Pin flag for PA0 */
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#define PWR_CSR2_WUPF1 (1 << 0)
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/* --- Function prototypes ------------------------------------------------- */
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enum pwr_vos_scale {
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PWR_SCALE1, /** <= 180MHz w/o overdrive, <= 216MHz w/ overdrive */
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PWR_SCALE2, /** <= 168MHz w/o overdrive, <= 180MHz w/ overdrive */
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PWR_SCALE3, /** <= 144MHz */
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};
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BEGIN_DECLS
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void pwr_set_vos_scale(enum pwr_vos_scale scale);
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void pwr_enable_overdrive(void);
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void pwr_disable_overdrive(void);
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END_DECLS
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#endif
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@ -36,6 +36,8 @@
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/f7/pwr.h>
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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@ -617,7 +619,8 @@ struct rcc_clock_scale {
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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uint8_t power_save;
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enum pwr_vos_scale vos_scale;
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uint8_t overdrive;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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};
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@ -30,6 +30,8 @@
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# include <libopencm3/stm32/f3/pwr.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/pwr.h>
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#elif defined(STM32F7)
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# include <libopencm3/stm32/f7/pwr.h>
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#elif defined(STM32L1)
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# include <libopencm3/stm32/l1/pwr.h>
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#elif defined(STM32L0)
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@ -42,7 +42,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS)
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ARFLAGS = rcs
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OBJS = rcc.o gpio.o gpio_common_all.o gpio_common_f0234.o
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OBJS = pwr.o rcc.o gpio.o gpio_common_all.o gpio_common_f0234.o
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OBJS += rcc_common_all.o flash_common_f234.o flash_common_f24.o
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66
lib/stm32/f7/pwr.c
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66
lib/stm32/f7/pwr.c
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@ -0,0 +1,66 @@
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/** @defgroup pwr_file PWR
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*
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* @ingroup STM32F7xx
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*
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* @brief <b>libopencm3 STM32F7xx Power Control</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
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* @author @htmlonly © @endhtmlonly 2017 Matthew Lai <m@matthewlai.ca>
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*
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* @date 12 March 2017
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*
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* This library supports the power control system for the
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* STM32F7 series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
|
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* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
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* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/pwr.h>
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void pwr_set_vos_scale(enum pwr_vos_scale scale)
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{
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PWR_CR1 &= ~PWR_CR1_VOS_MASK;
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if (scale == PWR_SCALE1) {
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PWR_CR1 |= PWR_CR1_VOS_SCALE_1;
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} else if (scale == PWR_SCALE2) {
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PWR_CR1 |= PWR_CR1_VOS_SCALE_2;
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} else if (scale == PWR_SCALE3) {
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PWR_CR1 |= PWR_CR1_VOS_SCALE_3;
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}
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}
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void pwr_enable_overdrive(void)
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{
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PWR_CR1 |= PWR_CR1_ODEN;
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while (!(PWR_CSR1 & PWR_CSR1_ODRDY));
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PWR_CR1 |= PWR_CR1_ODSWEN;
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while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY));
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}
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void pwr_disable_overdrive(void)
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{
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PWR_CR1 &= ~(PWR_CR1_ODEN | PWR_CR1_ODSWEN);
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while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY));
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}
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@ -1,5 +1,6 @@
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/flash.h>
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uint32_t rcc_ahb_frequency = 16000000;
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@ -12,11 +13,13 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.plln = 432,
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.pllp = 2,
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.pllq = 9,
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.flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN |
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FLASH_ACR_LATENCY_7WS,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN |
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FLASH_ACR_LATENCY_7WS,
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.vos_scale = PWR_SCALE1,
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.overdrive = 1,
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.apb1_frequency = 108000000,
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.apb2_frequency = 216000000,
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},
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@ -338,13 +341,13 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
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rcc_osc_on(RCC_HSE);
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rcc_wait_for_osc_ready(RCC_HSE);
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/* Enable/disable high performance mode */
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/* if (!clock->power_save) {
|
||||
pwr_set_vos_scale(SCALE1);
|
||||
} else {
|
||||
pwr_set_vos_scale(SCALE2);
|
||||
rcc_periph_clock_enable(RCC_PWR);
|
||||
pwr_set_vos_scale(clock->vos_scale);
|
||||
|
||||
if (clock->overdrive) {
|
||||
pwr_enable_overdrive();
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user