Factor out cm3/common.h and cm3/memorymap.h.

This commit is contained in:
Uwe Hermann 2010-12-30 00:53:52 +01:00
parent 01bfbfed41
commit 17b2e87ba3
30 changed files with 88 additions and 63 deletions

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@ -34,7 +34,7 @@ Development guidelines
- All subsystem-specific function names should be prefixed with the
subsystem name. For example, gpio_set_mode() or rcc_osc_on().
- Please consistently use the short form types from <libopenstm32/common.h>,
- Please consistently use the short form types from <cm3/common.h>,
e.g. u8, u16, u32, and so on.
- Variables that are used to store register values read from registers or

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@ -20,7 +20,7 @@
#ifndef DOGM128_H
#define DOGM128_H
#include <libopenstm32/common.h>
#include <cm3/common.h>
#include <libopenstm32/gpio.h>
#include <libopenstm32/spi.h>

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@ -17,8 +17,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENSTM32_COMMON_H
#define LIBOPENSTM32_COMMON_H
#ifndef CM3_COMMON_H
#define CM3_COMMON_H
#include <stdint.h>
#include <stdbool.h>

58
include/cm3/memorymap.h Normal file
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@ -0,0 +1,58 @@
/*
* This file is part of the libopenstm32 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CM3_MEMORYMAP_H
#define CM3_MEMORYMAP_H
/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
/* Private peripheral bus - Internal */
#define PPBI_BASE 0xE0000000
#define ITM_BASE (PPBI_BASE + 0x0000)
#define DWT_BASE (PPBI_BASE + 0x1000)
#define FPB_BASE (PPBI_BASE + 0x2000)
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
/* --- ITM: Instrumentation Trace Macrocell --- */
/* TODO */
/* --- DWT: Data Watchpoint and Trace unit --- */
/* TODO */
/* --- FPB: Flash Patch and Breakpoint unit --- */
/* TODO */
/* --- SCS: System Control Space --- */
/* ITR: Interrupt Type Register */
#define ITR_BASE (SCS_BASE + 0x0000)
/* SYS_TICK: System Timer */
#define SYS_TICK_BASE (SCS_BASE + 0x0010)
/* NVIC: Nested Vector Interrupt Controller */
#define NVIC_BASE (SCS_BASE + 0x0100)
/* SCB: System Control Block */
#define SCB_BASE (SCS_BASE + 0x0D00)
/* STE: Software Trigger Interrupt Register */
#define STIR_BASE (SCS_BASE + 0x0F00)
/* ID: ID space */
#define ID_BASE (SCS_BASE + 0x0FD0)
#endif

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_LIBOPENSTM32_H
#include <libopenstm32/tools.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
#include <libopenstm32/memorymap.h>
#include <libopenstm32/rcc.h>
#include <libopenstm32/gpio.h>

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_ADC_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_BKP_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- BKP registers ------------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_CAN_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_CRC_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- CRC registers ------------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_DMA_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_ETHERNET_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* Ethernet MAC registers */
#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00)

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_EXTI_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- EXTI registers ------------------------------------------------------ */

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@ -29,7 +29,7 @@
#define LIBOPENSTM32_FLASH_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- FLASH registers ----------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_GPIO_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_I2C_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_IWDG_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- IWDG registers ------------------------------------------------------ */

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@ -20,40 +20,7 @@
#ifndef LIBOPENSTM32_MEMORYMAP_H
#define LIBOPENSTM32_MEMORYMAP_H
/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
/* Private peripheral bus - Internal */
#define PPBI_BASE 0xE0000000
#define ITM_BASE (PPBI_BASE + 0x0000)
#define DWT_BASE (PPBI_BASE + 0x1000)
#define FPB_BASE (PPBI_BASE + 0x2000)
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
/* --- ITM: Instrumentation Trace Macrocell --- */
/* TODO */
/* --- DWT: Data Watchpoint and Trace unit --- */
/* TODO */
/* --- FPB: Flash Patch and Breakpoint unit --- */
/* TODO */
/* --- SCS: System Control Space --- */
/* ITR: Interrupt Type Register */
#define ITR_BASE (SCS_BASE + 0x0000)
/* SYS_TICK: System Timer */
#define SYS_TICK_BASE (SCS_BASE + 0x0010)
/* NVIC: Nested Vector Interrupt Controller */
#define NVIC_BASE (SCS_BASE + 0x0100)
/* SCB: System Control Block */
#define SCB_BASE (SCS_BASE + 0x0D00)
/* STE: Software Trigger Interrupt Register */
#define STIR_BASE (SCS_BASE + 0x0F00)
/* ID: ID space */
#define ID_BASE (SCS_BASE + 0x0FD0)
#include <cm3/memorymap.h>
/* --- STM32 specific peripheral definitions ------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_NVIC_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- NVIC Registers ------------------------------------------------------ */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_PWR_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- PWR registers ------------------------------------------------------- */

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@ -22,7 +22,7 @@
#define LIBOPENSTM32_RCC_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */
/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_RTC_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
#include <libopenstm32/pwr.h>
/* --- RTC registers ------------------------------------------------------- */

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@ -22,7 +22,7 @@
#define LIBOPENSTM32_SCB_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_SPI_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* Registers can be accessed as 16bit or 32bit values. */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_SYSTICK_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- SYSTICK registers --------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_TIMER_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_USART_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_USB_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
#include <libopenstm32/tools.h>
/* --- USB base addresses -------------------------------------------------- */

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@ -21,7 +21,7 @@
#define LIBOPENSTM32_WWDG_H
#include <libopenstm32/memorymap.h>
#include <libopenstm32/common.h>
#include <cm3/common.h>
/* --- WWDG registers ------------------------------------------------------ */

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@ -21,7 +21,7 @@
#define __USBSTD_H
#include <stdint.h>
#include <libopenstm32/common.h> /* TODO: Move elsewhere? */
#include <cm3/common.h>
/*
* This file contains structure definitions for the USB control structures

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@ -17,7 +17,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopenstm32/common.h>
#include <cm3/common.h>
#include <libopenstm32/tools.h>
#include <libopenstm32/usb.h>
#include <usb/usbd.h>