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stm32f42/f43: rcc: add 180 MHz clock options

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This commit is contained in:
Alfred Klomp 2018-11-12 17:06:59 +01:00 committed by Karl Palsson
parent f0e5c73d98
commit 1adc418f9a
2 changed files with 65 additions and 0 deletions
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1
include/libopencm3/stm32/f4/rcc.h
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@ -770,6 +770,7 @@ enum rcc_clock_3v3 {
RCC_CLOCK_3V3_84MHZ,
RCC_CLOCK_3V3_120MHZ,
RCC_CLOCK_3V3_168MHZ,
RCC_CLOCK_3V3_180MHZ,
RCC_CLOCK_3V3_END
};

64
lib/stm32/f4/rcc.c
View File

@ -114,6 +114,22 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 180MHz */
.pllm = 8,
.plln = 360,
.pllp = 2,
.pllq = 8,
.pllr = 0,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_5WS,
.ahb_frequency = 180000000,
.apb1_frequency = 45000000,
.apb2_frequency = 90000000,
},
};
const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
@ -181,6 +197,22 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 180MHz */
.pllm = 12,
.plln = 360,
.pllp = 2,
.pllq = 8,
.pllr = 0,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_5WS,
.ahb_frequency = 180000000,
.apb1_frequency = 45000000,
.apb2_frequency = 90000000,
},
};
const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
@ -248,6 +280,22 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 180MHz */
.pllm = 16,
.plln = 360,
.pllp = 2,
.pllq = 8,
.pllr = 0,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_5WS,
.ahb_frequency = 180000000,
.apb1_frequency = 45000000,
.apb2_frequency = 90000000,
},
};
const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
@ -315,6 +363,22 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 180MHz */
.pllm = 25,
.plln = 360,
.pllp = 2,
.pllq = 8,
.pllr = 0,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_5WS,
.ahb_frequency = 180000000,
.apb1_frequency = 45000000,
.apb2_frequency = 90000000,
},
};
void rcc_osc_ready_int_clear(enum rcc_osc osc)