[Style] Fixed all style errors in the efm32.
This commit is contained in:
Piotr Esden-Tempski
parent
77354cb371
commit
1f6fd11dd9
@ -405,7 +405,8 @@ void adc_enable_scan_prs_trigger(uint32_t adc);
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void adc_disable_scan_prs_trigger(uint32_t adc);
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void adc_set_scan_acquisition_cycle(uint32_t adc, uint32_t at);
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void adc_set_scan_reference(uint32_t adc, uint32_t ref);
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void adc_set_scan_channel(uint32_t adc, uint8_t length, uint8_t channel[]);
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void adc_set_scan_channel(uint32_t adc, uint8_t length,
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uint8_t channel[]);
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void adc_set_scan_resolution(uint32_t adc, uint32_t res);
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void adc_set_scan_left_aligned(uint32_t adc);
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void adc_set_scan_right_aligned(uint32_t adc);
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@ -161,35 +161,57 @@
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#define CMU_HFCORECLKDIV_HFCORECLKDIV(v) \
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(((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \
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CMU_HFCORECLKDIV_HFCORECLKDIV_MASK)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK CMU_HFCORECLKDIV_HFCORECLKDIV(0)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 CMU_HFCORECLKDIV_HFCORECLKDIV(1)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 CMU_HFCORECLKDIV_HFCORECLKDIV(2)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 CMU_HFCORECLKDIV_HFCORECLKDIV(3)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 CMU_HFCORECLKDIV_HFCORECLKDIV(4)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 CMU_HFCORECLKDIV_HFCORECLKDIV(5)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 CMU_HFCORECLKDIV_HFCORECLKDIV(6)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 CMU_HFCORECLKDIV_HFCORECLKDIV(7)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 CMU_HFCORECLKDIV_HFCORECLKDIV(8)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 CMU_HFCORECLKDIV_HFCORECLKDIV(9)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK \
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CMU_HFCORECLKDIV_HFCORECLKDIV(0)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(1)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(2)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(3)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(4)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(5)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(6)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(7)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(8)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 \
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CMU_HFCORECLKDIV_HFCORECLKDIV(9)
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256
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#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 \
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CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512
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/* CMU_HFPERCLKDIV */
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#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8)
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT (0)
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK (0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT)
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK \
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(0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT)
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#define CMU_HFPERCLKDIV_HFPERCLKDIV(v) \
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(((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
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(((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \
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CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
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#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK CMU_HFPERCLKDIV_HFPERCLKDIV(0)
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#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2 CMU_HFPERCLKDIV_HFPERCLKDIV(1)
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#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4 CMU_HFPERCLKDIV_HFPERCLKDIV(2)
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@ -202,16 +224,26 @@
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#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512 CMU_HFPERCLKDIV_HFPERCLKDIV(9)
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/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256
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#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 \
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CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512
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/* CMU_HFRCOCTRL */
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#define CMU_HFRCOCTRL_SUDELAY_SHIFT (12)
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@ -197,7 +197,8 @@
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/* DAC_CAL */
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#define DAC_CAL_GAIN_SHIFT (16)
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#define DAC_CAL_GAIN_MASK (0x7F << DAC_CAL_GAIN_SHIFT)
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#define DAC_CAL_GAIN(v) (((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK)
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#define DAC_CAL_GAIN(v) \
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(((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK)
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#define DAC_CAL_CH1OFFSET_SHIFT (8)
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#define DAC_CAL_CH1OFFSET_MASK (0x3F << DAC_CAL_CH1OFFSET_SHIFT)
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@ -215,8 +216,8 @@
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#define DAC_BIASPROG_OPA2BIASPROG_SHIFT (8)
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#define DAC_BIASPROG_OPA2BIASPROG_MASK (0xF << DAC_BIASPROG_OPA2BIASPROG_SHIFT)
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#define DAC_BIASPROG_OPA2BIASPROG(v) \
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(((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \
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DAC_BIASPROG_OPA2BIASPROG_MASK
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((((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \
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DAC_BIASPROG_OPA2BIASPROG_MASK)
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#define DAC_BIASPROG_HALFBIAS (1 << 6)
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@ -263,7 +264,7 @@
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#define DAC_OPA0MUX_RESSEL_SHIFT (28)
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#define DAC_OPA0MUX_RESSEL_MASK (0x7 << DAC_OPA0MUX_RESSEL_SHIFT)
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#define DAC_OPA0MUX_RESSEL_RESSEL(v) \
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(((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK)
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((((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK)
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#define DAC_OPA0MUX_RESSEL_RESSEL_RESx(x) DAC_OPA0MUX_RESSEL_RESSEL(x)
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#define DAC_OPA0MUX_RESSEL_RESSEL_RES0 DAC_OPA0MUX_RESSEL_RESSEL_RESx(0)
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#define DAC_OPA0MUX_RESSEL_RESSEL_RES1 DAC_OPA0MUX_RESSEL_RESSEL_RESx(1)
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@ -331,7 +332,7 @@
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#define DAC_OPA1MUX_RESSEL_SHIFT (28)
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#define DAC_OPA1MUX_RESSEL_MASK (0x7 << DAC_OPA1MUX_RESSEL_SHIFT)
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#define DAC_OPA1MUX_RESSEL_RESSEL(v) \
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(((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK)
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((((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK)
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#define DAC_OPA1MUX_RESSEL_RESSEL_RESx(x) DAC_OPA1MUX_RESSEL_RESSEL(x)
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#define DAC_OPA1MUX_RESSEL_RESSEL_RES0 DAC_OPA1MUX_RESSEL_RESSEL_RESx(0)
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#define DAC_OPA1MUX_RESSEL_RESSEL_RES1 DAC_OPA1MUX_RESSEL_RESSEL_RESx(1)
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@ -400,7 +401,7 @@
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#define DAC_OPA2MUX_RESSEL_SHIFT (28)
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#define DAC_OPA2MUX_RESSEL_MASK (0x7 << DAC_OPA2MUX_RESSEL_SHIFT)
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#define DAC_OPA2MUX_RESSEL_RESSEL(v) \
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(((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK)
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((((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK)
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#define DAC_OPA2MUX_RESSEL_RESSEL_RESx(x) DAC_OPA2MUX_RESSEL_RESSEL(x)
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#define DAC_OPA2MUX_RESSEL_RESSEL_RES0 DAC_OPA2MUX_RESSEL_RESSEL_RESx(0)
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#define DAC_OPA2MUX_RESSEL_RESSEL_RES1 DAC_OPA2MUX_RESSEL_RESSEL_RESx(1)
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@ -495,7 +496,8 @@ void dac_set_conversion_mode(uint32_t dac_base, uint32_t convmode);
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void dac_enable_sine(uint32_t dac_base);
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void dac_disable_sine(uint32_t dac_base);
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void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan, enum prs_ch prs_chan);
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void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan,
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enum prs_ch prs_chan);
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void dac_enable_prs_trigger(uint32_t dac_base, enum dac_ch ch);
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void dac_disable_prs_trigger(uint32_t dac_base, enum dac_ch ch);
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void dac_enable_auto_refresh(uint32_t dac_base, enum dac_ch ch);
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@ -555,33 +555,40 @@
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#define DMA_CH_CTRL_SIGSEL_AES_KEY_WR DMA_CH_CTRL_SIGSEL(3)
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#define DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV DMA_CH_CTRL_SIGSEL(0)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x) DMA_CH_CTRL_SIGSEL(x)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(0)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(1)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY \
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DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(0)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY \
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DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(1)
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#define DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL DMA_CH_CTRL_SIGSEL(2)
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#define DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY DMA_CH_CTRL_SIGSEL(3)
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/**
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* Application need to allocate (DMA_DESC_CH_SIZE * N) byte
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* Application needs to allocate (DMA_DESC_CH_SIZE * N) byte
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* where N is the number of first N channels to use.
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* and this allocated memory need to be assigned to DMA using
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* and this allocated memory needs to be assigned to DMA using
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* dma_set_desc_address().
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*
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* if the application code need alternate descriptor facility also.
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* it need to allocate the required memory (usually equal that of above)
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* if the application code needs alternate descriptor facility also.
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* it needs to allocate the required memory (usually equal to the one above)
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* and assign the memory using dma_set_alternate_desc_address()
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*
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* rest of the work will be transparently managed by convient functions.
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* rest of the work will be transparently managed by convience functions.
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*
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* all the memory above should be aligned to 256bit
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* (ie LSB 8bits of array address should be 0)
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* use gcc's __attribute__((aligned(256)))
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*/
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#define DMA_DESC_CH_SIZE (0x4 * 0x4)
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#define DMA_DESC_CHx_BASE(base, x) ((base) + ((x) * DMA_DESC_CH_SIZE))
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#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00)
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#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04)
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#define DMA_DESC_CHx_CFG(base, x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08)
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#define DMA_DESC_CHx_USER_DATA(base, x) MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C)
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#define DMA_DESC_CHx_BASE(base, x) \
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((base) + ((x) * DMA_DESC_CH_SIZE))
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#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x) \
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MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00)
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#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x) \
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MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04)
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#define DMA_DESC_CHx_CFG(base, x) \
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MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08)
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#define DMA_DESC_CHx_USER_DATA(base, x) \
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MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C)
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/* DMA_DESC_CH_CFG */
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#define DMA_DESC_CH_CFG_DEST_INC_SHIFT (30)
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@ -751,7 +758,7 @@ void dma_disable(void);
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bool dma_get_wait_on_request_flag(enum dma_ch ch);
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//bool dma_get_wait_flag(enum dma_ch ch);
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/*bool dma_get_wait_flag(enum dma_ch ch);*/
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void dma_enable_with_unprivileged_access(void);
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void dma_enable_with_privileged_access(void);
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@ -780,7 +787,7 @@ void dma_clear_bus_error_flag(void);
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bool dma_get_request_flag(enum dma_ch ch);
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//bool dma_get_single_request_flag(enum dma_ch ch);
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/*bool dma_get_single_request_flag(enum dma_ch ch);*/
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bool dma_get_bus_error_interrupt_flag(void);
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bool dma_get_done_interrupt_flag(enum dma_ch ch);
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@ -808,37 +815,53 @@ void dma_enable_loop(enum dma_ch ch);
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void dma_disable_loop(enum dma_ch ch);
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/* descriptor convient function. (prefix "dma_desc_") */
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void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size);
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void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc);
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void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size);
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void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc);
|
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void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem size);
|
||||
void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem inc);
|
||||
void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem size);
|
||||
void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem inc);
|
||||
|
||||
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, enum dma_r_power r_power);
|
||||
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_r_power r_power);
|
||||
|
||||
void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch);
|
||||
void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch);
|
||||
|
||||
void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count);
|
||||
|
||||
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, uint32_t user_data);
|
||||
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t user_data);
|
||||
uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch);
|
||||
|
||||
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, uint32_t src);
|
||||
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, uint32_t dest);
|
||||
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t src);
|
||||
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t dest);
|
||||
|
||||
void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode);
|
||||
|
||||
/* based on descriptor convient, macro are passing
|
||||
* {DMA_CTRLBASE, CTRL_ALTCTRLBASE} as per naming */
|
||||
#define dma_set_dest_size(ch, size) dma_desc_set_dest_size(DMA_CTRLBASE, ch, size)
|
||||
#define dma_set_dest_inc(ch, inc) dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc)
|
||||
#define dma_set_src_size(ch, size) dma_desc_set_src_size(DMA_CTRLBASE, ch, size)
|
||||
#define dma_set_src_inc(ch, inc) dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc)
|
||||
#define dma_set_dest_size(ch, size) \
|
||||
dma_desc_set_dest_size(DMA_CTRLBASE, ch, size)
|
||||
#define dma_set_dest_inc(ch, inc) \
|
||||
dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc)
|
||||
#define dma_set_src_size(ch, size) \
|
||||
dma_desc_set_src_size(DMA_CTRLBASE, ch, size)
|
||||
#define dma_set_src_inc(ch, inc) \
|
||||
dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc)
|
||||
|
||||
#define dma_set_alt_dest_size(ch, size) dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size)
|
||||
#define dma_set_alt_dest_inc(ch, inc) dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc)
|
||||
#define dma_set_alt_src_size(ch, size) dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size)
|
||||
#define dma_set_alt_src_inc(ch, inc) dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc)
|
||||
#define dma_set_alt_dest_size(ch, size) \
|
||||
dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size)
|
||||
#define dma_set_alt_dest_inc(ch, inc) \
|
||||
dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc)
|
||||
#define dma_set_alt_src_size(ch, size) \
|
||||
dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size)
|
||||
#define dma_set_alt_src_inc(ch, inc) \
|
||||
dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc)
|
||||
|
||||
#define dma_set_r_power(ch, r_power) \
|
||||
dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power)
|
||||
@ -864,8 +887,10 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode);
|
||||
#define dma_set_alt_user_data(ch, user_data) \
|
||||
dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data)
|
||||
|
||||
#define dma_get_user_data(ch) dma_desc_get_user_data(DMA_CTRLBASE, ch)
|
||||
#define dma_get_alt_user_data(ch) dma_desc_get_user_data(DMA_ALTCTRLBASE, ch)
|
||||
#define dma_get_user_data(ch) \
|
||||
dma_desc_get_user_data(DMA_CTRLBASE, ch)
|
||||
#define dma_get_alt_user_data(ch) \
|
||||
dma_desc_get_user_data(DMA_ALTCTRLBASE, ch)
|
||||
|
||||
#define dma_set_src_address(ch, src) \
|
||||
dma_desc_set_src_address(DMA_CTRLBASE, ch, src)
|
||||
@ -876,8 +901,10 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode);
|
||||
#define dma_set_alt_dest_address(ch, dest) \
|
||||
dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest)
|
||||
|
||||
#define dma_set_mode(ch, mode) dma_desc_set_mode(DMA_CTRLBASE, ch, mode)
|
||||
#define dma_set_alt_mode(ch, mode) dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode)
|
||||
#define dma_set_mode(ch, mode) \
|
||||
dma_desc_set_mode(DMA_CTRLBASE, ch, mode)
|
||||
#define dma_set_alt_mode(ch, mode) \
|
||||
dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode)
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@ -43,7 +43,8 @@
|
||||
/* EMU_CTRL */
|
||||
#define EMU_CTRL_EM4CTRL_SHIFT (2)
|
||||
#define EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT)
|
||||
#define EMU_CTLR_EM4CTRL(v) (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK)
|
||||
#define EMU_CTLR_EM4CTRL(v) \
|
||||
(((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK)
|
||||
|
||||
#define EMU_CTRL_EM2BLOCK (1 << 1)
|
||||
#define EMU_CTRL_EMVREG (1 << 0)
|
||||
@ -162,23 +163,27 @@
|
||||
#define EMU_BUBODBUVINCAL_RANGE_SHIFT (3)
|
||||
#define EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT)
|
||||
#define EMU_BUBODBUVINCAL_RANGE(v) \
|
||||
(((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & EMU_BUBODBUVINCAL_RANGE_MASK)
|
||||
(((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \
|
||||
EMU_BUBODBUVINCAL_RANGE_MASK)
|
||||
|
||||
#define EMU_BUBODBUVINCAL_THRES_SHIFT (0)
|
||||
#define EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT)
|
||||
#define EMU_BUBODBUVINCAL_THRES(v) \
|
||||
(((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & EMU_BUBODBUVINCAL_THRES_MASK)
|
||||
(((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \
|
||||
EMU_BUBODBUVINCAL_THRES_MASK)
|
||||
|
||||
/* EMU_BUBODUNREGCAL */
|
||||
#define EMU_BUBODUNREGCAL_RANGE_SHIFT (3)
|
||||
#define EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT)
|
||||
#define EMU_BUBODUNREGCAL_RANGE(v) \
|
||||
(((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & EMU_BUBODUNREGCAL_RANGE_MASK)
|
||||
(((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \
|
||||
EMU_BUBODUNREGCAL_RANGE_MASK)
|
||||
|
||||
#define EMU_BUBODUNREGCAL_THRES_SHIFT (0)
|
||||
#define EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT)
|
||||
#define EMU_BUBODUNREGCAL_THRES(v) \
|
||||
(((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & EMU_BUBODUNREGCAL_THRES_MASK)
|
||||
(((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \
|
||||
EMU_BUBODUNREGCAL_THRES_MASK)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -311,7 +311,8 @@ void gpio_enable_lock(void);
|
||||
void gpio_disable_lock(void);
|
||||
bool gpio_get_lock_flag(void);
|
||||
|
||||
void gpio_set_drive_strength(uint32_t gpio_port, enum gpio_drive_strength driver_stength);
|
||||
void gpio_set_drive_strength(uint32_t gpio_port,
|
||||
enum gpio_drive_strength driver_stength);
|
||||
void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios);
|
||||
|
||||
void gpio_set(uint32_t gpio_port, uint16_t gpios);
|
||||
|
||||
@ -42,7 +42,8 @@
|
||||
/* I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_SHIFT (16)
|
||||
#define I2C_CTRL_CLTO_MASK (0x7 << I2C_CTRL_CLTO_SHIFT)
|
||||
#define I2C_CTRL_CLTO(v) (((v) <<I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK)
|
||||
#define I2C_CTRL_CLTO(v) \
|
||||
(((v) << I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK)
|
||||
#define I2C_CTRL_CLTO_OFF I2C_CTRL_CLTO(0)
|
||||
#define I2C_CTRL_CLTO_40PCC I2C_CTRL_CLTO(1)
|
||||
#define I2C_CTRL_CLTO_80PCC I2C_CTRL_CLTO(2)
|
||||
@ -54,7 +55,8 @@
|
||||
|
||||
#define I2C_CTRL_BTO_SHIFT (12)
|
||||
#define I2C_CTRL_BTO_MASK (0x3 << I2C_CTRL_BTO_SHIFT)
|
||||
#define I2C_CTRL_BTO(v) (((v) <<I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK)
|
||||
#define I2C_CTRL_BTO(v) \
|
||||
(((v) << I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK)
|
||||
#define I2C_CTRL_BTO_OFF I2C_CTRL_BTO(0)
|
||||
#define I2C_CTRL_BTO_40PCC I2C_CTRL_BTO(1)
|
||||
#define I2C_CTRL_BTO_80PCC I2C_CTRL_BTO(2)
|
||||
@ -62,7 +64,8 @@
|
||||
|
||||
#define I2C_CTRL_CLHR_SHIFT (12)
|
||||
#define I2C_CTRL_CLHR_MASK (0x3 << I2C_CTRL_CLHR_SHIFT)
|
||||
#define I2C_CTRL_CLHR(v) (((v) <<I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK)
|
||||
#define I2C_CTRL_CLHR(v) \
|
||||
(((v) << I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK)
|
||||
#define I2C_CTRL_CLHR_STANDARD I2C_CTRL_CLHR(0)
|
||||
#define I2C_CTRL_CLHR_ASYMMETRIC I2C_CTRL_CLHR(1)
|
||||
#define I2C_CTRL_CLHR_FAST I2C_CTRL_CLHR(2)
|
||||
@ -88,7 +91,8 @@
|
||||
/* I2C_STATE */
|
||||
#define I2C_STATE_STATE_SHIFT (5)
|
||||
#define I2C_STATE_STATE_MASK (0x7 << I2C_STATE_STATE_SHIFT)
|
||||
#define I2C_STATE_STATE(v) (((v) <<I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK)
|
||||
#define I2C_STATE_STATE(v) \
|
||||
(((v) << I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK)
|
||||
#define I2C_STATE_STATE_IDLE I2C_STATE_STATE(0)
|
||||
#define I2C_STATE_STATE_WAIT I2C_STATE_STATE(1)
|
||||
#define I2C_STATE_STATE_START I2C_STATE_STATE(2)
|
||||
@ -117,12 +121,14 @@
|
||||
/* I2C_CLKDIV */
|
||||
#define I2C_CLKDIV_DIV_SHIFT (0)
|
||||
#define I2C_CLKDIV_DIV_MASK (0xFF << I2C_CLKDIV_DIV_SHIFT)
|
||||
#define I2C_CLKDIV_DIV(v) (((v) <<I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK)
|
||||
#define I2C_CLKDIV_DIV(v) \
|
||||
(((v) << I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK)
|
||||
|
||||
/* I2C_SADDR */
|
||||
#define I2C_SADDR_ADDR_SHIFT (0)
|
||||
#define I2C_SADDR_ADDR_MASK (0xFF << I2C_SADDR_ADDR_SHIFT)
|
||||
#define I2C_SADDR_ADDR(v) (((v) <<I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK)
|
||||
#define I2C_SADDR_ADDR(v) \
|
||||
(((v) << I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK)
|
||||
|
||||
/* I2C_SADDRMASK */
|
||||
#define I2C_SADDRMASK_MASK_SHIFT (0)
|
||||
@ -166,7 +172,7 @@
|
||||
#define I2C_IFS_TXC (1 << 3)
|
||||
#define I2C_IFS_ADDR (1 << 2)
|
||||
#define I2C_IFS_RSTART (1 << 1)
|
||||
#define I2C_IFS_START (1 << 0
|
||||
#define I2C_IFS_START (1 << 0)
|
||||
|
||||
/* I2C_IFC */
|
||||
#define I2C_IFC_SSTOP (1 << 16)
|
||||
@ -185,7 +191,7 @@
|
||||
#define I2C_IFC_TXC (1 << 3)
|
||||
#define I2C_IFC_ADDR (1 << 2)
|
||||
#define I2C_IFC_RSTART (1 << 1)
|
||||
#define I2C_IFC_START (1 << 0
|
||||
#define I2C_IFC_START (1 << 0)
|
||||
|
||||
/* I2C_IEN */
|
||||
#define I2C_IEN_SSTOP (1 << 16)
|
||||
@ -204,7 +210,7 @@
|
||||
#define I2C_IEN_TXC (1 << 3)
|
||||
#define I2C_IEN_ADDR (1 << 2)
|
||||
#define I2C_IEN_RSTART (1 << 1)
|
||||
#define I2C_IEN_START (1 << 0
|
||||
#define I2C_IEN_START (1 << 0)
|
||||
|
||||
/* I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_SHIFT (8)
|
||||
|
||||
@ -138,7 +138,7 @@
|
||||
#define PRS_CH_CTRL_SIGSEL_ADCSCAN PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0IRTX PRS_CH_CTRL_SIGSEL(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0RXDATA PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART1TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_USART2TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
@ -170,7 +170,7 @@
|
||||
#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART0TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART1TXC USART PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART1TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 PRS_CH_CTRL_SIGSEL(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 PRS_CH_CTRL_SIGSEL(1)
|
||||
@ -238,50 +238,88 @@
|
||||
#define PRS_CH_CTRL_SIGSEL_UART_TXC PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_UART_RXDATAV PRS_CH_CTRL_SIGSEL(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOL_PINx(x) PRS_CH_CTRL_SIGSEL(x)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(3)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(4)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(5)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(6)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7 PRS_CH_CTRL_SIGSEL_GPIOL_PINx(7)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(3)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(4)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(5)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(6)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOL_PINx(7)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOH_PINx(x) PRS_CH_CTRL_SIGSEL((x) - 8)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15 PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14)
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15 \
|
||||
PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15)
|
||||
#define PRS_CH_CTRL_SIGSEL_LETIMER_CHx(x) PRS_CH_CTRL_SIGSEL(x)
|
||||
#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0 PRS_CH_CTRL_SIGSEL_LETIMER_CHx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1 PRS_CH_CTRL_SIGSEL_LETIMER_CHx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0 \
|
||||
PRS_CH_CTRL_SIGSEL_LETIMER_CHx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1 \
|
||||
PRS_CH_CTRL_SIGSEL_LETIMER_CHx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_BURTC_OF PRS_CH_CTRL_SIGSEL(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_BURTC_COMP0 PRS_CH_CTRL_SIGSEL(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(x) PRS_CH_CTRL_SIGSEL(x)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(3)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(4)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(5)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(6)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7 PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(7)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x) PRS_CH_CTRL_SIGSEL((x) - 8)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15 PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(3)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(4)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(5)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(6)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(7)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x) \
|
||||
PRS_CH_CTRL_SIGSEL((x) - 8)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSED_DECx(x) PRS_CH_CTRL_SIGSEL(x)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0 PRS_CH_CTRL_SIGSEL_LESENSED_DECx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1 PRS_CH_CTRL_SIGSEL_LESENSED_DECx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2 PRS_CH_CTRL_SIGSEL_LESENSED_DECx(2)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSED_DECx(0)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSED_DECx(1)
|
||||
#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2 \
|
||||
PRS_CH_CTRL_SIGSEL_LESENSED_DECx(2)
|
||||
|
||||
/** @defgroup prs_ch PRS Channel Number
|
||||
@ingroup prs_defines
|
||||
|
||||
@ -248,7 +248,8 @@
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_RISING TIMER_CC_CTRL_ICEVCTRL(2)
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_FALLING TIMER_CC_CTRL_ICEVCTRL(3)
|
||||
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE \
|
||||
TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_EVERY_SECOND_EDGE \
|
||||
TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE
|
||||
|
||||
@ -322,8 +323,10 @@
|
||||
#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE TIMER_CC_CTRL_MODE(2)
|
||||
#define TIMER_CC_CTRL_MODE_PWM TIMER_CC_CTRL_MODE(3)
|
||||
|
||||
#define TIMER_CC_CTRL_MODE_INPUT_CAPTURE TIMER_CC_CTRL_MODE_INPUTCAPTURE
|
||||
#define TIMER_CC_CTRL_MODE_OUTPUT_CAPTURE TIMER_CC_CTRL_MODE_OUTPUTCAPTURE
|
||||
#define TIMER_CC_CTRL_MODE_INPUT_CAPTURE \
|
||||
TIMER_CC_CTRL_MODE_INPUTCAPTURE
|
||||
#define TIMER_CC_CTRL_MODE_OUTPUT_CAPTURE \
|
||||
TIMER_CC_CTRL_MODE_OUTPUTCAPTURE
|
||||
|
||||
/* TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSEN (1 << 24)
|
||||
|
||||
@ -91,11 +91,11 @@
|
||||
#define USART_CTRL_OVS_X6 USART_CTRL_OVS(2)
|
||||
#define USART_CTRL_OVS_X4 USART_CTRL_OVS(3)
|
||||
|
||||
#define USART_CTRL_MPAB (1 << )
|
||||
#define USART_CTRL_MPM (1 << )
|
||||
#define USART_CTRL_CCEN (1 << )
|
||||
#define USART_CTRL_LOOPBK (1 << )
|
||||
#define USART_CTRL_SYNC (1 << )
|
||||
#define USART_CTRL_MPAB (1 << 4)
|
||||
#define USART_CTRL_MPM (1 << 3)
|
||||
#define USART_CTRL_CCEN (1 << 2)
|
||||
#define USART_CTRL_LOOPBK (1 << 1)
|
||||
#define USART_CTRL_SYNC (1 << 0)
|
||||
|
||||
/* USART_FRAME */
|
||||
|
||||
@ -106,7 +106,8 @@
|
||||
#define USART_FRAME_STOPBITS_HALF USART_FRAME_STOPBITS(0)
|
||||
#define USART_FRAME_STOPBITS_ONE USART_FRAME_STOPBITS(1)
|
||||
#define USART_FRAME_STOPBITS_ONEANDAHALF USART_FRAME_STOPBITS(2)
|
||||
#define USART_FRAME_STOPBITS_ONE_AND_A_HALF USART_FRAME_STOPBITS_ONEANDAHALF
|
||||
#define USART_FRAME_STOPBITS_ONE_AND_A_HALF \
|
||||
USART_FRAME_STOPBITS_ONEANDAHALF
|
||||
#define USART_FRAME_STOPBITS_TWO USART_FRAME_STOPBITS(3)
|
||||
|
||||
#define USART_FRAME_PARITY_SHIFT (8)
|
||||
@ -185,7 +186,8 @@
|
||||
/* USART_CLKDIV */
|
||||
#define USART_CLKDIV_DIV_SHIFT (6)
|
||||
#define USART_CLKDIV_DIV_MASK (0x7FFF << USART_CLKDIV_DIV_SHIFT)
|
||||
#define USART_CLKDIV_DIV(v) (((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK)
|
||||
#define USART_CLKDIV_DIV(v) \
|
||||
(((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK)
|
||||
|
||||
/* USART_RXDATAX */
|
||||
#define USART_RXDATAX_FERR (1 << 15)
|
||||
@ -199,13 +201,15 @@
|
||||
#define USART_RXDOUBLEX_PERR1 (1 << 30)
|
||||
|
||||
#define USART_RXDOUBLEX_RXDATA1_SHIFT (16)
|
||||
#define USART_RXDOUBLEX_RXDATA1_MASK (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
|
||||
#define USART_RXDOUBLEX_RXDATA1_MASK \
|
||||
(0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
|
||||
|
||||
#define USART_RXDOUBLEX_FERR0 (1 << 15)
|
||||
#define USART_RXDOUBLEX_PERR0 (1 << 14)
|
||||
|
||||
#define USART_RXDOUBLEX_RXDATA0_SHIFT (0)
|
||||
#define USART_RXDOUBLEX_RXDATA0_MASK (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
|
||||
#define USART_RXDOUBLEX_RXDATA0_MASK \
|
||||
(0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT)
|
||||
|
||||
/* USART_RXDOUBLE */
|
||||
#define USART_RXDOUBLE_RXDATA1_SHIFT (8)
|
||||
@ -226,13 +230,15 @@
|
||||
#define USART_RXDOUBLEXP_PERR1 (1 << 30)
|
||||
|
||||
#define USART_RXDOUBLEXP_RXDATA1_SHIFT (16)
|
||||
#define USART_RXDOUBLEXP_RXDATA1_MASK (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
|
||||
#define USART_RXDOUBLEXP_RXDATA1_MASK \
|
||||
(0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
|
||||
|
||||
#define USART_RXDOUBLEXP_FERR0 (1 << 15)
|
||||
#define USART_RXDOUBLEXP_PERR0 (1 << 14)
|
||||
|
||||
#define USART_RXDOUBLEXP_RXDATA0_SHIFT (0)
|
||||
#define USART_RXDOUBLEXP_RXDATA0_MASK (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
|
||||
#define USART_RXDOUBLEXP_RXDATA0_MASK \
|
||||
(0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT)
|
||||
|
||||
/* USART_TXDATAX */
|
||||
#define USART_TXDATAX_RXENAT (1 << 15)
|
||||
@ -252,7 +258,8 @@
|
||||
#define USART_TXDOUBLEX_UBRXAT1 (1 << 27)
|
||||
|
||||
#define USART_TXDOUBLEX_TXDATA1_SHIFT (16)
|
||||
#define USART_TXDOUBLEX_TXDATA1_MASK (0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT)
|
||||
#define USART_TXDOUBLEX_TXDATA1_MASK \
|
||||
(0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT)
|
||||
|
||||
#define USART_TXDOUBLEX_RXENAT0 (1 << 15)
|
||||
#define USART_TXDOUBLEX_TXDISAT0 (1 << 14)
|
||||
@ -261,7 +268,8 @@
|
||||
#define USART_TXDOUBLEX_UBRXAT0 (1 << 11)
|
||||
|
||||
#define USART_TXDOUBLEX_TXDATA0_SHIFT (0)
|
||||
#define USART_TXDOUBLEX_TXDATA0_MASK (0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT)
|
||||
#define USART_TXDOUBLEX_TXDATA0_MASK \
|
||||
(0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT)
|
||||
|
||||
/* USART_TXDOUBLE */
|
||||
#define USART_TXDOUBLE_TXDATA1_SHIFT (8)
|
||||
|
||||
@ -55,7 +55,8 @@
|
||||
#define USB_GNPTXSTS MMIO32(USB_OTG_BASE + 0x02C)
|
||||
#define USB_GDFIFOCFG MMIO32(USB_OTG_BASE + 0x05C)
|
||||
#define USB_HPTXFSIZ MMIO32(USB_OTG_BASE + 0x100)
|
||||
#define USB_DIEPTXF(x) MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1)))
|
||||
#define USB_DIEPTXF(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1)))
|
||||
|
||||
/* Host-mode Control and Status Registers */
|
||||
#define USB_HCFG MMIO32(USB_OTG_BASE + 0x400)
|
||||
@ -65,11 +66,16 @@
|
||||
#define USB_HAINT MMIO32(USB_OTG_BASE + 0x414)
|
||||
#define USB_HAINTMSK MMIO32(USB_OTG_BASE + 0x418)
|
||||
#define USB_HPRT MMIO32(USB_OTG_BASE + 0x440)
|
||||
#define USB_HCx_CHAR(x) MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20))
|
||||
#define USB_HCx_INT(x) MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20))
|
||||
#define USB_HCx_INTMSK(x) MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20))
|
||||
#define USB_HCx_TSIZ(x) MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20))
|
||||
#define USB_HCx_DMAADDR(x) MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20))
|
||||
#define USB_HCx_CHAR(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20))
|
||||
#define USB_HCx_INT(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20))
|
||||
#define USB_HCx_INTMSK(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20))
|
||||
#define USB_HCx_TSIZ(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20))
|
||||
#define USB_HCx_DMAADDR(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20))
|
||||
|
||||
/* Device-mode Control and Status Registers */
|
||||
#define USB_DCFG MMIO32(USB_OTG_BASE + 0x800)
|
||||
@ -83,16 +89,22 @@
|
||||
#define USB_DVBUSPULSE MMIO32(USB_OTG_BASE + 0x82C)
|
||||
#define USB_DIEPEMPMSK MMIO32(USB_OTG_BASE + 0x834)
|
||||
|
||||
#define USB_DIEPx_CTL(x) MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20))
|
||||
#define USB_DIEPx_INT(x) MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20))
|
||||
#define USB_DIEPx_TSIZ(x) MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20))
|
||||
#define USB_DIEPx_CTL(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20))
|
||||
#define USB_DIEPx_INT(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20))
|
||||
#define USB_DIEPx_TSIZ(x) \
|
||||
MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20))
|
||||
#define USB_DIEP0CTL USB_DIEPx_CTL(0)
|
||||
#define USB_DIEP0TSIZ USB_DIEPx_TSIZ(0)
|
||||
#define USB_DIEP0INT USB_DIEPx_INT(0)
|
||||
|
||||
#define USB_DOEPx_CTL(x) MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20))
|
||||
#define USB_DOEPx_INT(x) MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20))
|
||||
#define USB_DOEPx_TSIZ(x) MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20))
|
||||
#define USB_DOEPx_CTL(x) \
|
||||
MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20))
|
||||
#define USB_DOEPx_INT(x) \
|
||||
MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20))
|
||||
#define USB_DOEPx_TSIZ(x) \
|
||||
MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20))
|
||||
#define USB_DOEP0CTL USB_DOEPx_CTL(0)
|
||||
#define USB_DOEP0TSIZ USB_DOEPx_TSIZ(0)
|
||||
#define USB_DOEP0INT USB_DOEPx_INT(0)
|
||||
@ -101,7 +113,8 @@
|
||||
#define USB_PCGCCTL MMIO32(USB_OTG_BASE + 0xE00)
|
||||
|
||||
/* Data FIFO */
|
||||
#define USB_FIFOxD(x) (&MMIO32(USB_OTG_BASE + (((x) + 1) << 12)))
|
||||
#define USB_FIFOxD(x) \
|
||||
(&MMIO32(USB_OTG_BASE + (((x) + 1) << 12)))
|
||||
|
||||
/* Global CSRs */
|
||||
/* USB control registers (OTG_HS_GOTGCTL) */
|
||||
|
||||
@ -87,7 +87,8 @@ void adc_disable_tailgating(uint32_t adc)
|
||||
*/
|
||||
void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode)
|
||||
{
|
||||
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK) | warmupmode;
|
||||
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK)
|
||||
| warmupmode;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@ -56,7 +56,8 @@ bool cmu_get_lock_flag(void)
|
||||
*
|
||||
* @param[in] periph enum cmu_periph_clken Peripheral Name
|
||||
*
|
||||
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for example)
|
||||
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
|
||||
* example)
|
||||
*/
|
||||
|
||||
void cmu_periph_clock_enable(enum cmu_periph_clken clken)
|
||||
@ -70,7 +71,8 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken)
|
||||
*
|
||||
* @param[in] periph enum cmu_periph_clken Peripheral Name
|
||||
*
|
||||
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for example)
|
||||
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
|
||||
* example)
|
||||
*/
|
||||
|
||||
void cmu_periph_clock_disable(enum cmu_periph_clken clken)
|
||||
@ -245,11 +247,12 @@ enum cmu_osc cmu_get_hfclk_source(void)
|
||||
void cmu_clock_setup_in_hfxo_out_48mhz(void)
|
||||
{
|
||||
/* configure HFXO and prescaler */
|
||||
CMU_HFCORECLKDIV = CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV |
|
||||
CMU_HFCORECLKDIV_HFCORECLKLEDIV;
|
||||
CMU_CTRL = (CMU_CTRL &
|
||||
~(CMU_CTRL_HFCLKDIV_MASK | CMU_CTRL_HFXOBUFCUR_MASK)) |
|
||||
(CMU_CTRL_HFCLKDIV_NODIV | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ);
|
||||
CMU_HFCORECLKDIV = CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV
|
||||
| CMU_HFCORECLKDIV_HFCORECLKLEDIV;
|
||||
CMU_CTRL = (CMU_CTRL
|
||||
& ~(CMU_CTRL_HFCLKDIV_MASK | CMU_CTRL_HFXOBUFCUR_MASK))
|
||||
| (CMU_CTRL_HFCLKDIV_NODIV
|
||||
| CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ);
|
||||
|
||||
/* enable HFXO */
|
||||
cmu_osc_on(HFXO);
|
||||
@ -258,8 +261,8 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void)
|
||||
cmu_wait_for_osc_ready(HFXO);
|
||||
|
||||
/* set flash wait state */
|
||||
MSC_READCTRL = (MSC_READCTRL & ~MSC_READCTRL_MODE_MASK) |
|
||||
MSC_READCTRL_MODE_WS2;
|
||||
MSC_READCTRL = (MSC_READCTRL & ~MSC_READCTRL_MODE_MASK)
|
||||
| MSC_READCTRL_MODE_WS2;
|
||||
|
||||
/* switch to HFXO */
|
||||
cmu_set_hfclk_source(HFXO);
|
||||
|
||||
@ -98,7 +98,8 @@ void dac_disable_sine(uint32_t dac)
|
||||
* @param[in] dac_ch DAC Channel (use DAC_CHx)
|
||||
* @param[in] prs_ch PRS Channel (use PRS_CHx)
|
||||
*/
|
||||
void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, enum prs_ch prs_chan)
|
||||
void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan,
|
||||
enum prs_ch prs_chan)
|
||||
{
|
||||
uint32_t ch_ctrl = DAC_CHx_CTRL(dac, dac_chan);
|
||||
ch_ctrl &= DAC_CH_CTRL_PRSSEL_MASK;
|
||||
|
||||
@ -307,7 +307,8 @@ void dma_disable_done_interrupt(enum dma_ch ch)
|
||||
*/
|
||||
void dma_set_source(enum dma_ch ch, uint32_t source)
|
||||
{
|
||||
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SOURCESEL_MASK) | source;
|
||||
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SOURCESEL_MASK)
|
||||
| source;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -317,7 +318,8 @@ void dma_set_source(enum dma_ch ch, uint32_t source)
|
||||
*/
|
||||
void dma_set_signal(enum dma_ch ch, uint32_t signal)
|
||||
{
|
||||
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SIGSEL_MASK) | signal;
|
||||
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SIGSEL_MASK)
|
||||
| signal;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -354,7 +356,8 @@ void dma_set_loop_count(enum dma_ch ch, uint16_t count)
|
||||
return;
|
||||
}
|
||||
|
||||
DMA_LOOPx(ch) = (DMA_LOOPx(ch) & ~DMA_LOOP_WIDTH_MASK) | DMA_LOOP_WIDTH(count - 1);
|
||||
DMA_LOOPx(ch) = (DMA_LOOPx(ch) & ~DMA_LOOP_WIDTH_MASK)
|
||||
| DMA_LOOP_WIDTH(count - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -385,11 +388,13 @@ void dma_disable_loop(enum dma_ch ch)
|
||||
|
||||
/**
|
||||
* Set desination size
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] size Size (use DMA_MEM_*)
|
||||
*/
|
||||
void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size)
|
||||
void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem size)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
cfg &= ~DMA_DESC_CH_CFG_DEST_SIZE_MASK;
|
||||
@ -399,11 +404,13 @@ void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem siz
|
||||
|
||||
/**
|
||||
* Set destination increment
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] inc Increment (use DMA_MEM_*)
|
||||
*/
|
||||
void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
|
||||
void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem inc)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
cfg &= ~DMA_DESC_CH_CFG_DEST_INC_MASK;
|
||||
@ -413,11 +420,13 @@ void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
|
||||
|
||||
/**
|
||||
* Set source size
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] size Size (use DMA_MEM_*)
|
||||
*/
|
||||
void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size)
|
||||
void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_mem size)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
cfg &= ~DMA_DESC_CH_CFG_SRC_SIZE_MASK;
|
||||
@ -427,7 +436,8 @@ void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size
|
||||
|
||||
/**
|
||||
* Set source increment
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] inc Increment (use DMA_MEM_*)
|
||||
*/
|
||||
@ -442,11 +452,13 @@ void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
|
||||
|
||||
/**
|
||||
* Set R Power
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] r_power R Power (Use DMA_R_POWER_*)
|
||||
*/
|
||||
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, enum dma_r_power r_power)
|
||||
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch,
|
||||
enum dma_r_power r_power)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
cfg &= ~DMA_DESC_CH_CFG_R_POWER_MASK;
|
||||
@ -456,7 +468,8 @@ void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, enum dma_r_power r
|
||||
|
||||
/**
|
||||
* Enable next useburst
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
*/
|
||||
void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch)
|
||||
@ -466,7 +479,8 @@ void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch)
|
||||
|
||||
/**
|
||||
* Disable next useburst
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
*/
|
||||
void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch)
|
||||
@ -476,7 +490,8 @@ void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch)
|
||||
|
||||
/**
|
||||
* Set number (count) of transfer to be performed
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] count Count
|
||||
*/
|
||||
@ -490,18 +505,21 @@ void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count)
|
||||
|
||||
/**
|
||||
* Store user data field in channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] user_data User data
|
||||
*/
|
||||
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, uint32_t user_data)
|
||||
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t user_data)
|
||||
{
|
||||
DMA_DESC_CHx_USER_DATA(desc_base, ch) = user_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* Extract user data field from channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @return user data
|
||||
*/
|
||||
@ -522,7 +540,8 @@ uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch)
|
||||
* @return the calculate end address
|
||||
* @note can be used to calculate {source, destination} end address
|
||||
*/
|
||||
inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, uint16_t n_minus_1)
|
||||
inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc,
|
||||
uint16_t n_minus_1)
|
||||
{
|
||||
switch (inc) {
|
||||
case DMA_MEM_BYTE:
|
||||
@ -540,49 +559,56 @@ inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, uint16_t n_
|
||||
|
||||
/**
|
||||
* Assign Source address to DMA Channel
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] src_start Source data start address
|
||||
* @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc() set value
|
||||
* to calculate the src data end address from @a src_start
|
||||
* @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc()
|
||||
* set value to calculate the src data end address from @a src_start
|
||||
* @note dma_desc_set_count() should be called first.
|
||||
* @note dma_desc_set_src_inc() should be called first.
|
||||
*/
|
||||
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, uint32_t src_start)
|
||||
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t src_start)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
uint8_t inc = (cfg & DMA_DESC_CH_CFG_SRC_INC_MASK) >>
|
||||
DMA_DESC_CH_CFG_SRC_INC_SHIFT;
|
||||
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK) >>
|
||||
DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
||||
uint8_t inc = (cfg & DMA_DESC_CH_CFG_SRC_INC_MASK)
|
||||
>> DMA_DESC_CH_CFG_SRC_INC_SHIFT;
|
||||
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
|
||||
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
||||
uint32_t src_end = dma_calc_end_from_start(src_start, inc, n_minus_1);
|
||||
DMA_DESC_CHx_SRC_DATA_END_PTR(desc_base, ch) = src_end;
|
||||
}
|
||||
|
||||
/**
|
||||
* Assign Destination address to DMA Channel
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] dest_start Destination data start address
|
||||
* @param[in] this function use dma_desc_set_count() and dma_desc_set_dest_inc() set value
|
||||
* to calculate the dest data end address from @a dest_start
|
||||
* @param[in] this function use dma_desc_set_count() and
|
||||
* dma_desc_set_dest_inc() set value to calculate the dest data end
|
||||
* address from @a dest_start
|
||||
* @note dma_desc_set_count() should be called first.
|
||||
* @note dma_desc_set_dest_inc() should be called first.
|
||||
*/
|
||||
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, uint32_t dest_start)
|
||||
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch,
|
||||
uint32_t dest_start)
|
||||
{
|
||||
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
|
||||
uint8_t inc = (cfg & DMA_DESC_CH_CFG_DEST_INC_MASK) >>
|
||||
DMA_DESC_CH_CFG_DEST_INC_SHIFT;
|
||||
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK) >>
|
||||
DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
||||
uint32_t dest_end = dma_calc_end_from_start(dest_start, inc, n_minus_1);
|
||||
uint8_t inc = (cfg & DMA_DESC_CH_CFG_DEST_INC_MASK)
|
||||
>> DMA_DESC_CH_CFG_DEST_INC_SHIFT;
|
||||
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
|
||||
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
|
||||
uint32_t dest_end = dma_calc_end_from_start(dest_start, inc,
|
||||
n_minus_1);
|
||||
DMA_DESC_CHx_DEST_DATA_END_PTR(desc_base, ch) = dest_end;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the channel mode ("Cycle control")
|
||||
* @param[in] desc_base start of memory location that contain channel descriptor
|
||||
* @param[in] desc_base start of memory location that contain channel
|
||||
* descriptor
|
||||
* @param[in] ch Channel (use DMA_CHx)
|
||||
* @param[in] mode Mode (use DMA_MODE_*)
|
||||
*/
|
||||
|
||||
@ -48,7 +48,8 @@ void gpio_disable_lock(void)
|
||||
*/
|
||||
bool gpio_get_lock_flag(void)
|
||||
{
|
||||
return (GPIO_LOCK & GPIO_LOCK_LOCKKEY_MASK) == GPIO_LOCK_LOCKKEY_LOCKED;
|
||||
return (GPIO_LOCK & GPIO_LOCK_LOCKKEY_MASK)
|
||||
== GPIO_LOCK_LOCKKEY_LOCKED;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -56,7 +57,8 @@ bool gpio_get_lock_flag(void)
|
||||
* @param[in] gpio_port GPIO Port (use GPIO* ex. GPIOA, GPIOB, ....)
|
||||
* @param[in] drive_stength Driver Stength (use GPIO_STENGTH_*)
|
||||
*/
|
||||
void gpio_set_drive_strength(uint32_t gpio_port, enum gpio_drive_strength drive_stength)
|
||||
void gpio_set_drive_strength(uint32_t gpio_port,
|
||||
enum gpio_drive_strength drive_stength)
|
||||
{
|
||||
GPIO_P_CTRL(gpio_port) = GPIO_P_CTRL_DRIVEMODE(drive_stength);
|
||||
}
|
||||
@ -122,7 +124,7 @@ void gpio_clear(uint32_t gpio_port, uint16_t gpios)
|
||||
*/
|
||||
uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios)
|
||||
{
|
||||
return (GPIO_P_DIN(gpio_port) & gpios);
|
||||
return GPIO_P_DIN(gpio_port) & gpios;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -159,9 +161,9 @@ void gpio_port_write(uint32_t gpio_port, uint16_t data)
|
||||
/**
|
||||
* @brief Lock the Configuration of a Group of Pins
|
||||
*
|
||||
* The configuration of one or more pins of the given GPIO port is locked. There
|
||||
* is no mechanism to unlock these via software. Unlocking occurs at the next
|
||||
* reset.
|
||||
* The configuration of one or more pins of the given GPIO port is locked.
|
||||
* There is no mechanism to unlock these via software. Unlocking occurs at the
|
||||
* next reset.
|
||||
*
|
||||
* @param[in] gpio_port GPIO Port (use GPIO* ex. GPIOA, GPIOB, ....)
|
||||
* @param[in] gpios (pins mask (use GPIO* ex . GPIO0, GPIO1 .... GPIO_ALL,
|
||||
|
||||
@ -123,7 +123,8 @@ void prs_set_edge(enum prs_ch ch, uint32_t edge)
|
||||
*/
|
||||
void prs_set_source(enum prs_ch ch, uint32_t source)
|
||||
{
|
||||
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SOURCESEL_MASK) | source;
|
||||
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SOURCESEL_MASK)
|
||||
| source;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -134,5 +135,6 @@ void prs_set_source(enum prs_ch ch, uint32_t source)
|
||||
*/
|
||||
void prs_set_signal(enum prs_ch ch, uint32_t signal)
|
||||
{
|
||||
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK) | signal;
|
||||
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK)
|
||||
| signal;
|
||||
}
|
||||
|
||||
@ -46,7 +46,8 @@ void timer_stop(uint32_t timer)
|
||||
*/
|
||||
void timer_set_clock_prescaler(uint32_t timer, uint32_t presc)
|
||||
{
|
||||
TIMER_CTRL(timer) = (TIMER_CTRL(timer) & ~TIMER_CTRL_PRESC_MASK) | presc;
|
||||
TIMER_CTRL(timer) = (TIMER_CTRL(timer) & ~TIMER_CTRL_PRESC_MASK)
|
||||
| presc;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user