jackcartersmith/blackmagic
1
0
Fork 0
Code Issues Pull Requests Releases Activity

Fix more STM32 whitespace issues

Browse Source
This commit is contained in:
Stephen Caudle 2011-10-31 11:11:03 -04:00
parent 6da485f06d
commit 1fea1df39a
28 changed files with 1343 additions and 1356 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

376
include/libopencm3/stm32/can.h
View File

@ -26,107 +26,107 @@
/* --- Convenience macros -------------------------------------------------- */
/* CAN register base adresses (for convenience) */
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
/* --- CAN registers ------------------------------------------------------- */
/* CAN master control register (CAN_MCR) */
#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
/* CAN master status register (CAN_MSR) */
#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
/* CAN transmit status register (CAN_TSR) */
#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
/* CAN receive FIFO 0 register (CAN_RF0R) */
#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
/* CAN receive FIFO 1 register (CAN_RF1R) */
#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
/* CAN interrupt enable register (CAN_IER) */
#define CAN_IER(can_base) MMIO32(can_base + 0x014)
#define CAN_IER(can_base) MMIO32(can_base + 0x014)
/* CAN error status register (CAN_ESR) */
#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
/* CAN bit timing register (CAN_BTR) */
#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
/* Registers in the offset range 0x020 to 0x17F are reserved. */
/* --- CAN mailbox registers ----------------------------------------------- */
/* CAN mailbox / FIFO register offsets */
#define CAN_MBOX0 0x180
#define CAN_MBOX1 0x190
#define CAN_MBOX2 0x1A0
#define CAN_FIFO0 0x1B0
#define CAN_FIFO1 0x1C0
#define CAN_MBOX0 0x180
#define CAN_MBOX1 0x190
#define CAN_MBOX2 0x1A0
#define CAN_FIFO0 0x1B0
#define CAN_FIFO1 0x1C0
/* CAN TX mailbox identifier register (CAN_TIxR) */
#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
/* CAN mailbox data low register (CAN_TDLxR) */
#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
/* CAN mailbox data high register (CAN_TDHxR) */
#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
/* CAN RX FIFO identifier register (CAN_RIxR) */
#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
/* --- CAN filter registers ------------------------------------------------ */
/* CAN filter master register (CAN_FMR) */
#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
/* CAN filter mode register (CAN_FM1R) */
#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
/* Register offset 0x208 is reserved. */
/* CAN filter scale register (CAN_FS1R) */
#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
/* Register offset 0x210 is reserved. */
/* CAN filter FIFO assignement register (CAN_FFA1R) */
#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
/* Register offset 0x218 is reserved. */
/* CAN filter activation register (CAN_FA1R) */
#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
/* Register offset 0x220 is reserved. */
@ -137,359 +137,359 @@
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */
/* 31:17 Reserved, forced by hardware to 0 */
/* DBF: Debug freeze */
#define CAN_MCR_DBF (1 << 16)
#define CAN_MCR_DBF (1 << 16)
/* RESET: bxCAN software master reset */
#define CAN_MCR_RESET (1 << 15)
#define CAN_MCR_RESET (1 << 15)
/* 14:8 Reserved, forced by hardware to 0 */
/* TTCM: Time triggered communication mode */
#define CAN_MCR_TTCM (1 << 7)
#define CAN_MCR_TTCM (1 << 7)
/* ABOM: Automatic bus-off management */
#define CAN_MCR_ABOM (1 << 6)
#define CAN_MCR_ABOM (1 << 6)
/* AWUM: Automatic wakeup mode */
#define CAN_MCR_AWUM (1 << 5)
#define CAN_MCR_AWUM (1 << 5)
/* NART: No automatic retransmission */
#define CAN_MCR_NART (1 << 4)
#define CAN_MCR_NART (1 << 4)
/* RFLM: Receive FIFO locked mode */
#define CAN_MCR_RFLM (1 << 3)
#define CAN_MCR_RFLM (1 << 3)
/* TXFP: Transmit FIFO priority */
#define CAN_MCR_TXFP (1 << 2)
#define CAN_MCR_TXFP (1 << 2)
/* SLEEP: Sleep mode request */
#define CAN_MCR_SLEEP (1 << 1)
#define CAN_MCR_SLEEP (1 << 1)
/* INRQ: Initialization request */
#define CAN_MCR_INRQ (1 << 0)
#define CAN_MCR_INRQ (1 << 0)
/* --- CAN_MSR values ------------------------------------------------------ */
/* 31:12 Reserved, forced by hardware to 0 */
/* RX: CAN Rx signal */
#define CAN_MSR_RX (1 << 11)
#define CAN_MSR_RX (1 << 11)
/* SAMP: Last sample point */
#define CAN_MSR_SAMP (1 << 10)
#define CAN_MSR_SAMP (1 << 10)
/* RXM: Receive mode */
#define CAN_MSR_RXM (1 << 9)
#define CAN_MSR_RXM (1 << 9)
/* TXM: Transmit mode */
#define CAN_MSR_TXM (1 << 8)
#define CAN_MSR_TXM (1 << 8)
/* 7:5 Reserved, forced by hardware to 0 */
/* SLAKI: Sleep acknowledge interrupt */
#define CAN_MSR_SLAKI (1 << 4)
#define CAN_MSR_SLAKI (1 << 4)
/* WKUI: Wakeup interrupt */
#define CAN_MSR_WKUI (1 << 3)
#define CAN_MSR_WKUI (1 << 3)
/* ERRI: Error interrupt */
#define CAN_MSR_ERRI (1 << 2)
#define CAN_MSR_ERRI (1 << 2)
/* SLAK: Sleep acknowledge */
#define CAN_MSR_SLAK (1 << 1)
#define CAN_MSR_SLAK (1 << 1)
/* INAK: Initialization acknowledge */
#define CAN_MSR_INAK (1 << 0)
#define CAN_MSR_INAK (1 << 0)
/* --- CAN_TSR values ------------------------------------------------------ */
/* LOW2: Lowest priority flag for mailbox 2 */
#define CAN_TSR_LOW2 (1 << 31)
#define CAN_TSR_LOW2 (1 << 31)
/* LOW1: Lowest priority flag for mailbox 1 */
#define CAN_TSR_LOW1 (1 << 30)
#define CAN_TSR_LOW1 (1 << 30)
/* LOW0: Lowest priority flag for mailbox 0 */
#define CAN_TSR_LOW0 (1 << 29)
#define CAN_TSR_LOW0 (1 << 29)
/* TME2: Transmit mailbox 2 empty */
#define CAN_TSR_TME2 (1 << 28)
#define CAN_TSR_TME2 (1 << 28)
/* TME1: Transmit mailbox 1 empty */
#define CAN_TSR_TME1 (1 << 27)
#define CAN_TSR_TME1 (1 << 27)
/* TME0: Transmit mailbox 0 empty */
#define CAN_TSR_TME0 (1 << 26)
#define CAN_TSR_TME0 (1 << 26)
/* CODE[1:0]: Mailbox code */
#define CAN_TSR_CODE_MASK (0x3 << 24)
#define CAN_TSR_CODE_MASK (0x3 << 24)
/* ABRQ2: Abort request for mailbox 2 */
#define CAN_TSR_TABRQ2 (1 << 23)
#define CAN_TSR_TABRQ2 (1 << 23)
/* 22:20 Reserved, forced by hardware to 0 */
/* TERR2: Transmission error for mailbox 2 */
#define CAN_TSR_TERR2 (1 << 19)
#define CAN_TSR_TERR2 (1 << 19)
/* ALST2: Arbitration lost for mailbox 2 */
#define CAN_TSR_ALST2 (1 << 18)
#define CAN_TSR_ALST2 (1 << 18)
/* TXOK2: Transmission OK for mailbox 2 */
#define CAN_TSR_TXOK2 (1 << 17)
#define CAN_TSR_TXOK2 (1 << 17)
/* RQCP2: Request completed mailbox 2 */
#define CAN_TSR_RQCP2 (1 << 16)
#define CAN_TSR_RQCP2 (1 << 16)
/* ABRQ1: Abort request for mailbox 1 */
#define CAN_TSR_ABRQ1 (1 << 15)
#define CAN_TSR_ABRQ1 (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* TERR1: Transmission error for mailbox 1 */
#define CAN_TSR_TERR1 (1 << 11)
#define CAN_TSR_TERR1 (1 << 11)
/* ALST1: Arbitration lost for mailbox 1 */
#define CAN_TSR_ALST1 (1 << 10)
#define CAN_TSR_ALST1 (1 << 10)
/* TXOK1: Transmission OK for mailbox 1 */
#define CAN_TSR_TXOK1 (1 << 9)
#define CAN_TSR_TXOK1 (1 << 9)
/* RQCP1: Request completed mailbox 1 */
#define CAN_TSR_RQCP1 (1 << 8)
#define CAN_TSR_RQCP1 (1 << 8)
/* ABRQ0: Abort request for mailbox 0 */
#define CAN_TSR_ABRQ0 (1 << 7)
#define CAN_TSR_ABRQ0 (1 << 7)
/* 6:4 Reserved, forced by hardware to 0 */
/* TERR0: Transmission error for mailbox 0 */
#define CAN_TSR_TERR0 (1 << 3)
#define CAN_TSR_TERR0 (1 << 3)
/* ALST0: Arbitration lost for mailbox 0 */
#define CAN_TSR_ALST0 (1 << 2)
#define CAN_TSR_ALST0 (1 << 2)
/* TXOK0: Transmission OK for mailbox 0 */
#define CAN_TSR_TXOK0 (1 << 1)
#define CAN_TSR_TXOK0 (1 << 1)
/* RQCP0: Request completed mailbox 0 */
#define CAN_TSR_RQCP0 (1 << 0)
#define CAN_TSR_RQCP0 (1 << 0)
/* --- CAN_RF0R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM0: Release FIFO 0 output mailbox */
#define CAN_RF0R_RFOM0 (1 << 5)
#define CAN_RF0R_RFOM0 (1 << 5)
/* FOVR0: FIFO 0 overrun */
#define CAN_RF0R_FAVR0 (1 << 4)
#define CAN_RF0R_FAVR0 (1 << 4)
/* FULL0: FIFO 0 full */
#define CAN_RF0R_FULL0 (1 << 3)
#define CAN_RF0R_FULL0 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP0[1:0]: FIFO 0 message pending */
#define CAN_RF0R_FMP0_MASK (0x3 << 0)
#define CAN_RF0R_FMP0_MASK (0x3 << 0)
/* --- CAN_RF1R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM1: Release FIFO 1 output mailbox */
#define CAN_RF1R_RFOM1 (1 << 5)
#define CAN_RF1R_RFOM1 (1 << 5)
/* FOVR1: FIFO 1 overrun */
#define CAN_RF1R_FAVR1 (1 << 4)
#define CAN_RF1R_FAVR1 (1 << 4)
/* FULL1: FIFO 1 full */
#define CAN_RF1R_FULL1 (1 << 3)
#define CAN_RF1R_FULL1 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP1[1:0]: FIFO 1 message pending */
#define CAN_RF1R_FMP1_MASK (0x3 << 0)
#define CAN_RF1R_FMP1_MASK (0x3 << 0)
/* --- CAN_IER values ------------------------------------------------------ */
/* 32:18 Reserved, forced by hardware to 0 */
/* SLKIE: Sleep interrupt enable */
#define CAN_IER_SLKIE (1 << 17)
#define CAN_IER_SLKIE (1 << 17)
/* WKUIE: Wakeup interrupt enable */
#define CAN_IER_WKUIE (1 << 16)
#define CAN_IER_WKUIE (1 << 16)
/* ERRIE: Error interrupt enable */
#define CAN_IER_ERRIE (1 << 15)
#define CAN_IER_ERRIE (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* LECIE: Last error code interrupt enable */
#define CAN_IER_LECIE (1 << 11)
#define CAN_IER_LECIE (1 << 11)
/* BOFIE: Bus-off interrupt enable */
#define CAN_IER_BOFIE (1 << 10)
#define CAN_IER_BOFIE (1 << 10)
/* EPVIE: Error passive interrupt enable */
#define CAN_IER_EPVIE (1 << 9)
#define CAN_IER_EPVIE (1 << 9)
/* EWGIE: Error warning interrupt enable */
#define CAN_IER_EWGIE (1 << 8)
#define CAN_IER_EWGIE (1 << 8)
/* 7 Reserved, forced by hardware to 0 */
/* FOVIE1: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE1 (1 << 6)
#define CAN_IER_FOVIE1 (1 << 6)
/* FFIE1: FIFO full interrupt enable */
#define CAN_IER_FFIE1 (1 << 5)
#define CAN_IER_FFIE1 (1 << 5)
/* FMPIE1: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE1 (1 << 4)
#define CAN_IER_FMPIE1 (1 << 4)
/* FOVIE0: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE0 (1 << 3)
#define CAN_IER_FOVIE0 (1 << 3)
/* FFIE0: FIFO full interrupt enable */
#define CAN_IER_FFIE0 (1 << 2)
#define CAN_IER_FFIE0 (1 << 2)
/* FMPIE0: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE0 (1 << 1)
#define CAN_IER_FMPIE0 (1 << 1)
/* TMEIE: Transmit mailbox empty interrupt enable */
#define CAN_IER_TMEIE (1 << 0)
#define CAN_IER_TMEIE (1 << 0)
/* --- CAN_ESR values ------------------------------------------------------ */
/* REC[7:0]: Receive error counter */
#define CAN_ESR_REC_MASK (0xF << 24)
#define CAN_ESR_REC_MASK (0xF << 24)
/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
#define CAN_ESR_TEC_MASK (0xF << 16)
#define CAN_ESR_TEC_MASK (0xF << 16)
/* 15:7 Reserved, forced by hardware to 0 */
/* LEC[2:0]: Last error code */
#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
#define CAN_ESR_LEC_MASK (0x7 << 4)
#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
#define CAN_ESR_LEC_MASK (0x7 << 4)
/* 3 Reserved, forced by hardware to 0 */
/* BOFF: Bus-off flag */
#define CAN_ESR_BOFF (1 << 2)
#define CAN_ESR_BOFF (1 << 2)
/* EPVF: Error passive flag */
#define CAN_ESR_EPVF (1 << 1)
#define CAN_ESR_EPVF (1 << 1)
/* EWGF: Error warning flag */
#define CAN_ESR_EWGF (1 << 0)
#define CAN_ESR_EWGF (1 << 0)
/* --- CAN_BTR values ------------------------------------------------------ */
/* SILM: Silent mode (debug) */
#define CAN_BTR_SILM (1 << 31)
#define CAN_BTR_SILM (1 << 31)
/* LBKM: Loop back mode (debug) */
#define CAN_BTR_LBKM (1 << 30)
#define CAN_BTR_LBKM (1 << 30)
/* 29:26 Reserved, forced by hardware to 0 */
/* SJW[1:0]: Resynchronization jump width */
#define CAN_BTR_SJW_1TQ (0x0 << 24)
#define CAN_BTR_SJW_2TQ (0x1 << 24)
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
#define CAN_BTR_SJW_1TQ (0x0 << 24)
#define CAN_BTR_SJW_2TQ (0x1 << 24)
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
/* 23 Reserved, forced by hardware to 0 */
/* TS2[2:0]: Time segment 2 */
#define CAN_BTR_TS2_1TQ (0x0 << 20)
#define CAN_BTR_TS2_2TQ (0x1 << 20)
#define CAN_BTR_TS2_3TQ (0x2 << 20)
#define CAN_BTR_TS2_4TQ (0x3 << 20)
#define CAN_BTR_TS2_5TQ (0x4 << 20)
#define CAN_BTR_TS2_6TQ (0x5 << 20)
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
#define CAN_BTR_TS2_1TQ (0x0 << 20)
#define CAN_BTR_TS2_2TQ (0x1 << 20)
#define CAN_BTR_TS2_3TQ (0x2 << 20)
#define CAN_BTR_TS2_4TQ (0x3 << 20)
#define CAN_BTR_TS2_5TQ (0x4 << 20)
#define CAN_BTR_TS2_6TQ (0x5 << 20)
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
/* TS1[3:0]: Time segment 1 */
#define CAN_BTR_TS1_1TQ (0x0 << 16)
#define CAN_BTR_TS1_2TQ (0x1 << 16)
#define CAN_BTR_TS1_3TQ (0x2 << 16)
#define CAN_BTR_TS1_4TQ (0x3 << 16)
#define CAN_BTR_TS1_5TQ (0x4 << 16)
#define CAN_BTR_TS1_6TQ (0x5 << 16)
#define CAN_BTR_TS1_7TQ (0x6 << 16)
#define CAN_BTR_TS1_8TQ (0x7 << 16)
#define CAN_BTR_TS1_9TQ (0x8 << 16)
#define CAN_BTR_TS1_10TQ (0x9 << 16)
#define CAN_BTR_TS1_11TQ (0xA << 16)
#define CAN_BTR_TS1_12TQ (0xB << 16)
#define CAN_BTR_TS1_13TQ (0xC << 16)
#define CAN_BTR_TS1_14TQ (0xD << 16)
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
#define CAN_BTR_TS1_1TQ (0x0 << 16)
#define CAN_BTR_TS1_2TQ (0x1 << 16)
#define CAN_BTR_TS1_3TQ (0x2 << 16)
#define CAN_BTR_TS1_4TQ (0x3 << 16)
#define CAN_BTR_TS1_5TQ (0x4 << 16)
#define CAN_BTR_TS1_6TQ (0x5 << 16)
#define CAN_BTR_TS1_7TQ (0x6 << 16)
#define CAN_BTR_TS1_8TQ (0x7 << 16)
#define CAN_BTR_TS1_9TQ (0x8 << 16)
#define CAN_BTR_TS1_10TQ (0x9 << 16)
#define CAN_BTR_TS1_11TQ (0xA << 16)
#define CAN_BTR_TS1_12TQ (0xB << 16)
#define CAN_BTR_TS1_13TQ (0xC << 16)
#define CAN_BTR_TS1_14TQ (0xD << 16)
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
/* 15:10 Reserved, forced by hardware to 0 */
/* BRP[9:0]: Baud rate prescaler */
#define CAN_BTR_BRP_MASK (0x1FF << 0)
#define CAN_BTR_BRP_MASK (0x1FF << 0)
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_TIxR_STID_MASK (0x3FF << 21)
#define CAN_TIxR_STID_SHIFT 21
#define CAN_TIxR_STID_MASK (0x3FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_TIxR_EXID_SHIFT 3
#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_TIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_TIxR_IDE (1 << 2)
#define CAN_TIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_TIxR_RTR (1 << 1)
#define CAN_TIxR_RTR (1 << 1)
/* TXRQ: Transmit mailbox request */
#define CAN_TIxR_TXRQ (1 << 0)
#define CAN_TIxR_TXRQ (1 << 0)
/* --- CAN_TDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_TDTxR_TIME_SHIFT 15
#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_TDTxR_TIME_SHIFT 15
/* 15:6 Reserved, forced by hardware to 0 */
/* TGT: Transmit global time */
#define CAN_TDTxR_TGT (1 << 5)
#define CAN_TDTxR_TGT (1 << 5)
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_TDTxR_DLC_MASK (0xF << 0)
#define CAN_TDTxR_DLC_SHIFT 0
#define CAN_TDTxR_DLC_MASK (0xF << 0)
#define CAN_TDTxR_DLC_SHIFT 0
/* --- CAN_TDLxR values ----------------------------------------------------- */
@ -508,36 +508,36 @@
/* --- CAN_RIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_RIxR_STID_MASK (0x3FF << 21)
#define CAN_RIxR_STID_SHIFT 21
#define CAN_RIxR_STID_MASK (0x3FF << 21)
#define CAN_RIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_RIxR_EXID_SHIFT 3
#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_RIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_RIxR_IDE (1 << 2)
#define CAN_RIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_RIxR_RTR (1 << 1)
#define CAN_RIxR_RTR (1 << 1)
/* 0 Reserved */
/* --- CAN_RDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_RDTxR_TIME_SHIFT 15
#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_RDTxR_TIME_SHIFT 15
/* FMI[7:0]: Filter match index */
#define CAN_RDTxR_FMI_MASK (0xFF << 8)
#define CAN_RDTxR_FMI_SHIFT 8
#define CAN_RDTxR_FMI_MASK (0xFF << 8)
#define CAN_RDTxR_FMI_SHIFT 8
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_RDTxR_DLC_MASK (0xF << 0)
#define CAN_RDTxR_DLC_SHIFT 0
#define CAN_RDTxR_DLC_MASK (0xF << 0)
#define CAN_RDTxR_DLC_SHIFT 0
/* --- CAN_RDLxR values ----------------------------------------------------- */
@ -561,13 +561,13 @@
* CAN2SB[5:0]: CAN2 start bank
* (only on connectivity line devices otherwise reserved)
*/
#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
#define CAN_FMR_CAN2SB_SHIFT 15
#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
#define CAN_FMR_CAN2SB_SHIFT 15
/* 7:1 Reserved, forced to reset value */
/* FINIT: Filter init mode */
#define CAN_FMR_FINIT (1 << 0)
#define CAN_FMR_FINIT (1 << 0)
/* --- CAN_FM1R values ------------------------------------------------------ */

166
include/libopencm3/stm32/f1/dma.h
View File

@ -26,152 +26,152 @@
/* --- Convenience macros -------------------------------------------------- */
/* DMA register base adresses (for convenience) */
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
/* --- DMA registers ------------------------------------------------------- */
/* DMA interrupt status register (DMAx_ISR) */
#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
#define DMA1_ISR DMA_ISR(DMA1)
#define DMA2_ISR DMA_ISR(DMA2)
#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
#define DMA1_ISR DMA_ISR(DMA1)
#define DMA2_ISR DMA_ISR(DMA2)
/* DMA interrupt flag clear register (DMAx_IFCR) */
#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
#define DMA1_IFCR DMA_IFCR(DMA1)
#define DMA2_IFCR DMA_IFCR(DMA2)
#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
#define DMA1_IFCR DMA_IFCR(DMA1)
#define DMA2_IFCR DMA_IFCR(DMA2)
/* DMA channel 1 configuration register (DMAx_CCR1) */
#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
#define DMA1_CCR1 DMA_CCR1(DMA1)
#define DMA2_CCR1 DMA_CCR1(DMA2)
#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
#define DMA1_CCR1 DMA_CCR1(DMA1)
#define DMA2_CCR1 DMA_CCR1(DMA2)
/* DMA channel 2 configuration register (DMAx_CCR2) */
#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
#define DMA1_CCR2 DMA_CCR2(DMA1)
#define DMA2_CCR2 DMA_CCR2(DMA2)
#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
#define DMA1_CCR2 DMA_CCR2(DMA1)
#define DMA2_CCR2 DMA_CCR2(DMA2)
/* DMA channel 3 configuration register (DMAx_CCR3) */
#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
#define DMA1_CCR3 DMA_CCR3(DMA1)
#define DMA2_CCR3 DMA_CCR3(DMA2)
#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
#define DMA1_CCR3 DMA_CCR3(DMA1)
#define DMA2_CCR3 DMA_CCR3(DMA2)
/* DMA channel 4 configuration register (DMAx_CCR4) */
#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3)
#define DMA1_CCR4 DMA_CCR4(DMA1)
#define DMA2_CCR4 DMA_CCR4(DMA2)
#define DMA1_CCR4 DMA_CCR4(DMA1)
#define DMA2_CCR4 DMA_CCR4(DMA2)
/* DMA channel 5 configuration register (DMAx_CCR5) */
#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
#define DMA1_CCR5 DMA_CCR5(DMA1)
#define DMA2_CCR5 DMA_CCR5(DMA2)
#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
#define DMA1_CCR5 DMA_CCR5(DMA1)
#define DMA2_CCR5 DMA_CCR5(DMA2)
/* DMA channel 6 configuration register (DMAx_CCR6) */
#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
#define DMA1_CCR6 DMA_CCR6(DMA1)
#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
#define DMA1_CCR6 DMA_CCR6(DMA1)
/* DMA channel 7 configuration register (DMAx_CCR7) */
#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
#define DMA1_CCR7 DMA_CCR7(DMA1)
#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
#define DMA1_CCR7 DMA_CCR7(DMA1)
/* DMA channel 1 number of data register (DMAx_CNDTR1) */
#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
/* DMA channel 2 number of data register (DMAx_CNDTR2) */
#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
/* DMA channel 3 number of data register (DMAx_CNDTR3) */
#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
/* DMA channel 4 number of data register (DMAx_CNDTR4) */
#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
/* DMA channel 5 number of data register (DMAx_CNDTR5) */
#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
/* DMA channel 6 number of data register (DMAx_CNDTR6) */
#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
/* DMA channel 7 number of data register (DMAx_CNDTR7) */
#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
/* DMA channel 1 peripheral address register (DMAx_CPAR1) */
#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
#define DMA1_CPAR1 DMA_CPAR1(DMA1)
#define DMA2_CPAR1 DMA_CPAR1(DMA2)
#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
#define DMA1_CPAR1 DMA_CPAR1(DMA1)
#define DMA2_CPAR1 DMA_CPAR1(DMA2)
/* DMA channel 2 peripheral address register (DMAx_CPAR2) */
#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
#define DMA1_CPAR2 DMA_CPAR2(DMA1)
#define DMA2_CPAR2 DMA_CPAR2(DMA2)
#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
#define DMA1_CPAR2 DMA_CPAR2(DMA1)
#define DMA2_CPAR2 DMA_CPAR2(DMA2)
/* DMA channel 3 peripheral address register (DMAx_CPAR3) */
#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
#define DMA1_CPAR3 DMA_CPAR3(DMA1)
#define DMA2_CPAR3 DMA_CPAR3(DMA2)
#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
#define DMA1_CPAR3 DMA_CPAR3(DMA1)
#define DMA2_CPAR3 DMA_CPAR3(DMA2)
/* DMA channel 4 peripheral address register (DMAx_CPAR4) */
#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
#define DMA1_CPAR4 DMA_CPAR4(DMA1)
#define DMA2_CPAR4 DMA_CPAR4(DMA2)
#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
#define DMA1_CPAR4 DMA_CPAR4(DMA1)
#define DMA2_CPAR4 DMA_CPAR4(DMA2)
/* DMA channel 5 peripheral address register (DMAx_CPAR5) */
#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
#define DMA1_CPAR5 DMA_CPAR5(DMA1)
#define DMA2_CPAR5 DMA_CPAR5(DMA2)
#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
#define DMA1_CPAR5 DMA_CPAR5(DMA1)
#define DMA2_CPAR5 DMA_CPAR5(DMA2)
/* DMA channel 6 peripheral address register (DMAx_CPAR6) */
#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
#define DMA1_CPAR6 DMA_CPAR6(DMA1)
#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
#define DMA1_CPAR6 DMA_CPAR6(DMA1)
/* DMA channel 7 peripheral address register (DMAx_CPAR7) */
#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
#define DMA1_CPAR7 DMA_CPAR7(DMA1)
#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
#define DMA1_CPAR7 DMA_CPAR7(DMA1)
/* DMA channel 1 memory address register (DMAx_CMAR1) */
#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
#define DMA1_CMAR1 DMA_CMAR1(DMA1)
#define DMA2_CMAR1 DMA_CMAR1(DMA2)
#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
#define DMA1_CMAR1 DMA_CMAR1(DMA1)
#define DMA2_CMAR1 DMA_CMAR1(DMA2)
/* DMA channel 2 memory address register (DMAx_CMAR2) */
#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
#define DMA1_CMAR2 DMA_CMAR2(DMA1)
#define DMA2_CMAR2 DMA_CMAR2(DMA2)
#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
#define DMA1_CMAR2 DMA_CMAR2(DMA1)
#define DMA2_CMAR2 DMA_CMAR2(DMA2)
/* DMA channel 3 memory address register (DMAx_CMAR3) */
#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
#define DMA1_CMAR3 DMA_CMAR3(DMA1)
#define DMA2_CMAR3 DMA_CMAR3(DMA2)
#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
#define DMA1_CMAR3 DMA_CMAR3(DMA1)
#define DMA2_CMAR3 DMA_CMAR3(DMA2)
/* DMA channel 4 memory address register (DMAx_CMAR4) */
#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
#define DMA1_CMAR4 DMA_CMAR4(DMA1)
#define DMA2_CMAR4 DMA_CMAR4(DMA2)
#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
#define DMA1_CMAR4 DMA_CMAR4(DMA1)
#define DMA2_CMAR4 DMA_CMAR4(DMA2)
/* DMA channel 5 memory address register (DMAx_CMAR5) */
#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
#define DMA1_CMAR5 DMA_CMAR5(DMA1)
#define DMA2_CMAR5 DMA_CMAR5(DMA2)
#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
#define DMA1_CMAR5 DMA_CMAR5(DMA1)
#define DMA2_CMAR5 DMA_CMAR5(DMA2)
/* DMA channel 6 memory address register (DMAx_CMAR6) */
#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
#define DMA1_CMAR6 DMA_CMAR6(DMA1)
#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
#define DMA1_CMAR6 DMA_CMAR6(DMA1)
/* DMA channel 7 memory address register (DMAx_CMAR7) */
#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
#define DMA1_CMAR7 DMA_CMAR7(DMA1)
#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
#define DMA1_CMAR7 DMA_CMAR7(DMA1)
/* --- DMA_ISR values ------------------------------------------------------ */

56
include/libopencm3/stm32/f1/flash.h
View File

@ -44,48 +44,48 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_PRFTBS (1 << 5)
#define FLASH_PRFTBE (1 << 4)
#define FLASH_HLFCYA (1 << 3)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_PRFTBS (1 << 5)
#define FLASH_PRFTBE (1 << 4)
#define FLASH_HLFCYA (1 << 3)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_EOP (1 << 5)
#define FLASH_WRPRTERR (1 << 4)
#define FLASH_PGERR (1 << 2)
#define FLASH_BSY (1 << 0)
#define FLASH_EOP (1 << 5)
#define FLASH_WRPRTERR (1 << 4)
#define FLASH_PGERR (1 << 2)
#define FLASH_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_EOPIE (1 << 12)
#define FLASH_ERRIE (1 << 10)
#define FLASH_OPTWRE (1 << 9)
#define FLASH_LOCK (1 << 7)
#define FLASH_STRT (1 << 6)
#define FLASH_OPTER (1 << 5)
#define FLASH_OPTPG (1 << 4)
#define FLASH_MER (1 << 2)
#define FLASH_PER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_EOPIE (1 << 12)
#define FLASH_ERRIE (1 << 10)
#define FLASH_OPTWRE (1 << 9)
#define FLASH_LOCK (1 << 7)
#define FLASH_STRT (1 << 6)
#define FLASH_OPTER (1 << 5)
#define FLASH_OPTPG (1 << 4)
#define FLASH_MER (1 << 2)
#define FLASH_PER (1 << 1)
#define FLASH_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
#define FLASH_NRST_STDBY (1 << 4)
#define FLASH_NRST_STOP (1 << 3)
#define FLASH_WDG_SW (1 << 2)
#define FLASH_RDPRT (1 << 1)
#define FLASH_OPTERR (1 << 0)
#define FLASH_NRST_STDBY (1 << 4)
#define FLASH_NRST_STOP (1 << 3)
#define FLASH_WDG_SW (1 << 2)
#define FLASH_RDPRT (1 << 1)
#define FLASH_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
#define RDP_KEY ((u16)0x00a5)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define RDP_KEY ((u16)0x00a5)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */

138
include/libopencm3/stm32/f1/gpio.h
View File

@ -63,22 +63,22 @@
#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */
#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */
#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
/* CAN2 */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
#define GPIO_CAN2_TX GPIO13 /* PB13 */
#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
/* JTAG/SWD */
#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */
@ -404,32 +404,32 @@
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
/* PIN[3:0]: Pin selection */
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
#define AFIO_EVCR_PIN_Px10 (0xA << 0)
#define AFIO_EVCR_PIN_Px11 (0xB << 0)
#define AFIO_EVCR_PIN_Px12 (0xC << 0)
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
#define AFIO_EVCR_PIN_Px10 (0xA << 0)
#define AFIO_EVCR_PIN_Px11 (0xB << 0)
#define AFIO_EVCR_PIN_Px12 (0xC << 0)
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
/* --- AFIO_MAPR values ---------------------------------------------------- */
@ -437,98 +437,98 @@
/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
* (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: SPI3/I2S3 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
/* MII_REMAP: MII or RMII selection
* (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: CAN2 I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: Ethernet MAC I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/* TIM4_REMAP: TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* TIM3_REMAP[1:0]: TIM3 remapping */
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
/* TIM2_REMAP[1:0]: TIM2 remapping */
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
/* TIM1_REMAP[1:0]: TIM1 remapping */
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
/* USART3_REMAP[1:0]: USART3 remapping */
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
/* USART2_REMAP[1:0]: USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */

34
include/libopencm3/stm32/f1/scb.h
View File

@ -27,50 +27,50 @@
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */

221
include/libopencm3/stm32/f1/usb.h
View File

@ -26,134 +26,135 @@
/* --- USB base addresses -------------------------------------------------- */
#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
/* USB packet buffer memory base addr. */
#define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */
/* USB Control register */
#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
/* USB Interrupt status register */
#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
/* USB Frame number register */
#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
/* USB Device address register */
#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
/* USB Buffer table address register */
#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
/* USB EP register */
#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
/* --- USB control register masks / bits ----------------------------------- */
/* Interrupt mask bits, set to 1 to enable interrupt generation */
#define USB_CNTR_CTRM 0x8000
#define USB_CNTR_PMAOVRM 0x4000
#define USB_CNTR_ERRM 0x2000
#define USB_CNTR_WKUPM 0x1000
#define USB_CNTR_SUSPM 0x0800
#define USB_CNTR_RESETM 0x0400
#define USB_CNTR_SOFM 0x0200
#define USB_CNTR_ESOFM 0x0100
#define USB_CNTR_CTRM 0x8000
#define USB_CNTR_PMAOVRM 0x4000
#define USB_CNTR_ERRM 0x2000
#define USB_CNTR_WKUPM 0x1000
#define USB_CNTR_SUSPM 0x0800
#define USB_CNTR_RESETM 0x0400
#define USB_CNTR_SOFM 0x0200
#define USB_CNTR_ESOFM 0x0100
/* Request/Force bits */
#define USB_CNTR_RESUME 0x0010 /* Resume request */
#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
#define USB_CNTR_PWDN 0x0002 /* Power down */
#define USB_CNTR_FRES 0x0001 /* Force reset */
#define USB_CNTR_RESUME 0x0010 /* Resume request */
#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
#define USB_CNTR_PWDN 0x0002 /* Power down */
#define USB_CNTR_FRES 0x0001 /* Force reset */
/* --- USB interrupt status register masks / bits -------------------------- */
#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
#define USB_ISTR_ERR 0x2000 /* Error */
#define USB_ISTR_WKUP 0x1000 /* Wake up */
#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
#define USB_ISTR_RESET 0x0400 /* USB RESET request */
#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
#define USB_ISTR_ERR 0x2000 /* Error */
#define USB_ISTR_WKUP 0x1000 /* Wake up */
#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
#define USB_ISTR_RESET 0x0400 /* USB RESET request */
#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
/* --- USB interrupt status register manipulators -------------------------- */
/* Note: CTR is read only! */
#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
/* --- USB device addres register masks / bits ----------------------------- */
#define USB_DADDR_ENABLE 0x0080
#define USB_DADDR_ADDR 0x007F
#define USB_DADDR_ENABLE 0x0080
#define USB_DADDR_ADDR 0x007F
/* --- USB device addres register manipulators ----------------------------- */
/* --- USB endpoint register offsets --------------------------------------- */
#define USB_EP0 0
#define USB_EP1 1
#define USB_EP2 2
#define USB_EP3 3
#define USB_EP4 4
#define USB_EP5 5
#define USB_EP6 6
#define USB_EP7 7
#define USB_EP0 0
#define USB_EP1 1
#define USB_EP2 2
#define USB_EP3 3
#define USB_EP4 4
#define USB_EP5 5
#define USB_EP6 6
#define USB_EP7 7
/* --- USB endpoint register masks / bits ---------------------------------- */
/* Masks and toggle bits */
#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
#define USB_EP_TYPE 0x0600 /* Endpoint type */
#define USB_EP_KIND 0x0100 /* Endpoint kind.
#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
#define USB_EP_TYPE 0x0600 /* Endpoint type */
#define USB_EP_KIND 0x0100 /* Endpoint kind.
* When set and type=bulk -> double buffer
* When set and type=control -> status out
*/
#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
#define USB_EP_ADDR 0x000F /* Endpoint Address */
#define USB_EP_ADDR 0x000F /* Endpoint Address */
/* Masking all toggle bits */
#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
USB_EP_SETUP | \
USB_EP_TYPE | \
USB_EP_KIND | \
USB_EP_TX_CTR | \
USB_EP_ADDR)
#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
USB_EP_SETUP | \
USB_EP_TYPE | \
USB_EP_KIND | \
USB_EP_TX_CTR | \
USB_EP_ADDR)
/* All non toggle bits plus EP_RX toggle bits */
#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
/* All non toggle bits plus EP_TX toggle bits */
#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
/* Endpoint status bits for USB_EP_RX_STAT bit field */
#define USB_EP_RX_STAT_DISABLED 0x0000
#define USB_EP_RX_STAT_STALL 0x1000
#define USB_EP_RX_STAT_NAK 0x2000
#define USB_EP_RX_STAT_VALID 0x3000
#define USB_EP_RX_STAT_DISABLED 0x0000
#define USB_EP_RX_STAT_STALL 0x1000
#define USB_EP_RX_STAT_NAK 0x2000
#define USB_EP_RX_STAT_VALID 0x3000
/* Endpoint status bits for USB_EP_TX_STAT bit field */
#define USB_EP_TX_STAT_DISABLED 0x0000
#define USB_EP_TX_STAT_STALL 0x0010
#define USB_EP_TX_STAT_NAK 0x0020
#define USB_EP_TX_STAT_VALID 0x0030
#define USB_EP_TX_STAT_DISABLED 0x0000
#define USB_EP_TX_STAT_STALL 0x0010
#define USB_EP_TX_STAT_NAK 0x0020
#define USB_EP_TX_STAT_VALID 0x0030
/* Endpoint type bits for USB_EP_TYPE bit field */
#define USB_EP_TYPE_BULK 0x0000
#define USB_EP_TYPE_CONTROL 0x0200
#define USB_EP_TYPE_ISO 0x0400
#define USB_EP_TYPE_INTERRUPT 0x0600
#define USB_EP_TYPE_BULK 0x0000
#define USB_EP_TYPE_CONTROL 0x0200
#define USB_EP_TYPE_ISO 0x0400
#define USB_EP_TYPE_INTERRUPT 0x0600
/* --- USB endpoint register manipulators ---------------------------------- */
@ -185,46 +186,46 @@
#define USB_CLR_EP_TX_CTR(EP) \
USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
#define USB_SET_EP_TYPE(EP, TYPE) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_TYPE))) | TYPE)
#define USB_SET_EP_TYPE(EP, TYPE) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_TYPE))) | TYPE)
#define USB_SET_EP_KIND(EP) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_KIND))) | USB_EP_KIND)
#define USB_SET_EP_KIND(EP) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_KIND))) | USB_EP_KIND)
#define USB_CLR_EP_KIND(EP) \
SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
(USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
#define USB_SET_EP_ADDR(EP, ADDR) \
SET_REG(USB_EP_REG(EP), \
((GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_ADDR))) | ADDR))
#define USB_SET_EP_ADDR(EP, ADDR) \
SET_REG(USB_EP_REG(EP), \
((GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \
(~USB_EP_ADDR))) | ADDR))
/* Macros for clearing DTOG bits */
#define USB_CLR_EP_TX_DTOG(EP) \
SET_REG(USB_EP_REG(EP), \
GET_REG(USB_EP_REG(EP)) & \
#define USB_CLR_EP_TX_DTOG(EP) \
SET_REG(USB_EP_REG(EP), \
GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))
#define USB_CLR_EP_RX_DTOG(EP) \
SET_REG(USB_EP_REG(EP), \
GET_REG(USB_EP_REG(EP)) & \
#define USB_CLR_EP_RX_DTOG(EP) \
SET_REG(USB_EP_REG(EP), \
GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
/* --- USB BTABLE registers ------------------------------------------------ */
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
#define USB_EP_TX_ADDR(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
@ -240,14 +241,14 @@
/* --- USB BTABLE manipulators --------------------------------------------- */
#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_BUFF(EP) \
(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))

118
include/libopencm3/stm32/f2/flash.h
View File

@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
@ -145,10 +145,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

18
include/libopencm3/stm32/f2/gpio.h
View File

@ -179,8 +179,8 @@
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2*(n)))
#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
@ -193,8 +193,8 @@
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
@ -202,8 +202,8 @@
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
@ -231,8 +231,8 @@
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n)*4))
#define GPIO_AFR_MASK(n) (0xf << ((n)*4))
#define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2
@ -258,7 +258,7 @@
* Note: The F2 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
* closely match the peripheral capabilities and also to deliberately break
* compatibility with old F1 code so there is no confusion with similar
* compatibility with old F1 code so there is no confusion with similar
* sounding functions that have very different functionality.
*/

162
include/libopencm3/stm32/f2/nvic_f2.h
View File

@ -27,86 +27,86 @@
*/
/* User Interrupts */
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_USART4_IRQ 52
#define NVIC_USART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_USART4_IRQ 52
#define NVIC_USART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#endif

16
include/libopencm3/stm32/f2/rcc.h
View File

@ -132,14 +132,14 @@
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2

34
include/libopencm3/stm32/f2/scb.h
View File

@ -27,50 +27,50 @@
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */

6
include/libopencm3/stm32/f2/spi.h
View File

@ -30,13 +30,13 @@
/* --- SPI_CR2 values ------------------------------------------------------ */
/* FRF: Frame format. */
#define SPI_CR2_FRF (1 << 4)
#define SPI_CR2_FRF_TI (1 << 4)
#define SPI_CR2_FRF (1 << 4)
#define SPI_CR2_FRF_TI (1 << 4)
#define SPI_CR2_FRF_MOTOROLA (1 << 4)
/* --- SPI_SR values ------------------------------------------------------- */
/* TIFRFE: TI frame format error. */
#define SPI_SR_RXNE (1 << 0)
#define SPI_SR_RXNE (1 << 0)
#endif

2
include/libopencm3/stm32/f2/syscfg.h
View File

@ -40,7 +40,7 @@
/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
#endif

29
include/libopencm3/stm32/f2/timer.h
View File

@ -22,33 +22,32 @@
#include <libopencm3/stm32/timer.h>
/*
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
*/
/* Timer 2/5 option register (TIMx_OR) */
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
#define TIM2_OR TIM_OR(TIM2)
#define TIM5_OR TIM_OR(TIM5)
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
#define TIM2_OR TIM_OR(TIM2)
#define TIM5_OR TIM_OR(TIM5)
/* --- TIM2_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
/* --- TIM5_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
#endif

2
include/libopencm3/stm32/f2/usart.h
View File

@ -30,6 +30,6 @@
/* --- USART_CR3 values ---------------------------------------------------- */
/* ONEBIT: One sample bit method enable */
#define USART_CR3_ONEBIT (1 << 11)
#define USART_CR3_ONEBIT (1 << 11)
#endif

118
include/libopencm3/stm32/f4/flash.h
View File

@ -42,76 +42,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
#define FLASH_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11)
#define FLASH_DCE (1 << 10)
#define FLASH_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1)
#define FLASH_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
#define FLASH_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16)
#define FLASH_MER (1 << 2)
#define FLASH_SER (1 << 1)
#define FLASH_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
#define FLASH_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
#define FLASH_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
@ -144,10 +144,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

18
include/libopencm3/stm32/f4/gpio.h
View File

@ -179,8 +179,8 @@
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2*(n)))
#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
@ -193,8 +193,8 @@
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
@ -202,8 +202,8 @@
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
@ -231,8 +231,8 @@
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n)*4))
#define GPIO_AFR_MASK(n) (0xf << ((n)*4))
#define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2
@ -258,7 +258,7 @@
* Note: The F2 series has a completely new GPIO peripheral with different
* configuration options. Here we implement a different API partly to more
* closely match the peripheral capabilities and also to deliberately break
* compatibility with old F1 code so there is no confusion with similar
* compatibility with old F1 code so there is no confusion with similar
* sounding functions that have very different functionality.
*/

162
include/libopencm3/stm32/f4/nvic_f4.h
View File

@ -27,86 +27,86 @@
*/
/* User Interrupts */
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_USART4_IRQ 52
#define NVIC_USART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#define NVIC_NVIC_WWDG_IRQ 0
#define NVIC_PVD_IRQ 1
#define NVIC_TAMP_STAMP_IRQ 2
#define NVIC_RTC_WKUP_IRQ 3
#define NVIC_FLASH_IRQ 4
#define NVIC_RCC_IRQ 5
#define NVIC_EXTI0_IRQ 6
#define NVIC_EXTI1_IRQ 7
#define NVIC_EXTI2_IRQ 8
#define NVIC_EXTI3_IRQ 9
#define NVIC_EXTI4_IRQ 10
#define NVIC_DMA1_STREAM0_IRQ 11
#define NVIC_DMA1_STREAM1_IRQ 12
#define NVIC_DMA1_STREAM2_IRQ 13
#define NVIC_DMA1_STREAM3_IRQ 14
#define NVIC_DMA1_STREAM4_IRQ 15
#define NVIC_DMA1_STREAM5_IRQ 16
#define NVIC_DMA1_STREAM6_IRQ 17
#define NVIC_ADC_IRQ 18
#define NVIC_CAN1_TX_IRQ 19
#define NVIC_CAN1_RX0_IRQ 20
#define NVIC_CAN1_RX1_IRQ 21
#define NVIC_CAN1_SCE_IRQ 22
#define NVIC_EXTI9_5_IRQ 23
#define NVIC_TIM1_BRK_TIM9_IRQ 24
#define NVIC_TIM1_UP_TIM10_IRQ 25
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
#define NVIC_TIM1_CC_IRQ 27
#define NVIC_TIM2_IRQ 28
#define NVIC_TIM3_IRQ 29
#define NVIC_TIM4_IRQ 30
#define NVIC_I2C1_EV_IRQ 31
#define NVIC_I2C1_ER_IRQ 32
#define NVIC_I2C2_EV_IRQ 33
#define NVIC_I2C2_ER_IRQ 34
#define NVIC_SPI1_IRQ 35
#define NVIC_SPI2_IRQ 36
#define NVIC_USART1_IRQ 37
#define NVIC_USART2_IRQ 38
#define NVIC_USART3_IRQ 39
#define NVIC_EXTI15_10_IRQ 40
#define NVIC_RTC_ALARM_IRQ 41
#define NVIC_USB_FS_WKUP_IRQ 42
#define NVIC_TIM8_BRK_TIM12_IRQ 43
#define NVIC_TIM8_UP_TIM13_IRQ 44
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
#define NVIC_TIM8_CC_IRQ 46
#define NVIC_DMA1_STREAM7_IRQ 47
#define NVIC_FSMC_IRQ 48
#define NVIC_SDIO_IRQ 49
#define NVIC_TIM5_IRQ 50
#define NVIC_SPI3_IRQ 51
#define NVIC_USART4_IRQ 52
#define NVIC_USART5_IRQ 53
#define NVIC_TIM6_DAC_IRQ 54
#define NVIC_TIM7_IRQ 55
#define NVIC_DMA2_STREAM0_IRQ 56
#define NVIC_DMA2_STREAM1_IRQ 57
#define NVIC_DMA2_STREAM2_IRQ 58
#define NVIC_DMA2_STREAM3_IRQ 59
#define NVIC_DMA2_STREAM4_IRQ 60
#define NVIC_ETH_IRQ 61
#define NVIC_ETH_WKUP_IRQ 62
#define NVIC_CAN2_TX_IRQ 63
#define NVIC_CAN2_RX0_IRQ 64
#define NVIC_CAN2_RX1_IRQ 65
#define NVIC_CAN2_SCE_IRQ 66
#define NVIC_OTG_FS_IRQ 67
#define NVIC_DMA2_STREAM5_IRQ 68
#define NVIC_DMA2_STREAM6_IRQ 69
#define NVIC_DMA2_STREAM7_IRQ 70
#define NVIC_USART6_IRQ 71
#define NVIC_I2C3_EV_IRQ 72
#define NVIC_I2C3_ER_IRQ 73
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
#define NVIC_OTG_HS_EP1_IN_IRQ 75
#define NVIC_OTG_HS_WKUP_IRQ 76
#define NVIC_OTG_HS_IRQ 77
#define NVIC_DCMI_IRQ 78
#define NVIC_CRYP_IRQ 79
#define NVIC_HASH_RNG_IRQ 80
#endif

16
include/libopencm3/stm32/f4/rcc.h
View File

@ -133,14 +133,14 @@
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2

34
include/libopencm3/stm32/f4/scb.h
View File

@ -27,50 +27,50 @@
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */

4
include/libopencm3/stm32/f4/spi.h
View File

@ -31,8 +31,8 @@
/* FRF: Frame format. */
#define SPI_CR2_FRF (1 << 4)
#define SPI_CR2_FRF_TI (1 << 4)
#define SPI_CR2_FRF_MOTOROLA (1 << 4)
#define SPI_CR2_FRF_TI (1 << 4)
#define SPI_CR2_FRF_MOTOROLA (1 << 4)
/* --- SPI_SR values ------------------------------------------------------- */

2
include/libopencm3/stm32/f4/syscfg.h
View File

@ -40,7 +40,7 @@
/* External interrupt configuration register 4 (SYSCFG_EXTICR4) */
#define SYSCFG_EXTICR4 MMIO32(SYSCFG_BASE + 0x14)
#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
#endif

29
include/libopencm3/stm32/f4/timer.h
View File

@ -22,33 +22,32 @@
#include <libopencm3/stm32/timer.h>
/*
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
*/
/* Timer 2/5 option register (TIMx_OR) */
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
#define TIM2_OR TIM_OR(TIM2)
#define TIM5_OR TIM_OR(TIM5)
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
#define TIM2_OR TIM_OR(TIM2)
#define TIM5_OR TIM_OR(TIM5)
/* --- TIM2_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
/* --- TIM5_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
#endif

2
include/libopencm3/stm32/f4/usart.h
View File

@ -30,6 +30,6 @@
/* --- USART_CR3 values ---------------------------------------------------- */
/* ONEBIT: One sample bit method enable */
#define USART_CR3_ONEBIT (1 << 11)
#define USART_CR3_ONEBIT (1 << 11)
#endif

4
include/libopencm3/stm32/i2c.h
View File

@ -26,8 +26,8 @@
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/* --- I2C registers ------------------------------------------------------- */

14
include/libopencm3/stm32/nvic.h
View File

@ -27,40 +27,40 @@
/* ISER: Interrupt Set Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
/* ICER: Interrupt Clear Enable Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
/* ISPR: Interrupt Set Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
/* ICPR: Interrupt Clear Pending Registers */
/* Note: 8 32bit Registers */
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
/* IABR: Interrupt Active Bit Register */
/* Note: 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
/* IPR: Interrupt Priority Registers */
/* Note: 240 8bit Registers */
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
/* STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE)
#define NVIC_STIR MMIO32(STIR_BASE)
/* --- IRQ channel numbers-------------------------------------------------- */

906
include/libopencm3/stm32/timer.h
View File

File diff suppressed because it is too large Load Diff

12
include/libopencm3/stm32/tools.h
View File

@ -25,20 +25,20 @@
*/
/* Get register content. */
#define GET_REG(REG) ((u16) *REG)
#define GET_REG(REG) ((u16) *REG)
/* Set register content. */
#define SET_REG(REG, VAL) (*REG = (u16)VAL)
#define SET_REG(REG, VAL) (*REG = (u16)VAL)
/* Clear register bit. */
#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
/* Clear register bit masking out some bits that must not be touched. */
#define CLR_REG_BIT_MSK(REG, MSK, BIT) \
SET_REG(REG, (GET_REG(REG) & MSK & (~BIT)))
/* Get masked out bit value. */
#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
/*
* Set/reset a bit in a masked window by using toggle mechanism.
@ -52,10 +52,10 @@
*/
#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
do { \
register u16 toggle_mask = GET_REG(REG) & (MSK); \
register u16 toggle_mask = GET_REG(REG) & (MSK); \
register u16 bit_selector; \
for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
if ((bit_selector & (BIT)) != 0) \
if ((bit_selector & (BIT)) != 0) \
toggle_mask ^= bit_selector; \
} \
SET_REG(REG, toggle_mask); \