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Fix more STM32 whitespace issues

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This commit is contained in:
Stephen Caudle 2011-10-31 11:11:03 -04:00
parent 6da485f06d
commit 1fea1df39a
28 changed files with 1343 additions and 1356 deletions
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3
include/libopencm3/stm32/f1/usb.h
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@ -26,7 +26,8 @@
/* --- USB base addresses -------------------------------------------------- */
#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
/* USB packet buffer memory base addr. */
#define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */

6
include/libopencm3/stm32/f2/flash.h
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@ -145,10 +145,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

1
include/libopencm3/stm32/f2/timer.h
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@ -22,7 +22,6 @@
#include <libopencm3/stm32/timer.h>
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4

6
include/libopencm3/stm32/f4/flash.h
View File

@ -144,10 +144,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

3
include/libopencm3/stm32/f4/timer.h
View File

@ -22,7 +22,6 @@
#include <libopencm3/stm32/timer.h>
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
@ -36,7 +35,7 @@
/* --- TIM2_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)