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Fix more STM32 whitespace issues

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This commit is contained in:
Stephen Caudle 2011-10-31 11:11:03 -04:00
parent 6da485f06d
commit 1fea1df39a
28 changed files with 1343 additions and 1356 deletions
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3
include/libopencm3/stm32/f1/usb.h
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@ -26,7 +26,8 @@
/* --- USB base addresses -------------------------------------------------- */
#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
/* USB packet buffer memory base addr. */
#define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */

6
include/libopencm3/stm32/f2/flash.h
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@ -145,10 +145,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

16
include/libopencm3/stm32/f2/gpio.h
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@ -179,8 +179,8 @@
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2*(n)))
#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
@ -193,8 +193,8 @@
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
@ -202,8 +202,8 @@
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
@ -231,8 +231,8 @@
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n)*4))
#define GPIO_AFR_MASK(n) (0xf << ((n)*4))
#define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2

16
include/libopencm3/stm32/f2/rcc.h
View File

@ -132,14 +132,14 @@
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2

1
include/libopencm3/stm32/f2/timer.h
View File

@ -22,7 +22,6 @@
#include <libopencm3/stm32/timer.h>
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4

6
include/libopencm3/stm32/f4/flash.h
View File

@ -144,10 +144,4 @@ void flash_program_byte(u32 address, u8 data, u32 program_size);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
#if 0
// TODO: Implement support for option bytes
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
#endif
#endif

16
include/libopencm3/stm32/f4/gpio.h
View File

@ -179,8 +179,8 @@
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2*(n)))
#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
@ -193,8 +193,8 @@
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
@ -202,8 +202,8 @@
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
@ -231,8 +231,8 @@
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n)*4))
#define GPIO_AFR_MASK(n) (0xf << ((n)*4))
#define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2

16
include/libopencm3/stm32/f4/rcc.h
View File

@ -133,14 +133,14 @@
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2

3
include/libopencm3/stm32/f4/timer.h
View File

@ -22,7 +22,6 @@
#include <libopencm3/stm32/timer.h>
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
@ -36,7 +35,7 @@
/* --- TIM2_OR values ---------------------------------------------------- */
/* MOE: Main output enable */
#define TIM2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)