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Vectors and Memory Map for STM32L1 series

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This commit is contained in:
Karl Palsson 2012-07-12 20:01:54 +00:00
parent f1f1aa84f3
commit 2011941b55
6 changed files with 397 additions and 1 deletions
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0
include/libopencm3/stm32/f1/desig.h → include/libopencm3/stm32/desig.h
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108
include/libopencm3/stm32/l1/memorymap.h Normal file
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@ -0,0 +1,108 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_MEMORYMAP_H
#define LIBOPENCM3_MEMORYMAP_H
#include <libopencm3/cm3/memorymap.h>
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE ((u32)0x40000000)
#define INFO_BASE ((u32)0x1ff00000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
/* Register boundary addresses */
/* APB1 */
#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
// datasheet has an error? here
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
/* gap */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
/* APB2 */
#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800)
#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00)
#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000)
/* gap */
#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400)
/* gap */
#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00)
#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
/* gap */
#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
/* AHB */
#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000)
#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400)
#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800)
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
/* gap */
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
/* gap */
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
/* gap */
#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
/* FSMC */
#define FSMC_BASE (PERIPH_BASE + 0x60000000)
/* AES */
#define AES_BASE (PERIPH_BASE + 0x10000000)
/* Device Electronic Signature */
#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C)
#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050)
#endif

2
include/libopencm3/stm32/memorymap.h
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@ -26,6 +26,8 @@
# include <libopencm3/stm32/f2/memorymap.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/memorymap.h>
#elif defined(STM32L1)
# include <libopencm3/stm32/l1/memorymap.h>
#else
# error "stm32 family not defined."
#endif

2
lib/stm32/f1/desig.c → lib/stm32/desig.c
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@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/f1/desig.h>
#include <libopencm3/stm32/desig.h>
u16 desig_get_flash_size(void)
{

58
lib/stm32/l1/Makefile Normal file
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##
## This file is part of the libopencm3 project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This library is free software: you can redistribute it and/or modify
## it under the terms of the GNU Lesser General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This library is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with this library. If not, see <http://www.gnu.org/licenses/>.
##
LIBNAME = libopencm3_stm32l1
PREFIX ?= arm-none-eabi
#PREFIX ?= arm-elf
CC = $(PREFIX)-gcc
AR = $(PREFIX)-ar
CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32L1
# ARFLAGS = rcsv
ARFLAGS = rcs
OBJS = vector.o desig.o crc.o
VPATH += ../../usb:../
# Be silent per default, but 'make V=1' will show all compiler calls.
ifneq ($(V),1)
Q := @
endif
all: $(LIBNAME).a
$(LIBNAME).a: $(OBJS)
@printf " AR $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AR) $(ARFLAGS) $@ $^
%.o: %.c
@printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(CFLAGS) -o $@ -c $<
clean:
@printf " CLEAN lib/stm32/f1\n"
$(Q)rm -f *.o *.d
$(Q)rm -f $(LIBNAME).a
.PHONY: clean
-include $(OBJS:.o=.d)

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lib/stm32/l1/vector.c Normal file
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s). */
extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
void blocking_handler(void);
void null_handler(void);
void WEAK nmi_handler(void);
void WEAK hard_fault_handler(void);
void WEAK mem_manage_handler(void);
void WEAK bus_fault_handler(void);
void WEAK usage_fault_handler(void);
void WEAK sv_call_handler(void);
void WEAK debug_monitor_handler(void);
void WEAK pend_sv_handler(void);
void WEAK sys_tick_handler(void);
void WEAK wwdg_isr(void);
void WEAK pvd_isr(void);
void WEAK tamper_isr(void);
void WEAK rtc_isr(void);
void WEAK flash_isr(void);
void WEAK rcc_isr(void);
void WEAK exti0_isr(void);
void WEAK exti1_isr(void);
void WEAK exti2_isr(void);
void WEAK exti3_isr(void);
void WEAK exti4_isr(void);
void WEAK dma1_channel1_isr(void);
void WEAK dma1_channel2_isr(void);
void WEAK dma1_channel3_isr(void);
void WEAK dma1_channel4_isr(void);
void WEAK dma1_channel5_isr(void);
void WEAK dma1_channel6_isr(void);
void WEAK dma1_channel7_isr(void);
void WEAK adc1_isr(void);
void WEAK usb_hp_isr(void);
void WEAK usb_lp_isr(void);
void WEAK dac_isr(void);
void WEAK comp_isr(void);
void WEAK exti9_5_isr(void);
void WEAK lcd_isr(void);
void WEAK tim9_isr(void);
void WEAK tim10_isr(void);
void WEAK tim11_isr(void);
void WEAK tim2_isr(void);
void WEAK tim3_isr(void);
void WEAK tim4_isr(void);
void WEAK i2c1_ev_isr(void);
void WEAK i2c1_er_isr(void);
void WEAK i2c2_ev_isr(void);
void WEAK i2c2_er_isr(void);
void WEAK spi1_isr(void);
void WEAK spi2_isr(void);
void WEAK usart1_isr(void);
void WEAK usart2_isr(void);
void WEAK usart3_isr(void);
void WEAK exti15_10_isr(void);
void WEAK rtc_alarm_isr(void);
void WEAK usb_wakeup_isr(void);
void WEAK tim6_isr(void);
void WEAK tim7_isr(void);
__attribute__ ((section(".vectors")))
void (*const vector_table[]) (void) = {
(void*)&_stack, /* Addr: 0x0000_0000 */
reset_handler, /* Addr: 0x0000_0004 */
nmi_handler, /* Addr: 0x0000_0008 */
hard_fault_handler, /* Addr: 0x0000_000C */
mem_manage_handler, /* Addr: 0x0000_0010 */
bus_fault_handler, /* Addr: 0x0000_0014 */
usage_fault_handler, /* Addr: 0x0000_0018 */
0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */
sv_call_handler, /* Addr: 0x0000_002C */
debug_monitor_handler, /* Addr: 0x0000_0030*/
0, /* Reserved Addr: 0x0000_00034 */
pend_sv_handler, /* Addr: 0x0000_0038 */
sys_tick_handler, /* Addr: 0x0000_003C */
wwdg_isr, /* Addr: 0x0000_0040 */
pvd_isr, /* Addr: 0x0000_0044 */
tamper_isr, /* Addr: 0x0000_0048 */
rtc_isr, /* Addr: 0x0000_004C */
flash_isr, /* Addr: 0x0000_0050 */
rcc_isr, /* Addr: 0x0000_0054 */
exti0_isr, /* Addr: 0x0000_0058 */
exti1_isr, /* Addr: 0x0000_005C */
exti2_isr, /* Addr: 0x0000_0060 */
exti3_isr, /* Addr: 0x0000_0064 */
exti4_isr, /* Addr: 0x0000_0068 */
dma1_channel1_isr, /* Addr: 0x0000_006C */
dma1_channel2_isr, /* Addr: 0x0000_0070 */
dma1_channel3_isr, /* Addr: 0x0000_0074 */
dma1_channel4_isr, /* Addr: 0x0000_0078 */
dma1_channel5_isr, /* Addr: 0x0000_007C */
dma1_channel6_isr, /* Addr: 0x0000_0080 */
dma1_channel7_isr, /* Addr: 0x0000_0084 */
adc1_isr, /* Addr: 0x0000_0088 */
usb_hp_isr, /* Addr: 0x0000_008C */
usb_lp_isr, /* Addr: 0x0000_0090 */
dac_isr, /* Addr: 0x0000_0094 */
comp_isr, /* Addr: 0x0000_0098 */
exti9_5_isr, /* Addr: 0x0000_009C */
lcd_isr, /* Addr: 0x0000_00A0 */
tim9_isr, /* Addr: 0x0000_00A4 */
tim10_isr, /* Addr: 0x0000_00A8 */
tim11_isr, /* Addr: 0x0000_00AC */
tim2_isr, /* Addr: 0x0000_00B0 */
tim3_isr, /* Addr: 0x0000_00B4 */
tim4_isr, /* Addr: 0x0000_00B8 */
i2c1_ev_isr, /* Addr: 0x0000_00BC */
i2c1_er_isr, /* Addr: 0x0000_00C0 */
i2c2_ev_isr, /* Addr: 0x0000_00C4 */
i2c2_er_isr, /* Addr: 0x0000_00C8 */
spi1_isr, /* Addr: 0x0000_00CC */
spi2_isr, /* Addr: 0x0000_00D0 */
usart1_isr, /* Addr: 0x0000_00D4 */
usart2_isr, /* Addr: 0x0000_00D8 */
usart3_isr, /* Addr: 0x0000_00DC */
exti15_10_isr, /* Addr: 0x0000_00E0 */
rtc_alarm_isr, /* Addr: 0x0000_00E4 */
usb_wakeup_isr, /* Addr: 0x0000_00E8 */
tim6_isr, /* Addr: 0x0000_00EC */
tim7_isr, /* Addr: 0x0000_00F0 */
};
void reset_handler(void)
{
volatile unsigned *src, *dest;
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)
*dest++ = 0;
/* Call the application's entry point. */
main();
}
void blocking_handler(void)
{
while (1) ;
}
void null_handler(void)
{
/* Do nothing. */
}
#pragma weak nmi_handler = null_handler
#pragma weak hard_fault_handler = blocking_handler
#pragma weak mem_manage_handler = blocking_handler
#pragma weak bus_fault_handler = blocking_handler
#pragma weak usage_fault_handler = blocking_handler
#pragma weak sv_call_handler = null_handler
#pragma weak debug_monitor_handler = null_handler
#pragma weak pend_sv_handler = null_handler
#pragma weak sys_tick_handler = null_handler
#pragma weak wwdg_isr = null_handler
#pragma weak pvd_isr = null_handler
#pragma weak tamper_isr = null_handler
#pragma weak rtc_isr = null_handler
#pragma weak flash_isr = null_handler
#pragma weak rcc_isr = null_handler
#pragma weak exti0_isr = null_handler
#pragma weak exti1_isr = null_handler
#pragma weak exti2_isr = null_handler
#pragma weak exti3_isr = null_handler
#pragma weak exti4_isr = null_handler
#pragma weak dma1_channel1_isr = null_handler
#pragma weak dma1_channel2_isr = null_handler
#pragma weak dma1_channel3_isr = null_handler
#pragma weak dma1_channel4_isr = null_handler
#pragma weak dma1_channel5_isr = null_handler
#pragma weak dma1_channel6_isr = null_handler
#pragma weak dma1_channel7_isr = null_handler
#pragma weak adc1_isr = null_handler
#pragma weak usb_hp_isr = null_handler
#pragma weak usb_lp_isr = null_handler
#pragma weak dac_isr = null_handler
#pragma weak comp_isr = null_handler
#pragma weak exti9_5_isr = null_handler
#pragma weak lcd_isr = null_handler
#pragma weak tim9_isr = null_handler
#pragma weak tim10_isr = null_handler
#pragma weak tim11_isr = null_handler
#pragma weak tim2_isr = null_handler
#pragma weak tim3_isr = null_handler
#pragma weak tim4_isr = null_handler
#pragma weak i2c1_ev_isr = null_handler
#pragma weak i2c1_er_isr = null_handler
#pragma weak i2c2_ev_isr = null_handler
#pragma weak i2c2_er_isr = null_handler
#pragma weak spi1_isr = null_handler
#pragma weak spi2_isr = null_handler
#pragma weak usart1_isr = null_handler
#pragma weak usart2_isr = null_handler
#pragma weak usart3_isr = null_handler
#pragma weak exti15_10_isr = null_handler
#pragma weak rtc_alarm_isr = null_handler
#pragma weak usb_wakeup_isr = null_handler
#pragma weak tim6_isr = null_handler
#pragma weak tim7_isr = null_handler