diff --git a/include/libopencm3/stm32/f0/spi.h b/include/libopencm3/stm32/f0/spi.h
new file mode 100644
index 00000000..96fec1e9
--- /dev/null
+++ b/include/libopencm3/stm32/f0/spi.h
@@ -0,0 +1,109 @@
+/** @defgroup spi_defines SPI Defines
+ *
+ * @brief Defined Constants and Types for the STM32F0xx SPI
+ *
+ * @ingroup STM32F0xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date 11 July 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include
+#include
+
+#define SPI1_BASE SPI1_I2S1_BASE
+
+
+/* DFF: Data frame format */
+/****************************************************************************/
+/** @defgroup spi_dff SPI data frame format
+ * @ingroup spi_defines
+ *
+ * @{*/
+#define SPI_CR1_CRCL_8BIT (0 << 11)
+#define SPI_CR1_CRCL_16BIT (1 << 11)
+/**@}*/
+#define SPI_CR1_CRCL (1 << 11)
+
+/* --- SPI_CR2 values ------------------------------------------------------ */
+
+/* LDMA_TX: Last DMA transfer for transmission */
+#define SPI_CR2_LDMA_TX (1 << 14)
+
+/* LDMA_RX: Last DMA transfer for reception */
+#define SPI_CR2_LDMA_RX (1 << 13)
+
+/* FRXTH: FIFO reception threshold */
+#define SPI_CR2_FRXTH (1 << 12)
+
+/* DS [3:0]: Data size */
+/* 0x0 - 0x2 NOT USED */
+#define SPI_CR2_DS_4BIT (0x3 << 8)
+#define SPI_CR2_DS_5BIT (0x4 << 8)
+#define SPI_CR2_DS_6BIT (0x5 << 8)
+#define SPI_CR2_DS_7BIT (0x6 << 8)
+#define SPI_CR2_DS_8BIT (0x7 << 8)
+#define SPI_CR2_DS_9BIT (0x8 << 8)
+#define SPI_CR2_DS_10BIT (0x9 << 8)
+#define SPI_CR2_DS_11BIT (0xA << 8)
+#define SPI_CR2_DS_12BIT (0xB << 8)
+#define SPI_CR2_DS_13BIT (0xC << 8)
+#define SPI_CR2_DS_14BIT (0xD << 8)
+#define SPI_CR2_DS_15BIT (0xE << 8)
+#define SPI_CR2_DS_16BIT (0xF << 8)
+#define SPI_CR2_DS_MASK (0xF << 8)
+
+/* NSSP: NSS pulse management */
+#define SPI_CR2_NSSP (1 << 3)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* FTLVL[1:0]: FIFO Transmission Level */
+#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
+#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
+#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
+#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
+
+/* FRLVL[1:0]: FIFO Reception Level */
+#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
+#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
+#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
+#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void spi_set_data_size(uint32_t spi, uint16_t data_s);
+void spi_fifo_reception_threshold_8bit(uint32_t spi);
+void spi_fifo_reception_threshold_16bit(uint32_t spi);
+void spi_i2s_mode_spi_mode(uint32_t spi);
+void spi_send8(uint32_t spi, uint8_t data);
+uint8_t spi_read8(uint32_t spi);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index f7df21e1..06a25af4 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -17,7 +17,9 @@
* along with this library. If not, see .
*/
-#if defined(STM32F1)
+#if defined(STM32F0)
+# include
+#elif defined(STM32F1)
# include
#elif defined(STM32F2)
# include
diff --git a/lib/stm32/common/spi_common_all.c b/lib/stm32/common/spi_common_all.c
index 762558c3..25221b03 100644
--- a/lib/stm32/common/spi_common_all.c
+++ b/lib/stm32/common/spi_common_all.c
@@ -81,6 +81,10 @@ spi_reg_base.
void spi_reset(uint32_t spi_peripheral)
{
+/* there is another way of resetting mechanism on F0. It will be extended to all
+ families of stm32 and this function will be deprecated and deleted in the
+ future.*/
+#if !defined(STM32F0)
switch (spi_peripheral) {
case SPI1:
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST);
@@ -97,6 +101,7 @@ void spi_reset(uint32_t spi_peripheral)
break;
#endif
}
+#endif
}
/* TODO: Error handling? */
diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile
index d1b3f9aa..0447708d 100644
--- a/lib/stm32/f0/Makefile
+++ b/lib/stm32/f0/Makefile
@@ -33,11 +33,11 @@ CFLAGS = -Os -g \
ARFLAGS = rcs
-OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o
+OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o spi.o
OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \
pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \
- dma_common_l1f013.o exti_common_all.o
+ dma_common_l1f013.o exti_common_all.o spi_common_all.o
VPATH += ../../usb:../:../../cm3:../common
diff --git a/lib/stm32/f0/spi.c b/lib/stm32/f0/spi.c
new file mode 100644
index 00000000..060e557d
--- /dev/null
+++ b/lib/stm32/f0/spi.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#include
+#include
+
+void spi_set_data_size(uint32_t spi, uint16_t data_s)
+{
+ SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) |
+ (data_s & SPI_CR2_DS_MASK);
+}
+
+void spi_fifo_reception_threshold_8bit(uint32_t spi)
+{
+ SPI_CR2(spi) |= SPI_CR2_FRXTH;
+}
+
+void spi_fifo_reception_threshold_16bit(uint32_t spi)
+{
+ SPI_CR2(spi) &= ~SPI_CR2_FRXTH;
+}
+
+void spi_i2s_mode_spi_mode(uint32_t spi)
+{
+ SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
+}