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[l1] Update to newest ref man definitions

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Support for the Medium+ and High density parts, mostly by way of extra
irqs and register definitions.
This commit is contained in:
Karl Palsson 2013-01-22 22:43:48 +00:00
parent df5e3e5ff1
commit 2306c907ab
2 changed files with 21 additions and 5 deletions
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19
include/libopencm3/stm32/l1/irq.yaml
View File

@ -4,8 +4,8 @@ partname_doxygen: STM32L1
irqs: irqs:
- wwdg - wwdg
- pvd - pvd
- tamper - tamper_stamp
- rtc - rtc_wkup
- flash - flash
- rcc - rcc
- exti0 - exti0
@ -44,6 +44,19 @@ irqs:
- usart3 - usart3
- exti15_10 - exti15_10
- rtc_alarm - rtc_alarm
- usb_wakeup - usb_fs_wakeup
- tim6 - tim6
- tim7 - tim7
# below here is medium+/high density
- sdio
- tim5
- spi3
- uart4
- uart5
- dma2_ch1
- dma2_ch2
- dma2_ch3
- dma2_ch4
- dma2_ch5
- aes
- comp_acq

7
include/libopencm3/stm32/l1/memorymap.h
View File

@ -47,7 +47,6 @@
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
// datasheet has an error? here
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
@ -61,6 +60,7 @@
/* gap */ /* gap */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00) #define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04) #define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
@ -85,13 +85,16 @@
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00) #define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000) #define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400) #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
/* gap */ /* gap */
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) #define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
/* gap */ /* gap */
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800) #define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
/* gap */ /* gap */
#define DMA_BASE (PERIPH_BASE_AHB + 0x06000) #define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
/* PPIB */ /* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000) #define DBGMCU_BASE (PPBI_BASE + 0x00042000)