Add generated bit/shift/mask #defines for CGU, CREG, RGU, USB (USB0 only) peripherals.
Added script used to generate #defines above. Fixed one small change in the #define naming scheme in i2c0_init().
This commit is contained in:
Jared Boone
Piotr Esden-Tempski
parent
49b2be5224
commit
24d8d81b43
@ -179,61 +179,710 @@ LGPL License Terms @ref lgpl_license
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/* Output stage 27 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
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/* --- CGU_XTAL_OSC_CTRL values -------------------------------------------- */
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/* --- CGU_FREQ_MON values -------------------------------------- */
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << 0) /* enable or power down xtal osc */
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << 1) /* external clock input (not xtal) */
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#define CGU_XTAL_OSC_CTRL_HF (1 << 2) /* high frequency mode (>15 MHz) */
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/* RCNT: 9-bit reference clock-counter value */
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#define CGU_FREQ_MON_RCNT_SHIFT (0)
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#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)
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#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------------------ */
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/* FCNT: 14-bit selected clock-counter value */
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#define CGU_FREQ_MON_FCNT_SHIFT (9)
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#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_PLL1_STAT_LOCK (1 << 0)
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/* MEAS: Measure frequency */
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#define CGU_FREQ_MON_MEAS_SHIFT (23)
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#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------------------ */
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/* CLK_SEL: Clock-source selection for the clock to be measured */
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#define CGU_FREQ_MON_CLK_SEL_SHIFT (24)
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#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_PD (1 << 0) /* power down */
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#define CGU_PLL1_CTRL_BYPASS (1 << 1) /* PLL input to post-dividers */
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#define CGU_PLL1_CTRL_FBSEL (1 << 6) /* use clkout as feedback input */
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#define CGU_PLL1_CTRL_DIRECT (1 << 7) /* enable direct CCO output */
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#define CGU_PLL1_CTRL_PSEL_SHIFT 8 /* division ratio P (2 bits) */
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_PLL1_CTRL_NSEL_SHIFT 12 /* division ratio N (2 bits) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT 16 /* division ratio M (8 bits) */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
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/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */
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/* --- CGU_PLL0USB_STAT values --------------------------------------------- */
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/* ENABLE: Oscillator-pad enable */
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#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)
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#define CGU_PLL0USB_STAT_LOCK (1 << 0) /* PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_FR (1 << 1) /* PLL0 free running indicator */
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/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */
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#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)
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/* --- CGU_PLL0USB_CTRL values --------------------------------------------- */
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/* HF: Select frequency range */
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#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2)
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#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)
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#define CGU_PLL0USB_CTRL_PD (1 << 0) /* power down */
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#define CGU_PLL0USB_CTRL_BYPASS (1 << 1) /* input to post-dividers */
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << 2) /* direct input */
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << 3) /* direct output */
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#define CGU_PLL0USB_CTRL_CLKEN (1 << 4) /* clock enable */
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#define CGU_PLL0USB_CTRL_FRM (1 << 6) /* free running mode */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT 24 /* clock source (5 bits) */
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/* --- CGU_PLL0USB_STAT values ---------------------------------- */
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/* --- CGU_PLL0USB_MDIV values --------------------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT 0 /* Decoded M-divider value (17 bits) */
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#define CGU_PLL0USB_SELP_MDEC_SHIFT 17 /* Bandwidth select P value (5 bits) */
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#define CGU_PLL0USB_SELI_MDEC_SHIFT 22 /* Bandwidth select I value (6 bits) */
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#define CGU_PLL0USB_SELR_MDEC_SHIFT 28 /* Bandwidth select R value (4 bits) */
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0USB_STAT_FR_SHIFT (1)
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#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values ------------------------------------------- */
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/* --- CGU_PLL0USB_CTRL values ---------------------------------- */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT 0 /* Decoded P-divider value (7 bits) */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT 12 /* Decoded N-divider value (8 bits) */
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/* PD: PLL0 power down */
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#define CGU_PLL0USB_CTRL_PD_SHIFT (0)
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#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)
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/* --- CGU_BASE_x_CLK values ----------------------------------------------- */
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)
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#define CGU_BASE_CLK_PD (1 << 0) /* output stage power-down */
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#define CGU_BASE_CLK_AUTOBLOCK (1 << 11) /* block clock automatically */
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#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0USB_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0USB_MDIV values ---------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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/* SELP: Bandwidth select P value */
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#define CGU_PLL0USB_MDIV_SELP_SHIFT (17)
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#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)
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#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)
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/* SELI: Bandwidth select I value */
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#define CGU_PLL0USB_MDIV_SELI_SHIFT (22)
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#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)
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#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)
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/* SELR: Bandwidth select R value */
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#define CGU_PLL0USB_MDIV_SELR_SHIFT (28)
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#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)
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#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1)
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#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)
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/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0)
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#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)
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/* PLLFRACT_REQ: Fractional PLL word write request */
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)
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/* SEL_EXT: Select fractional divider */
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)
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/* MOD_PD: Sigma-Delta modulator power-down */
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#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)
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#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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#define CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */
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/* PLLFRACT_CTRL: PLL fractional divider control word */
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------- */
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/* LOCK: PLL1 lock indicator */
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#define CGU_PLL1_STAT_LOCK_SHIFT (0)
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#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------- */
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/* PD: PLL1 power down */
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#define CGU_PLL1_CTRL_PD_SHIFT (0)
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#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL1_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)
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/* FBSEL: PLL feedback select */
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#define CGU_PLL1_CTRL_FBSEL_SHIFT (6)
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#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)
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/* DIRECT: PLL direct CCO output */
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#define CGU_PLL1_CTRL_DIRECT_SHIFT (7)
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#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)
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/* PSEL: Post-divider division ratio P */
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#define CGU_PLL1_CTRL_PSEL_SHIFT (8)
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#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
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#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)
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/* NSEL: Pre-divider division ratio N */
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#define CGU_PLL1_CTRL_NSEL_SHIFT (12)
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#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
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#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)
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/* MSEL: Feedback-divider division ratio (M) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT (16)
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#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)
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#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)
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/* CLK_SEL: Clock-source selection */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVA_CTRL values ------------------------------------ */
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/* PD: Integer divider power down */
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#define CGU_IDIVA_CTRL_PD_SHIFT (0)
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#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)
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/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */
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#define CGU_IDIVA_CTRL_IDIV_SHIFT (2)
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#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)
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#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVB_CTRL values ------------------------------------ */
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/* PD: Integer divider power down */
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#define CGU_IDIVB_CTRL_PD_SHIFT (0)
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#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)
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||||
/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVB_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVC_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVC_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVC_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVD_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVD_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVD_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_IDIVE_CTRL values ------------------------------------ */
|
||||
|
||||
/* PD: Integer divider power down */
|
||||
#define CGU_IDIVE_CTRL_PD_SHIFT (0)
|
||||
#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)
|
||||
|
||||
/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */
|
||||
#define CGU_IDIVE_CTRL_IDIV_SHIFT (2)
|
||||
#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)
|
||||
#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
|
||||
#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SAFE_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SAFE_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_USB0_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_USB0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_USB1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_USB1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_M4_CLK values ----------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_M4_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SPI_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SPI_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APB1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APB1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APB3_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APB3_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_LCD_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_LCD_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_VADC_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_VADC_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SDIO_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SDIO_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SSP0_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SSP0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_SSP1_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_SSP1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART0_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART1_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART2_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART2_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_UART3_CLK values -------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_UART3_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_OUT_CLK values ---------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_OUT_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_APLL_CLK values --------------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_APLL_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */
|
||||
|
||||
/* PD: Output stage power down */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)
|
||||
|
||||
/* AUTOBLOCK: Block clock automatically during frequency change */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)
|
||||
|
||||
/* CLK_SEL: Clock source selection */
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
|
||||
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
|
||||
|
||||
|
||||
@ -102,6 +102,249 @@ LGPL License Terms @ref lgpl_license
|
||||
/* USB1 frame length adjust register */
|
||||
#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)
|
||||
|
||||
/* --- CREG_CREG0 values ---------------------------------------- */
|
||||
|
||||
/* EN1KHZ: Enable 1 kHz output */
|
||||
#define CREG_CREG0_EN1KHZ_SHIFT (0)
|
||||
#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)
|
||||
|
||||
/* EN32KHZ: Enable 32 kHz output */
|
||||
#define CREG_CREG0_EN32KHZ_SHIFT (1)
|
||||
#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)
|
||||
|
||||
/* RESET32KHZ: 32 kHz oscillator reset */
|
||||
#define CREG_CREG0_RESET32KHZ_SHIFT (2)
|
||||
#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)
|
||||
|
||||
/* PD32KHZ: 32 kHz power control */
|
||||
#define CREG_CREG0_PD32KHZ_SHIFT (3)
|
||||
#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)
|
||||
|
||||
/* USB0PHY: USB0 PHY power control */
|
||||
#define CREG_CREG0_USB0PHY_SHIFT (5)
|
||||
#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)
|
||||
|
||||
/* ALARMCTRL: RTC_ALARM pin output control */
|
||||
#define CREG_CREG0_ALARMCTRL_SHIFT (6)
|
||||
#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)
|
||||
#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)
|
||||
|
||||
/* BODLVL1: BOD trip level to generate an interrupt */
|
||||
#define CREG_CREG0_BODLVL1_SHIFT (8)
|
||||
#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)
|
||||
#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)
|
||||
|
||||
/* BODLVL2: BOD trip level to generate a reset */
|
||||
#define CREG_CREG0_BODLVL2_SHIFT (10)
|
||||
#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)
|
||||
#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)
|
||||
|
||||
/* SAMPLECTRL: SAMPLE pin input/output control */
|
||||
#define CREG_CREG0_SAMPLECTRL_SHIFT (12)
|
||||
#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)
|
||||
#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)
|
||||
|
||||
/* WAKEUP0CTRL: WAKEUP0 pin input/output control */
|
||||
#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14)
|
||||
#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)
|
||||
#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)
|
||||
|
||||
/* WAKEUP1CTRL: WAKEUP1 pin input/output control */
|
||||
#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16)
|
||||
#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)
|
||||
#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)
|
||||
|
||||
/* --- CREG_M4MEMMAP values ------------------------------------- */
|
||||
|
||||
/* M4MAP: Shadow address when accessing memory at address 0x00000000 */
|
||||
#define CREG_M4MEMMAP_M4MAP_SHIFT (12)
|
||||
#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)
|
||||
#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)
|
||||
|
||||
/* --- CREG_CREG5 values ---------------------------------------- */
|
||||
|
||||
/* M4TAPSEL: JTAG debug select for M4 core */
|
||||
#define CREG_CREG5_M4TAPSEL_SHIFT (6)
|
||||
#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)
|
||||
|
||||
/* M0APPTAPSEL: JTAG debug select for M0 co-processor */
|
||||
#define CREG_CREG5_M0APPTAPSEL_SHIFT (9)
|
||||
#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)
|
||||
|
||||
/* --- CREG_DMAMUX values --------------------------------------- */
|
||||
|
||||
/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */
|
||||
#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0)
|
||||
#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)
|
||||
|
||||
/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */
|
||||
#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2)
|
||||
#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)
|
||||
|
||||
/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */
|
||||
#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4)
|
||||
#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)
|
||||
|
||||
/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */
|
||||
#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6)
|
||||
#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)
|
||||
|
||||
/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */
|
||||
#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8)
|
||||
#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)
|
||||
|
||||
/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */
|
||||
#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10)
|
||||
#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)
|
||||
|
||||
/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */
|
||||
#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12)
|
||||
#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)
|
||||
|
||||
/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */
|
||||
#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14)
|
||||
#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)
|
||||
|
||||
/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */
|
||||
#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16)
|
||||
#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)
|
||||
|
||||
/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */
|
||||
#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18)
|
||||
#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)
|
||||
|
||||
/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */
|
||||
#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20)
|
||||
#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)
|
||||
|
||||
/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */
|
||||
#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22)
|
||||
#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)
|
||||
|
||||
/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */
|
||||
#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24)
|
||||
#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)
|
||||
|
||||
/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */
|
||||
#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26)
|
||||
#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)
|
||||
|
||||
/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */
|
||||
#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28)
|
||||
#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)
|
||||
|
||||
/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */
|
||||
#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30)
|
||||
#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)
|
||||
#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)
|
||||
|
||||
/* --- CREG_FLASHCFGA values ------------------------------------ */
|
||||
|
||||
/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */
|
||||
#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12)
|
||||
#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)
|
||||
#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)
|
||||
|
||||
/* POW: Flash bank A power control */
|
||||
#define CREG_FLASHCFGA_POW_SHIFT (31)
|
||||
#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)
|
||||
|
||||
/* --- CREG_FLASHCFGB values ------------------------------------ */
|
||||
|
||||
/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */
|
||||
#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12)
|
||||
#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)
|
||||
#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)
|
||||
|
||||
/* POW: Flash bank B power control */
|
||||
#define CREG_FLASHCFGB_POW_SHIFT (31)
|
||||
#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)
|
||||
|
||||
/* --- CREG_ETBCFG values --------------------------------------- */
|
||||
|
||||
/* ETB: Select SRAM interface */
|
||||
#define CREG_ETBCFG_ETB_SHIFT (0)
|
||||
#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)
|
||||
|
||||
/* --- CREG_CREG6 values ---------------------------------------- */
|
||||
|
||||
/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the PHY interface */
|
||||
#define CREG_CREG6_ETHMODE_SHIFT (0)
|
||||
#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)
|
||||
#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)
|
||||
|
||||
/* CTOUTCTRL: Selects the functionality of the SCT outputs */
|
||||
#define CREG_CREG6_CTOUTCTRL_SHIFT (4)
|
||||
#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)
|
||||
|
||||
/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */
|
||||
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)
|
||||
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)
|
||||
|
||||
/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */
|
||||
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)
|
||||
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)
|
||||
|
||||
/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */
|
||||
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)
|
||||
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)
|
||||
|
||||
/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */
|
||||
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)
|
||||
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)
|
||||
|
||||
/* EMC_CLK_SEL: EMC_CLK divided clock select */
|
||||
#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16)
|
||||
#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)
|
||||
|
||||
/* --- CREG_M4TXEVENT values ------------------------------------ */
|
||||
|
||||
/* TXEVCLR: Cortex-M4 TXEV event */
|
||||
#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0)
|
||||
#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)
|
||||
|
||||
/* --- CREG_M0TXEVENT values ------------------------------------ */
|
||||
|
||||
/* TXEVCLR: Cortex-M0 TXEV event */
|
||||
#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0)
|
||||
#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)
|
||||
|
||||
/* --- CREG_M0APPMEMMAP values ---------------------------------- */
|
||||
|
||||
/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */
|
||||
#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)
|
||||
#define CREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
|
||||
#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
|
||||
|
||||
/* --- CREG_USB0FLADJ values ------------------------------------ */
|
||||
|
||||
/* FLTV: Frame length timing value */
|
||||
#define CREG_USB0FLADJ_FLTV_SHIFT (0)
|
||||
#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)
|
||||
#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)
|
||||
|
||||
/* --- CREG_USB1FLADJ values ------------------------------------ */
|
||||
|
||||
/* FLTV: Frame length timing value */
|
||||
#define CREG_USB1FLADJ_FLTV_SHIFT (0)
|
||||
#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)
|
||||
#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)
|
||||
|
||||
/**@}*/
|
||||
|
||||
#endif
|
||||
|
||||
@ -257,6 +257,885 @@ LGPL License Terms @ref lgpl_license
|
||||
/* Reserved */
|
||||
#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)
|
||||
|
||||
/* --- RESET_CTRL0 values --------------------------------------- */
|
||||
|
||||
/* CORE_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_CORE_RST_SHIFT (0)
|
||||
#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT)
|
||||
|
||||
/* PERIPH_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_PERIPH_RST_SHIFT (1)
|
||||
#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT)
|
||||
|
||||
/* MASTER_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_MASTER_RST_SHIFT (2)
|
||||
#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT)
|
||||
|
||||
/* WWDT_RST: Writing a one to this bit has no effect */
|
||||
#define RESET_CTRL0_WWDT_RST_SHIFT (4)
|
||||
#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT)
|
||||
|
||||
/* CREG_RST: Writing a one to this bit has no effect */
|
||||
#define RESET_CTRL0_CREG_RST_SHIFT (5)
|
||||
#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT)
|
||||
|
||||
/* BUS_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_BUS_RST_SHIFT (8)
|
||||
#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT)
|
||||
|
||||
/* SCU_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_SCU_RST_SHIFT (9)
|
||||
#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT)
|
||||
|
||||
/* M4_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_M4_RST_SHIFT (13)
|
||||
#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT)
|
||||
|
||||
/* LCD_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_LCD_RST_SHIFT (16)
|
||||
#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT)
|
||||
|
||||
/* USB0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_USB0_RST_SHIFT (17)
|
||||
#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT)
|
||||
|
||||
/* USB1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_USB1_RST_SHIFT (18)
|
||||
#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT)
|
||||
|
||||
/* DMA_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_DMA_RST_SHIFT (19)
|
||||
#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT)
|
||||
|
||||
/* SDIO_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_SDIO_RST_SHIFT (20)
|
||||
#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT)
|
||||
|
||||
/* EMC_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_EMC_RST_SHIFT (21)
|
||||
#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT)
|
||||
|
||||
/* ETHERNET_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_ETHERNET_RST_SHIFT (22)
|
||||
#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT)
|
||||
|
||||
/* FLASHA_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_FLASHA_RST_SHIFT (25)
|
||||
#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT)
|
||||
|
||||
/* EEPROM_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_EEPROM_RST_SHIFT (27)
|
||||
#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT)
|
||||
|
||||
/* GPIO_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_GPIO_RST_SHIFT (28)
|
||||
#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT)
|
||||
|
||||
/* FLASHB_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL0_FLASHB_RST_SHIFT (29)
|
||||
#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT)
|
||||
|
||||
/* --- RESET_CTRL1 values --------------------------------------- */
|
||||
|
||||
/* TIMER0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_TIMER0_RST_SHIFT (0)
|
||||
#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT)
|
||||
|
||||
/* TIMER1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_TIMER1_RST_SHIFT (1)
|
||||
#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT)
|
||||
|
||||
/* TIMER2_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_TIMER2_RST_SHIFT (2)
|
||||
#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT)
|
||||
|
||||
/* TIMER3_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_TIMER3_RST_SHIFT (3)
|
||||
#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT)
|
||||
|
||||
/* RTIMER_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_RTIMER_RST_SHIFT (4)
|
||||
#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT)
|
||||
|
||||
/* SCT_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SCT_RST_SHIFT (5)
|
||||
#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT)
|
||||
|
||||
/* MOTOCONPWM_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6)
|
||||
#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT)
|
||||
|
||||
/* QEI_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_QEI_RST_SHIFT (7)
|
||||
#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT)
|
||||
|
||||
/* ADC0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_ADC0_RST_SHIFT (8)
|
||||
#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT)
|
||||
|
||||
/* ADC1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_ADC1_RST_SHIFT (9)
|
||||
#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT)
|
||||
|
||||
/* DAC_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_DAC_RST_SHIFT (10)
|
||||
#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT)
|
||||
|
||||
/* UART0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_UART0_RST_SHIFT (12)
|
||||
#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT)
|
||||
|
||||
/* UART1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_UART1_RST_SHIFT (13)
|
||||
#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT)
|
||||
|
||||
/* UART2_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_UART2_RST_SHIFT (14)
|
||||
#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT)
|
||||
|
||||
/* UART3_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_UART3_RST_SHIFT (15)
|
||||
#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT)
|
||||
|
||||
/* I2C0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_I2C0_RST_SHIFT (16)
|
||||
#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT)
|
||||
|
||||
/* I2C1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_I2C1_RST_SHIFT (17)
|
||||
#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT)
|
||||
|
||||
/* SSP0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SSP0_RST_SHIFT (18)
|
||||
#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT)
|
||||
|
||||
/* SSP1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SSP1_RST_SHIFT (19)
|
||||
#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT)
|
||||
|
||||
/* I2S_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_I2S_RST_SHIFT (20)
|
||||
#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT)
|
||||
|
||||
/* SPIFI_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SPIFI_RST_SHIFT (21)
|
||||
#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT)
|
||||
|
||||
/* CAN1_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_CAN1_RST_SHIFT (22)
|
||||
#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT)
|
||||
|
||||
/* CAN0_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_CAN0_RST_SHIFT (23)
|
||||
#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT)
|
||||
|
||||
/* M0APP_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_M0APP_RST_SHIFT (24)
|
||||
#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT)
|
||||
|
||||
/* SGPIO_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SGPIO_RST_SHIFT (25)
|
||||
#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT)
|
||||
|
||||
/* SPI_RST: Writing a one activates the reset */
|
||||
#define RESET_CTRL1_SPI_RST_SHIFT (26)
|
||||
#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT)
|
||||
|
||||
/* --- RESET_STATUS0 values ------------------------------------- */
|
||||
|
||||
/* CORE_RST: Status of the CORE_RST reset generator output */
|
||||
#define RESET_STATUS0_CORE_RST_SHIFT (0)
|
||||
#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT)
|
||||
#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT)
|
||||
|
||||
/* PERIPH_RST: Status of the PERIPH_RST reset generator output */
|
||||
#define RESET_STATUS0_PERIPH_RST_SHIFT (2)
|
||||
#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT)
|
||||
#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT)
|
||||
|
||||
/* MASTER_RST: Status of the MASTER_RST reset generator output */
|
||||
#define RESET_STATUS0_MASTER_RST_SHIFT (4)
|
||||
#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT)
|
||||
#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT)
|
||||
|
||||
/* WWDT_RST: Status of the WWDT_RST reset generator output */
|
||||
#define RESET_STATUS0_WWDT_RST_SHIFT (8)
|
||||
#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT)
|
||||
#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT)
|
||||
|
||||
/* CREG_RST: Status of the CREG_RST reset generator output */
|
||||
#define RESET_STATUS0_CREG_RST_SHIFT (10)
|
||||
#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT)
|
||||
#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT)
|
||||
|
||||
/* BUS_RST: Status of the BUS_RST reset generator output */
|
||||
#define RESET_STATUS0_BUS_RST_SHIFT (16)
|
||||
#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT)
|
||||
#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT)
|
||||
|
||||
/* SCU_RST: Status of the SCU_RST reset generator output */
|
||||
#define RESET_STATUS0_SCU_RST_SHIFT (18)
|
||||
#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT)
|
||||
#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT)
|
||||
|
||||
/* M4_RST: Status of the M4_RST reset generator output */
|
||||
#define RESET_STATUS0_M4_RST_SHIFT (26)
|
||||
#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT)
|
||||
#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT)
|
||||
|
||||
/* --- RESET_STATUS1 values ------------------------------------- */
|
||||
|
||||
/* LCD_RST: Status of the LCD_RST reset generator output */
|
||||
#define RESET_STATUS1_LCD_RST_SHIFT (0)
|
||||
#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT)
|
||||
#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT)
|
||||
|
||||
/* USB0_RST: Status of the USB0_RST reset generator output */
|
||||
#define RESET_STATUS1_USB0_RST_SHIFT (2)
|
||||
#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT)
|
||||
#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT)
|
||||
|
||||
/* USB1_RST: Status of the USB1_RST reset generator output */
|
||||
#define RESET_STATUS1_USB1_RST_SHIFT (4)
|
||||
#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT)
|
||||
#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT)
|
||||
|
||||
/* DMA_RST: Status of the DMA_RST reset generator output */
|
||||
#define RESET_STATUS1_DMA_RST_SHIFT (6)
|
||||
#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT)
|
||||
#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT)
|
||||
|
||||
/* SDIO_RST: Status of the SDIO_RST reset generator output */
|
||||
#define RESET_STATUS1_SDIO_RST_SHIFT (8)
|
||||
#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT)
|
||||
#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT)
|
||||
|
||||
/* EMC_RST: Status of the EMC_RST reset generator output */
|
||||
#define RESET_STATUS1_EMC_RST_SHIFT (10)
|
||||
#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT)
|
||||
#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT)
|
||||
|
||||
/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */
|
||||
#define RESET_STATUS1_ETHERNET_RST_SHIFT (12)
|
||||
#define RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT)
|
||||
#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT)
|
||||
|
||||
/* FLASHA_RST: Status of the FLASHA_RST reset generator output */
|
||||
#define RESET_STATUS1_FLASHA_RST_SHIFT (18)
|
||||
#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT)
|
||||
#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT)
|
||||
|
||||
/* EEPROM_RST: Status of the EEPROM_RST reset generator output */
|
||||
#define RESET_STATUS1_EEPROM_RST_SHIFT (22)
|
||||
#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT)
|
||||
#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT)
|
||||
|
||||
/* GPIO_RST: Status of the GPIO_RST reset generator output */
|
||||
#define RESET_STATUS1_GPIO_RST_SHIFT (24)
|
||||
#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT)
|
||||
#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT)
|
||||
|
||||
/* FLASHB_RST: Status of the FLASHB_RST reset generator output */
|
||||
#define RESET_STATUS1_FLASHB_RST_SHIFT (26)
|
||||
#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT)
|
||||
#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT)
|
||||
|
||||
/* --- RESET_STATUS2 values ------------------------------------- */
|
||||
|
||||
/* TIMER0_RST: Status of the TIMER0_RST reset generator output */
|
||||
#define RESET_STATUS2_TIMER0_RST_SHIFT (0)
|
||||
#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT)
|
||||
#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT)
|
||||
|
||||
/* TIMER1_RST: Status of the TIMER1_RST reset generator output */
|
||||
#define RESET_STATUS2_TIMER1_RST_SHIFT (2)
|
||||
#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT)
|
||||
#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT)
|
||||
|
||||
/* TIMER2_RST: Status of the TIMER2_RST reset generator output */
|
||||
#define RESET_STATUS2_TIMER2_RST_SHIFT (4)
|
||||
#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT)
|
||||
#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT)
|
||||
|
||||
/* TIMER3_RST: Status of the TIMER3_RST reset generator output */
|
||||
#define RESET_STATUS2_TIMER3_RST_SHIFT (6)
|
||||
#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT)
|
||||
#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT)
|
||||
|
||||
/* RITIMER_RST: Status of the RITIMER_RST reset generator output */
|
||||
#define RESET_STATUS2_RITIMER_RST_SHIFT (8)
|
||||
#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT)
|
||||
#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT)
|
||||
|
||||
/* SCT_RST: Status of the SCT_RST reset generator output */
|
||||
#define RESET_STATUS2_SCT_RST_SHIFT (10)
|
||||
#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT)
|
||||
#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT)
|
||||
|
||||
/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */
|
||||
#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12)
|
||||
#define RESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)
|
||||
#define RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)
|
||||
|
||||
/* QEI_RST: Status of the QEI_RST reset generator output */
|
||||
#define RESET_STATUS2_QEI_RST_SHIFT (14)
|
||||
#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT)
|
||||
#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT)
|
||||
|
||||
/* ADC0_RST: Status of the ADC0_RST reset generator output */
|
||||
#define RESET_STATUS2_ADC0_RST_SHIFT (16)
|
||||
#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT)
|
||||
#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT)
|
||||
|
||||
/* ADC1_RST: Status of the ADC1_RST reset generator output */
|
||||
#define RESET_STATUS2_ADC1_RST_SHIFT (18)
|
||||
#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT)
|
||||
#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT)
|
||||
|
||||
/* DAC_RST: Status of the DAC_RST reset generator output */
|
||||
#define RESET_STATUS2_DAC_RST_SHIFT (20)
|
||||
#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT)
|
||||
#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT)
|
||||
|
||||
/* UART0_RST: Status of the UART0_RST reset generator output */
|
||||
#define RESET_STATUS2_UART0_RST_SHIFT (24)
|
||||
#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT)
|
||||
#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT)
|
||||
|
||||
/* UART1_RST: Status of the UART1_RST reset generator output */
|
||||
#define RESET_STATUS2_UART1_RST_SHIFT (26)
|
||||
#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT)
|
||||
#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT)
|
||||
|
||||
/* UART2_RST: Status of the UART2_RST reset generator output */
|
||||
#define RESET_STATUS2_UART2_RST_SHIFT (28)
|
||||
#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT)
|
||||
#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT)
|
||||
|
||||
/* UART3_RST: Status of the UART3_RST reset generator output */
|
||||
#define RESET_STATUS2_UART3_RST_SHIFT (30)
|
||||
#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT)
|
||||
#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT)
|
||||
|
||||
/* --- RESET_STATUS3 values ------------------------------------- */
|
||||
|
||||
/* I2C0_RST: Status of the I2C0_RST reset generator output */
|
||||
#define RESET_STATUS3_I2C0_RST_SHIFT (0)
|
||||
#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT)
|
||||
#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT)
|
||||
|
||||
/* I2C1_RST: Status of the I2C1_RST reset generator output */
|
||||
#define RESET_STATUS3_I2C1_RST_SHIFT (2)
|
||||
#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT)
|
||||
#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT)
|
||||
|
||||
/* SSP0_RST: Status of the SSP0_RST reset generator output */
|
||||
#define RESET_STATUS3_SSP0_RST_SHIFT (4)
|
||||
#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT)
|
||||
#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT)
|
||||
|
||||
/* SSP1_RST: Status of the SSP1_RST reset generator output */
|
||||
#define RESET_STATUS3_SSP1_RST_SHIFT (6)
|
||||
#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT)
|
||||
#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT)
|
||||
|
||||
/* I2S_RST: Status of the I2S_RST reset generator output */
|
||||
#define RESET_STATUS3_I2S_RST_SHIFT (8)
|
||||
#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT)
|
||||
#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT)
|
||||
|
||||
/* SPIFI_RST: Status of the SPIFI_RST reset generator output */
|
||||
#define RESET_STATUS3_SPIFI_RST_SHIFT (10)
|
||||
#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT)
|
||||
#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT)
|
||||
|
||||
/* CAN1_RST: Status of the CAN1_RST reset generator output */
|
||||
#define RESET_STATUS3_CAN1_RST_SHIFT (12)
|
||||
#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT)
|
||||
#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT)
|
||||
|
||||
/* CAN0_RST: Status of the CAN0_RST reset generator output */
|
||||
#define RESET_STATUS3_CAN0_RST_SHIFT (14)
|
||||
#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT)
|
||||
#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT)
|
||||
|
||||
/* M0APP_RST: Status of the M0APP_RST reset generator output */
|
||||
#define RESET_STATUS3_M0APP_RST_SHIFT (16)
|
||||
#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT)
|
||||
#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT)
|
||||
|
||||
/* SGPIO_RST: Status of the SGPIO_RST reset generator output */
|
||||
#define RESET_STATUS3_SGPIO_RST_SHIFT (18)
|
||||
#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT)
|
||||
#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT)
|
||||
|
||||
/* SPI_RST: Status of the SPI_RST reset generator output */
|
||||
#define RESET_STATUS3_SPI_RST_SHIFT (20)
|
||||
#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT)
|
||||
#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT)
|
||||
|
||||
/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */
|
||||
|
||||
/* CORE_RST: Current status of the CORE_RST */
|
||||
#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0)
|
||||
#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT)
|
||||
|
||||
/* PERIPH_RST: Current status of the PERIPH_RST */
|
||||
#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1)
|
||||
#define RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT)
|
||||
|
||||
/* MASTER_RST: Current status of the MASTER_RST */
|
||||
#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2)
|
||||
#define RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT)
|
||||
|
||||
/* WWDT_RST: Current status of the WWDT_RST */
|
||||
#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4)
|
||||
#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT)
|
||||
|
||||
/* CREG_RST: Current status of the CREG_RST */
|
||||
#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5)
|
||||
#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT)
|
||||
|
||||
/* BUS_RST: Current status of the BUS_RST */
|
||||
#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8)
|
||||
#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT)
|
||||
|
||||
/* SCU_RST: Current status of the SCU_RST */
|
||||
#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9)
|
||||
#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT)
|
||||
|
||||
/* M4_RST: Current status of the M4_RST */
|
||||
#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13)
|
||||
#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT)
|
||||
|
||||
/* LCD_RST: Current status of the LCD_RST */
|
||||
#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16)
|
||||
#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT)
|
||||
|
||||
/* USB0_RST: Current status of the USB0_RST */
|
||||
#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17)
|
||||
#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT)
|
||||
|
||||
/* USB1_RST: Current status of the USB1_RST */
|
||||
#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18)
|
||||
#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT)
|
||||
|
||||
/* DMA_RST: Current status of the DMA_RST */
|
||||
#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19)
|
||||
#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT)
|
||||
|
||||
/* SDIO_RST: Current status of the SDIO_RST */
|
||||
#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20)
|
||||
#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT)
|
||||
|
||||
/* EMC_RST: Current status of the EMC_RST */
|
||||
#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21)
|
||||
#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT)
|
||||
|
||||
/* ETHERNET_RST: Current status of the ETHERNET_RST */
|
||||
#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22)
|
||||
#define RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT)
|
||||
|
||||
/* FLASHA_RST: Current status of the FLASHA_RST */
|
||||
#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25)
|
||||
#define RESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT)
|
||||
|
||||
/* EEPROM_RST: Current status of the EEPROM_RST */
|
||||
#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27)
|
||||
#define RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT)
|
||||
|
||||
/* GPIO_RST: Current status of the GPIO_RST */
|
||||
#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28)
|
||||
#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT)
|
||||
|
||||
/* FLASHB_RST: Current status of the FLASHB_RST */
|
||||
#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29)
|
||||
#define RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT)
|
||||
|
||||
/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */
|
||||
|
||||
/* TIMER0_RST: Current status of the TIMER0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0)
|
||||
#define RESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT)
|
||||
|
||||
/* TIMER1_RST: Current status of the TIMER1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1)
|
||||
#define RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT)
|
||||
|
||||
/* TIMER2_RST: Current status of the TIMER2_RST */
|
||||
#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2)
|
||||
#define RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT)
|
||||
|
||||
/* TIMER3_RST: Current status of the TIMER3_RST */
|
||||
#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3)
|
||||
#define RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT)
|
||||
|
||||
/* RITIMER_RST: Current status of the RITIMER_RST */
|
||||
#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4)
|
||||
#define RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT)
|
||||
|
||||
/* SCT_RST: Current status of the SCT_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5)
|
||||
#define RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT)
|
||||
|
||||
/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */
|
||||
#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6)
|
||||
#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT)
|
||||
|
||||
/* QEI_RST: Current status of the QEI_RST */
|
||||
#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7)
|
||||
#define RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT)
|
||||
|
||||
/* ADC0_RST: Current status of the ADC0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8)
|
||||
#define RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT)
|
||||
|
||||
/* ADC1_RST: Current status of the ADC1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9)
|
||||
#define RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT)
|
||||
|
||||
/* DAC_RST: Current status of the DAC_RST */
|
||||
#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10)
|
||||
#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT)
|
||||
|
||||
/* UART0_RST: Current status of the UART0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12)
|
||||
#define RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT)
|
||||
|
||||
/* UART1_RST: Current status of the UART1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13)
|
||||
#define RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT)
|
||||
|
||||
/* UART2_RST: Current status of the UART2_RST */
|
||||
#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14)
|
||||
#define RESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT)
|
||||
|
||||
/* UART3_RST: Current status of the UART3_RST */
|
||||
#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15)
|
||||
#define RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT)
|
||||
|
||||
/* I2C0_RST: Current status of the I2C0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16)
|
||||
#define RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT)
|
||||
|
||||
/* I2C1_RST: Current status of the I2C1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17)
|
||||
#define RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT)
|
||||
|
||||
/* SSP0_RST: Current status of the SSP0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18)
|
||||
#define RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT)
|
||||
|
||||
/* SSP1_RST: Current status of the SSP1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19)
|
||||
#define RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT)
|
||||
|
||||
/* I2S_RST: Current status of the I2S_RST */
|
||||
#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20)
|
||||
#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT)
|
||||
|
||||
/* SPIFI_RST: Current status of the SPIFI_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21)
|
||||
#define RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT)
|
||||
|
||||
/* CAN1_RST: Current status of the CAN1_RST */
|
||||
#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22)
|
||||
#define RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT)
|
||||
|
||||
/* CAN0_RST: Current status of the CAN0_RST */
|
||||
#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23)
|
||||
#define RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT)
|
||||
|
||||
/* M0APP_RST: Current status of the M0APP_RST */
|
||||
#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24)
|
||||
#define RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT)
|
||||
|
||||
/* SGPIO_RST: Current status of the SGPIO_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25)
|
||||
#define RESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT)
|
||||
|
||||
/* SPI_RST: Current status of the SPI_RST */
|
||||
#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26)
|
||||
#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT0 values ----------------------------------- */
|
||||
|
||||
/* EXT_RESET: Reset activated by external reset from reset pin */
|
||||
#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0)
|
||||
#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT)
|
||||
|
||||
/* BOD_RESET: Reset activated by BOD reset */
|
||||
#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4)
|
||||
#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT)
|
||||
|
||||
/* WWDT_RESET: Reset activated by WWDT time-out */
|
||||
#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5)
|
||||
#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT1 values ----------------------------------- */
|
||||
|
||||
/* CORE_RESET: Reset activated by CORE_RST output */
|
||||
#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1)
|
||||
#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT2 values ----------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT4 values ----------------------------------- */
|
||||
|
||||
/* CORE_RESET: Reset activated by CORE_RST output */
|
||||
#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1)
|
||||
#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT5 values ----------------------------------- */
|
||||
|
||||
/* CORE_RESET: Reset activated by CORE_RST output */
|
||||
#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1)
|
||||
#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT8 values ----------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT9 values ----------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT13 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT16 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT17 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT18 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT19 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT20 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT21 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT22 values ---------------------------------- */
|
||||
|
||||
/* MASTER_RESET: Reset activated by MASTER_RST output */
|
||||
#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3)
|
||||
#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT25 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT27 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT28 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT29 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT32 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT33 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT34 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT35 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT36 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT37 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT38 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT39 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT40 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT41 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT42 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT44 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT45 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT46 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT47 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT48 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT49 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT50 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT51 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT52 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT53 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT54 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT55 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT56 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT57 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/* --- RESET_EXT_STAT58 values ---------------------------------- */
|
||||
|
||||
/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
|
||||
#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2)
|
||||
#define RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT)
|
||||
|
||||
/**@}*/
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -47,7 +47,7 @@ void i2c0_init(void)
|
||||
SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
|
||||
|
||||
/* use IRC as clock source for APB1 (including I2C0) */
|
||||
CGU_BASE_APB1_CLK = (CGU_SRC_IRC << CGU_BASE_CLK_SEL_SHIFT);
|
||||
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
|
||||
|
||||
/* FIXME assuming we're on IRC at 12 MHz */
|
||||
|
||||
|
||||
54
scripts/data/lpc43xx/gen.py
Normal file
54
scripts/data/lpc43xx/gen.py
Normal file
@ -0,0 +1,54 @@
|
||||
#!/usr/bin/env python
|
||||
|
||||
import sys
|
||||
import csv
|
||||
from collections import OrderedDict
|
||||
|
||||
from pprint import pprint
|
||||
|
||||
reader = csv.reader(open(sys.argv[1], 'r'))
|
||||
|
||||
registers = OrderedDict()
|
||||
for register_name, lsb, width, field_name, description, reset_value, access in reader:
|
||||
if register_name not in registers:
|
||||
registers[register_name] = {
|
||||
'fields': OrderedDict(),
|
||||
}
|
||||
|
||||
register = registers[register_name]
|
||||
fields = register['fields']
|
||||
if field_name in fields:
|
||||
raise RuntimeError('Duplicate field name "%s" in register "%s"' %
|
||||
field_name, register_name)
|
||||
else:
|
||||
fields[field_name] = {
|
||||
'lsb': int(lsb),
|
||||
'width': int(width),
|
||||
'description': description,
|
||||
'reset_value': reset_value,
|
||||
'access': access,
|
||||
}
|
||||
|
||||
for register_name, register in registers.iteritems():
|
||||
print('/* --- %s values %s */' % (register_name, '-' * (50 - len(register_name))))
|
||||
print
|
||||
fields = register['fields']
|
||||
#for field_name, field in sorted(fields.items(), lambda x, y: cmp(x[1]['lsb'], y[1]['lsb'])):
|
||||
for field_name, field in fields.items():
|
||||
mask_bits = (1 << field['width']) - 1
|
||||
print('/* %s: %s */' % (field_name, field['description']))
|
||||
print('#define %s_%s_SHIFT (%d)' % (
|
||||
register_name, field_name, field['lsb'],
|
||||
))
|
||||
if mask_bits > 1:
|
||||
print('#define %s_%s_MASK (0x%x << %s_%s_SHIFT)' % (
|
||||
register_name, field_name, mask_bits, register_name, field_name,
|
||||
))
|
||||
print('#define %s_%s(x) ((x) << %s_%s_SHIFT)' % (
|
||||
register_name, field_name, register_name, field_name,
|
||||
))
|
||||
else:
|
||||
print('#define %s_%s (1 << %s_%s_SHIFT)' % (
|
||||
register_name, field_name, register_name, field_name,
|
||||
))
|
||||
print
|
||||
Loading…
x
Reference in New Issue
Block a user