diff --git a/include/libopencm3/stm32/common/adc_common_v1.h b/include/libopencm3/stm32/common/adc_common_v1.h
index 6ffddedf..134b235b 100644
--- a/include/libopencm3/stm32/common/adc_common_v1.h
+++ b/include/libopencm3/stm32/common/adc_common_v1.h
@@ -289,14 +289,14 @@ specific memorymap.h header before including this header file.*/
 /* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
 
 #define ADC_JOFFSET_LSB                 0
-#define ADC_JOFFSET_MSK                 (0x7ff << 0)
+#define ADC_JOFFSET_MSK                 0xfff
 #define ADC_HT_LSB                      0
-#define ADC_HT_MSK                      (0x7ff << 0)
+#define ADC_HT_MSK                      0xfff
 #define ADC_LT_LSB                      0
-#define ADC_LT_MSK                      (0x7ff << 0)
+#define ADC_LT_MSK                      0xfff
 
 /* --- ADC_SQR1 values ----------------------------------------------------- */
-/* The sequence length field is always in the same place, but sized 
+/* The sequence length field is always in the same place, but sized
  * differently on various parts */
 #define ADC_SQR1_L_LSB                  20
 
@@ -344,6 +344,53 @@ specific memorymap.h header before including this header file.*/
 
 BEGIN_DECLS
 
+void adc_power_on(uint32_t adc);
+void adc_off(uint32_t adc);
+void adc_enable_analog_watchdog_regular(uint32_t adc);
+void adc_disable_analog_watchdog_regular(uint32_t adc);
+void adc_enable_analog_watchdog_injected(uint32_t adc);
+void adc_disable_analog_watchdog_injected(uint32_t adc);
+void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
+void adc_disable_discontinuous_mode_regular(uint32_t adc);
+void adc_enable_discontinuous_mode_injected(uint32_t adc);
+void adc_disable_discontinuous_mode_injected(uint32_t adc);
+void adc_enable_automatic_injected_group_conversion(uint32_t adc);
+void adc_disable_automatic_injected_group_conversion(uint32_t adc);
+void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
+void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
+						    uint8_t channel);
+void adc_enable_scan_mode(uint32_t adc);
+void adc_disable_scan_mode(uint32_t adc);
+void adc_enable_eoc_interrupt_injected(uint32_t adc);
+void adc_disable_eoc_interrupt_injected(uint32_t adc);
+void adc_enable_awd_interrupt(uint32_t adc);
+void adc_disable_awd_interrupt(uint32_t adc);
+void adc_enable_eoc_interrupt(uint32_t adc);
+void adc_disable_eoc_interrupt(uint32_t adc);
+void adc_set_left_aligned(uint32_t adc);
+void adc_set_right_aligned(uint32_t adc);
+bool adc_eoc(uint32_t adc);
+bool adc_eoc_injected(uint32_t adc);
+uint32_t adc_read_regular(uint32_t adc);
+uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
+void adc_set_continuous_conversion_mode(uint32_t adc);
+void adc_set_single_conversion_mode(uint32_t adc);
+void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
+void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
+void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
+void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
+void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
+void adc_start_conversion_regular(uint32_t adc);
+void adc_start_conversion_injected(uint32_t adc);
+void adc_enable_dma(uint32_t adc);
+void adc_disable_dma(uint32_t adc);
+
+/* common methods that have slight differences */
+void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
+void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
+void adc_disable_external_trigger_regular(uint32_t adc);
+void adc_disable_external_trigger_injected(uint32_t adc);
+
 END_DECLS
 
 #endif
diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h
index bd44d9e7..543b8916 100644
--- a/include/libopencm3/stm32/f1/adc.h
+++ b/include/libopencm3/stm32/f1/adc.h
@@ -129,6 +129,7 @@ LGPL License Terms @ref lgpl_license
 #define ADC_CR1_DUALMOD_MASK		(0xF << 16)
 #define ADC_CR1_DUALMOD_SHIFT		16
 
+#define ADC_CR1_AWDCH_MAX		17
 
 /* --- ADC_CR2 values ------------------------------------------------------ */
 
@@ -343,18 +344,11 @@ and ADC2
 #define ADC_SMPR_SMP_239DOT5CYC		0x7
 /**@}*/
 
-/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
-
-#define ADC_JOFFSET_LSB			0
-#define ADC_JOFFSET_MSK			(0x7ff << 0)
-#define ADC_HT_LSB			0
-#define ADC_HT_MSK			(0x7ff << 0)
-#define ADC_LT_LSB			0
-#define ADC_LT_MSK			(0x7ff << 0)
 
 /* --- ADC_SQR1 values ----------------------------------------------------- */
 
-#define ADC_SQR1_L_LSB			20
+#define ADC_SQR_MAX_CHANNELS_REGULAR	16
+
 #define ADC_SQR1_SQ16_LSB		15
 #define ADC_SQR1_SQ15_LSB		10
 #define ADC_SQR1_SQ14_LSB		5
@@ -409,72 +403,18 @@ and ADC2
 
 BEGIN_DECLS
 
-void adc_power_on(uint32_t adc);
 void adc_start_conversion_direct(uint32_t adc);
 void adc_set_single_channel(uint32_t adc, uint8_t channel);
 void adc_set_dual_mode(uint32_t mode);
-bool adc_eoc(uint32_t adc);
-bool adc_eoc_injected(uint32_t adc);
-uint32_t adc_read_regular(uint32_t adc);
-uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
-void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
-void adc_enable_analog_watchdog_regular(uint32_t adc);
-void adc_disable_analog_watchdog_regular(uint32_t adc);
-void adc_enable_analog_watchdog_injected(uint32_t adc);
-void adc_disable_analog_watchdog_injected(uint32_t adc);
-void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
-void adc_disable_discontinuous_mode_regular(uint32_t adc);
-void adc_enable_discontinuous_mode_injected(uint32_t adc);
-void adc_disable_discontinuous_mode_injected(uint32_t adc);
-void adc_enable_automatic_injected_group_conversion(uint32_t adc);
-void adc_disable_automatic_injected_group_conversion(uint32_t adc);
-void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
-void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
-						    uint8_t channel);
-void adc_enable_scan_mode(uint32_t adc);
-void adc_disable_scan_mode(uint32_t adc);
-void adc_enable_eoc_interrupt_injected(uint32_t adc);
-void adc_disable_eoc_interrupt_injected(uint32_t adc);
-void adc_enable_awd_interrupt(uint32_t adc);
-void adc_disable_awd_interrupt(uint32_t adc);
-void adc_enable_eoc_interrupt(uint32_t adc);
-void adc_disable_eoc_interrupt(uint32_t adc);
 void adc_enable_temperature_sensor(uint32_t adc);
 void adc_disable_temperature_sensor(uint32_t adc);
-void adc_start_conversion_regular(uint32_t adc);
-void adc_start_conversion_injected(uint32_t adc);
 void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
-void adc_disable_external_trigger_regular(uint32_t adc);
 void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
-void adc_disable_external_trigger_injected(uint32_t adc);
-void adc_set_left_aligned(uint32_t adc);
-void adc_set_right_aligned(uint32_t adc);
-void adc_enable_dma(uint32_t adc);
-void adc_disable_dma(uint32_t adc);
 void adc_reset_calibration(uint32_t adc);
 void adc_calibration(uint32_t adc);
-void adc_set_continuous_conversion_mode(uint32_t adc);
-void adc_set_single_conversion_mode(uint32_t adc);
 void adc_on(uint32_t adc)
 	LIBOPENCM3_DEPRECATED("will be removed in the first release");
-void adc_off(uint32_t adc);
-void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
-void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
-void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
-void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
-void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
-void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
 
-void adc_set_continous_conversion_mode(uint32_t adc)
-	LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
-void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
-	LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
-void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
-	LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
-void adc_enable_jeoc_interrupt(uint32_t adc)
-	LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
-void adc_disable_jeoc_interrupt(uint32_t adc)
-	LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
 END_DECLS
 
 #endif
diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h
index 38ace8b6..63233190 100644
--- a/include/libopencm3/stm32/f4/adc.h
+++ b/include/libopencm3/stm32/f4/adc.h
@@ -118,6 +118,7 @@ LGPL License Terms @ref lgpl_license
 /* Note: Bits [21:16] are reserved, and must be kept at reset value. */
 
 /* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
+#define ADC_CR1_AWDCH_MAX		18
 
 
 /* --- ADC_CR2 values ------------------------------------------------------ */
@@ -312,18 +313,10 @@ LGPL License Terms @ref lgpl_license
 #define ADC_SMPR_SMP_480CYC		0x7
 /**@}*/
 
-/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
-
-#define ADC_JOFFSET_LSB			0
-#define ADC_JOFFSET_MSK			(0x7ff << 0)
-#define ADC_HT_LSB			0
-#define ADC_HT_MSK			(0x7ff << 0)
-#define ADC_LT_LSB			0
-#define ADC_LT_MSK			(0x7ff << 0)
-
 /* --- ADC_SQR1 values ----------------------------------------------------- */
 
-#define ADC_SQR1_L_LSB			20
+#define ADC_SQR_MAX_CHANNELS_REGULAR	16
+
 #define ADC_SQR1_SQ16_LSB		15
 #define ADC_SQR1_SQ15_LSB		10
 #define ADC_SQR1_SQ14_LSB		5
@@ -568,51 +561,6 @@ LGPL License Terms @ref lgpl_license
 
 BEGIN_DECLS
 
-void adc_power_on(uint32_t adc);
-void adc_off(uint32_t adc);
-void adc_enable_analog_watchdog_regular(uint32_t adc);
-void adc_disable_analog_watchdog_regular(uint32_t adc);
-void adc_enable_analog_watchdog_injected(uint32_t adc);
-void adc_disable_analog_watchdog_injected(uint32_t adc);
-void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
-void adc_disable_discontinuous_mode_regular(uint32_t adc);
-void adc_enable_discontinuous_mode_injected(uint32_t adc);
-void adc_disable_discontinuous_mode_injected(uint32_t adc);
-void adc_enable_automatic_injected_group_conversion(uint32_t adc);
-void adc_disable_automatic_injected_group_conversion(uint32_t adc);
-void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
-void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
-						    uint8_t channel);
-void adc_enable_scan_mode(uint32_t adc);
-void adc_disable_scan_mode(uint32_t adc);
-void adc_enable_eoc_interrupt_injected(uint32_t adc);
-void adc_disable_eoc_interrupt_injected(uint32_t adc);
-void adc_enable_awd_interrupt(uint32_t adc);
-void adc_disable_awd_interrupt(uint32_t adc);
-void adc_enable_eoc_interrupt(uint32_t adc);
-void adc_disable_eoc_interrupt(uint32_t adc);
-void adc_start_conversion_regular(uint32_t adc);
-void adc_start_conversion_injected(uint32_t adc);
-void adc_disable_external_trigger_regular(uint32_t adc);
-void adc_disable_external_trigger_injected(uint32_t adc);
-void adc_set_left_aligned(uint32_t adc);
-void adc_set_right_aligned(uint32_t adc);
-void adc_enable_dma(uint32_t adc);
-void adc_disable_dma(uint32_t adc);
-void adc_set_continuous_conversion_mode(uint32_t adc);
-void adc_set_single_conversion_mode(uint32_t adc);
-void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
-void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
-void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
-void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
-void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
-void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
-bool adc_eoc(uint32_t adc);
-bool adc_eoc_injected(uint32_t adc);
-uint32_t adc_read_regular(uint32_t adc);
-uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
-void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
-
 void adc_set_clk_prescale(uint32_t prescaler);
 void adc_set_multi_mode(uint32_t mode);
 void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
@@ -629,6 +577,7 @@ void adc_eoc_after_each(uint32_t adc);
 void adc_eoc_after_group(uint32_t adc);
 void adc_set_dma_continue(uint32_t adc);
 void adc_set_dma_terminate(uint32_t adc);
+
 void adc_enable_temperature_sensor(void);
 void adc_disable_temperature_sensor(void);
 
diff --git a/include/libopencm3/stm32/l1/adc.h b/include/libopencm3/stm32/l1/adc.h
index 2dabd9c6..3d4cecad 100644
--- a/include/libopencm3/stm32/l1/adc.h
+++ b/include/libopencm3/stm32/l1/adc.h
@@ -1,6 +1,7 @@
 /** @defgroup STM32L1xx_adc_defines ADC Defines
 
-@brief <b>Defined Constants and Types for the STM32L1xx Analog to Digital Converters</b>
+@brief <b>Defined Constants and Types for the STM32L1xx Analog to
+Digital Converters</b>
 
 @ingroup STM32L1xx_defines
 
@@ -119,6 +120,7 @@ LGPL License Terms @ref lgpl_license
 #define ADC_CR1_PDI			(1 << 17)
 #define ADC_CR1_PDD			(1 << 16)
 
+#define ADC_CR1_AWDCH_MAX		26
 
 /* --- ADC_CR2 values ------------------------------------------------------- */
 /* SWSTART: */ /** Start conversion of regular channels. */
@@ -156,7 +158,7 @@ LGPL License Terms @ref lgpl_license
 #define ADC_CR2_EXTSEL_TIM3_CC3		(8 << ADC_CR2_EXTSEL_SHIFT)
 #define ADC_CR2_EXTSEL_TIM4_TRGO	(9 << ADC_CR2_EXTSEL_SHIFT)
 #define ADC_CR2_EXTSEL_TIM6_TRGO	(10 << ADC_CR2_EXTSEL_SHIFT)
-// reserved....
+/* reserved.... */
 #define ADC_CR2_EXTSEL_EXTI11		(15 << ADC_CR2_EXTSEL_SHIFT)
 /**@}*/
 
@@ -175,13 +177,13 @@ LGPL License Terms @ref lgpl_license
 #define ADC_CR2_JEXTEN_BOTH_EDGES	(0x3 << ADC_CR2_JEXTEN_SHIFT)
 /**@}*/
 
-// FIXME - add the values here
+/* FIXME - add the values here */
 #define ADC_CR2_JEXTSEL_SHIFT		16
 #define ADC_CR2_JEXTSEL_MASK		(0xf << ADC_CR2_JEXTSEL_SHIFT)
 
 #define ADC_CR2_EOCS			(1 << 10)
 #define ADC_CR2_DDS			(1 << 9)
-// FIXME- add the values here
+/* FIXME- add the values here */
 #define ADC_CR2_DELS_SHIFT		4
 #define ADC_CR2_DELS_MASK		0x7
 
@@ -208,11 +210,18 @@ LGPL License Terms @ref lgpl_license
 /**@}*/
 
 #define ADC_SQR_MASK			0x1f
+#define ADC_SQR_MAX_CHANNELS_REGULAR	28 /* m+/h only, otherwise 27 */
 
 #define ADC_CCR_TSVREFE			(1 << 23)
 
 BEGIN_DECLS
-        // We will add these when we are ready...
+	/* L1 specific, or not fully unified adc routines */
+void adc_enable_temperature_sensor(void);
+void adc_disable_temperature_sensor(void);
+void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
+					 uint32_t polarity);
+void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
+					  uint32_t polarity);
 
 END_DECLS
 
diff --git a/lib/stm32/common/adc_common_v1.c b/lib/stm32/common/adc_common_v1.c
new file mode 100644
index 00000000..a4b92577
--- /dev/null
+++ b/lib/stm32/common/adc_common_v1.c
@@ -0,0 +1,755 @@
+/** @addtogroup adc_file
+
+@author @htmlonly &copy; @endhtmlonly
+2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+@author @htmlonly &copy; @endhtmlonly
+2012 Ken Sarkies <ksarkies@internode.on.net>
+@author @htmlonly &copy; @endhtmlonly
+2014 Karl Palsson <karlp@tweak.net.au>
+
+This library supports one style of the Analog to Digital Conversion System in
+the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
+
+The style of ADC Peripheral supported by this code is found in the F1, F2,
+F37x, F38x, F4, and L1 series devices (at the time of writing) but is quite
+different to the style found on the F0 and F30x and F31x.
+Devices can have up to three A/D converters each with their own set of
+registers.
+However all the A/D converters share a common clock.  On most devices, this is
+prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
+of 8, though on the L1 this is always a divider from the HSI. (And therefore HSI
+_must_ be enabled before attempting to enable the ADC)
+
+Each A/D converter has up to ADC_MAX_CHANNELS channels:
+@li On ADC1 the analog channels 16 and 17 are internally connected to the
+temperature sensor and V<sub>REFINT</sub>, respectively.
+@li On ADC2 (if available) the analog channels 16 and 17 are internally
+connected to V<sub>SS</sub>.
+@li On ADC3 (if available) the analog channels 9, 14, 15, 16 and 17 are
+internally connected to V<sub>SS</sub>.
+
+The conversions can occur as a one-off conversion whereby the process stops once
+conversion is complete. The conversions can also be continuous wherein a new
+conversion starts immediately the previous conversion has ended.
+
+Conversion can occur as a single channel conversion or a scan of a group of
+channels in either continuous or one-off mode. If more than one channel is
+converted in a scan group, DMA must be used to transfer the data as there is
+only one result register available. An interrupt can be set to occur at the end
+of conversion, which occurs after all channels have been scanned.
+
+A discontinuous mode allows a subgroup of group of a channels to be converted in
+bursts of a given length.
+
+Injected conversions allow a second group of channels to be converted separately
+from the regular group. An interrupt can be set to occur at the end of
+conversion, which occurs after all channels have been scanned.
+
+@section adc_api_ex Basic ADC Handling API.
+
+Example 1: Simple single channel conversion polled. Enable the peripheral clock
+and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
+(default). Enable triggering for a software trigger.
+
+@code
+    rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN);
+    adc_off(ADC1);
+    rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
+    rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST);
+    rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
+    adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
+    adc_disable_scan_mode(ADC1);
+    adc_set_single_conversion_mode(ADC1);
+    adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
+    adc_set_single_channel(ADC1, ADC_CHANNEL0);
+    adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
+    adc_power_on(ADC1);
+    adc_reset_calibration(ADC1);
+    adc_calibration(ADC1);
+    adc_start_conversion_regular(ADC1);
+    while (! adc_eoc(ADC1));
+    reg16 = adc_read_regular(ADC1);
+@endcode
+
+LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/adc.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Off
+
+Turn off the ADC to reduce power consumption to a few microamps.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_off(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_ADON;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Regular Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two
+threshold levels. The thresholds must be preset. Comparison is done before data
+alignment takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_enable_analog_watchdog_regular(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_AWDEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_disable_analog_watchdog_regular(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for Injected Conversions
+
+The analog watchdog allows the monitoring of an analog signal between two
+threshold levels. The thresholds must be preset. Comparison is done before data
+alignment takes place, so the thresholds are left-aligned.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_analog_watchdog_injected(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_JAWDEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_analog_watchdog_injected(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Regular Conversions
+
+In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
+defined regular channel group. The subgroup is defined by the number of
+consecutive channels to be converted. After a subgroup has been converted
+the next trigger will start conversion of the immediately following subgroup
+of the same length or until the whole group has all been converted. When the
+the whole group has been converted, the next trigger will restart conversion
+of the subgroup at the beginning of the whole group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group @ref
+adc_cr1_discnum
+*/
+
+void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
+{
+	if ((length-1) > 7) {
+		return;
+	}
+	ADC_CR1(adc) |= ADC_CR1_DISCEN;
+	ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Regular Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_regular(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Discontinuous Mode for Injected Conversions
+
+In this mode the ADC converts sequentially one channel of the defined group of
+injected channels, cycling back to the first channel in the group once the
+entire group has been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_discontinuous_mode_injected(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_JDISCEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Discontinuous Mode for Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_discontinuous_mode_injected(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Automatic Injected Conversions
+
+The ADC converts a defined injected group of channels immediately after the
+regular channels have been converted. The external trigger on the injected
+channels is disabled as required.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_automatic_injected_group_conversion(uint32_t adc)
+{
+	adc_disable_external_trigger_injected(adc);
+	ADC_CR1(adc) |= ADC_CR1_JAUTO;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Automatic Injected Conversions
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_automatic_injected_group_conversion(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
+
+The analog watchdog allows the monitoring of an analog signal between two
+threshold levels. The thresholds must be preset. Comparison is done before data
+alignment takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled.
+@ref adc_enable_analog_watchdog_injected, @ref
+adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog for a Selected Channel
+
+The analog watchdog allows the monitoring of an analog signal between two
+threshold levels. The thresholds must be preset. Comparison is done before data
+alignment takes place, so the thresholds are left-aligned.
+
+@note The analog watchdog must be enabled for either or both of the regular or
+injected channels. If neither are enabled, the analog watchdog feature will be
+disabled. If both are enabled, the same channel number is monitored.
+@ref adc_enable_analog_watchdog_injected, @ref
+adc_enable_analog_watchdog_regular.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
+*/
+
+void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
+						    uint8_t channel)
+{
+	uint32_t reg32;
+
+	reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
+	if (channel <= ADC_CR1_AWDCH_MAX) {
+		reg32 |= channel;
+	}
+	ADC_CR1(adc) = reg32;
+	ADC_CR1(adc) |= ADC_CR1_AWDSGL;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set Scan Mode
+
+In this mode a conversion consists of a scan of the predefined set of channels,
+regular and injected, each channel conversion immediately following the
+previous one. It can use single, continuous or discontinuous mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_scan_mode(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_SCAN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Scan Mode
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_scan_mode(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_SCAN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_eoc_interrupt_injected(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_JEOCIE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Injected End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_eoc_interrupt_injected(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_awd_interrupt(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_AWDIE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Analog Watchdog Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_awd_interrupt(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_eoc_interrupt(uint32_t adc)
+{
+	ADC_CR1(adc) |= ADC_CR1_EOCIE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable Regular End-Of-Conversion Interrupt
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_eoc_interrupt(uint32_t adc)
+{
+	ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Left Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_set_left_aligned(uint32_t adc)
+{
+	ADC_CR2(adc) |= ADC_CR2_ALIGN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set the Data as Right Aligned
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_set_right_aligned(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag
+
+This flag is set after all channels of a regular or injected group have been
+converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc(uint32_t adc)
+{
+	return (ADC_SR(adc) & ADC_SR_EOC) != 0;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
+
+This flag is set after all channels of an injected group have been converted.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns bool. End of conversion flag.
+*/
+
+bool adc_eoc_injected(uint32_t adc)
+{
+	return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Read from the Regular Conversion Result Register
+
+The result read back is 12 bits, right or left aligned within the first 16 bits.
+For ADC1 only, the higher 16 bits will hold the result from ADC2 if
+an appropriate dual mode has been set @see adc_set_dual_mode.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@returns Unsigned int32 conversion result.
+*/
+
+uint32_t adc_read_regular(uint32_t adc)
+{
+	return ADC_DR(adc);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Read from an Injected Conversion Result Register
+
+The result read back from the selected injected result register (one of four)
+is 12 bits, right or left aligned within the first 16 bits. The result can have
+a negative value if the injected channel offset has been set @see
+adc_set_injected_offset.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@returns Unsigned int32 conversion result.
+*/
+
+uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
+{
+	switch (reg) {
+	case 1:
+		return ADC_JDR1(adc);
+	case 2:
+		return ADC_JDR2(adc);
+	case 3:
+		return ADC_JDR3(adc);
+	case 4:
+		return ADC_JDR4(adc);
+	}
+	return 0;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Continuous Conversion Mode
+
+In this mode the ADC starts a new conversion of a single channel or a channel
+group immediately following completion of the previous channel group conversion.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_set_continuous_conversion_mode(uint32_t adc)
+{
+	ADC_CR2(adc) |= ADC_CR2_CONT;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable Single Conversion Mode
+
+In this mode the ADC performs a conversion of one channel or a channel group
+and stops.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_set_single_conversion_mode(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_CONT;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Upper Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Upper threshold value
+*/
+
+void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
+{
+	uint32_t reg32 = 0;
+
+	reg32 = (uint32_t)threshold;
+	reg32 &= ADC_HT_MSK;
+	ADC_HTR(adc) = reg32;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set Analog Watchdog Lower Threshold
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] threshold Unsigned int8. Lower threshold value
+*/
+
+void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
+{
+	uint32_t reg32 = 0;
+
+	reg32 = (uint32_t)threshold;
+	reg32 &= ADC_LT_MSK;
+	ADC_LTR(adc) = reg32;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/** @brief ADC Set a Regular Channel Conversion Sequence
+
+Define a sequence of channels to be converted as a regular group with a length
+from 1 to ADC_REGULAR_SEQUENCE_MAX channels. If this is called during
+conversion, the current conversion is reset and conversion begins again with
+the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..31.
+ */
+
+void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
+{
+	uint32_t fifth6 = 0;
+	uint32_t fourth6 = 0;
+	uint32_t third6 = 0;
+	uint32_t second6 = 0;
+	uint32_t first6 = 0;
+	uint8_t i = 0;
+
+	if (length > ADC_SQR_MAX_CHANNELS_REGULAR) {
+		return;
+	}
+
+	for (i = 1; i <= length; i++) {
+		if (i <= 6) {
+			first6 |= (channel[i - 1] << ((i - 1) * 5));
+		}
+		if ((i > 6) & (i <= 12)) {
+			second6 |= (channel[i - 1] << ((i - 6 - 1) * 5));
+		}
+		if ((i > 12) & (i <= 18)) {
+			third6 |= (channel[i - 1] << ((i - 12 - 1) * 5));
+		}
+		if ((i > 18) & (i <= 24)) {
+			fourth6 |= (channel[i - 1] << ((i - 18 - 1) * 5));
+		}
+		if ((i > 24) & (i <= 28)) {
+			fifth6 |= (channel[i - 1] << ((i - 24 - 1) * 5));
+		}
+	}
+#if defined(ADC_SQR5)
+	ADC_SQR1(adc) = fifth6 | ((length - 1) << ADC_SQR1_L_LSB);
+	ADC_SQR2(adc) = fourth6;
+	ADC_SQR3(adc) = third6;
+	ADC_SQR4(adc) = second6;
+	ADC_SQR5(adc) = first6;
+#else
+	ADC_SQR1(adc) = third6 | ((length - 1) << ADC_SQR1_L_LSB);
+	ADC_SQR2(adc) = second6;
+	ADC_SQR3(adc) = first6;
+#endif
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set an Injected Channel Conversion Sequence
+
+Defines a sequence of channels to be converted as an injected group with a
+length from 1 to 4 channels. If this is called during conversion, the current
+conversion is reset and conversion begins again with the newly defined group.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] length Unsigned int8. Number of channels in the group.
+@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
+*/
+
+void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
+{
+	uint32_t reg32 = 0;
+	uint8_t i = 0;
+
+	/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
+	if ((length - 1) > 3) {
+		return;
+	}
+
+	for (i = 0; i < length; i++) {
+		reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
+	}
+
+	reg32 |= ADC_JSQR_JL_VAL(length);
+
+	ADC_JSQR(adc) = reg32;
+}
+
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Set the Injected Channel Data Offset
+
+This value is subtracted from the injected channel results after conversion is
+complete, and can result in negative results. A separate value can be specified
+for each injected data register.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] reg Unsigned int8. Register number (1 ... 4).
+@param[in] offset Unsigned int32.
+*/
+
+void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
+{
+	switch (reg) {
+	case 1:
+		ADC_JOFR1(adc) = offset;
+		break;
+	case 2:
+		ADC_JOFR2(adc) = offset;
+		break;
+	case 3:
+		ADC_JOFR3(adc) = offset;
+		break;
+	case 4:
+		ADC_JOFR4(adc) = offset;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Regular Channels
+
+This starts conversion on a set of defined regular channels if the ADC trigger
+is set to be a software trigger. It is cleared by hardware once conversion
+starts.
+
+Special F1 Note this is a software trigger and requires triggering to be
+enabled and the trigger source to be set appropriately otherwise conversion
+will not start. This is not the same as the ADC start conversion operation.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_start_conversion_regular(uint32_t adc)
+{
+	/* Start conversion on regular channels. */
+	ADC_CR2(adc) |= ADC_CR2_SWSTART;
+
+	/* Wait until the ADC starts the conversion. */
+	while (ADC_CR2(adc) & ADC_CR2_SWSTART);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Software Triggered Conversion on Injected Channels
+
+This starts conversion on a set of defined injected channels if the ADC trigger
+is set to be a software trigger. It is cleared by hardware once conversion
+starts.
+
+Special F1 Note this is a software trigger and requires triggering to be
+enabled and the trigger source to be set appropriately otherwise conversion
+will not start. This is not the same as the ADC start conversion operation.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref
+adc_reg_base.
+*/
+
+void adc_start_conversion_injected(uint32_t adc)
+{
+	/* Start conversion on injected channels. */
+	ADC_CR2(adc) |= ADC_CR2_JSWSTART;
+
+	/* Wait until the ADC starts the conversion. */
+	while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable DMA Transfers
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_enable_dma(uint32_t adc)
+{
+	ADC_CR2(adc) |= ADC_CR2_DMA;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Disable DMA Transfers
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_dma(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_DMA;
+}
+
+
+
+/**@}*/
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 032b46a2..fb813485 100644
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -33,7 +33,7 @@ CFLAGS		= -Os -g \
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= adc.o can.o desig.o ethernet.o flash.o gpio.o \
+OBJS		= adc.o adc_common_v1.o can.o desig.o ethernet.o flash.o gpio.o \
                   rcc.o rtc.o timer.o
 
 OBJS            += crc_common_all.o dac_common_all.o dma_common_l1f013.o \
diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c
index d9ed99e5..af572522 100644
--- a/lib/stm32/f1/adc.c
+++ b/lib/stm32/f1/adc.c
@@ -118,6 +118,7 @@ LGPL License Terms @ref lgpl_license
 If the ADC is in power-down mode then it is powered up. The application needs
 to wait a time of about 3 microseconds for stabilization before using the ADC.
 If the ADC is already on this function call has no effect.
+ * NOTE Common with F37x
 
 @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
 */
@@ -191,416 +192,7 @@ void adc_set_dual_mode(uint32_t mode)
 	ADC1_CR1 |= mode;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read the End-of-Conversion Flag
 
-This flag is set after all channels of a regular or injected group have been
-converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@returns bool. End of conversion flag.
-*/
-
-bool adc_eoc(uint32_t adc)
-{
-	return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
-
-This flag is set after all channels of an injected group have been converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@returns bool. End of conversion flag.
-*/
-
-bool adc_eoc_injected(uint32_t adc)
-{
-	return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read from the Regular Conversion Result Register
-
-The result read back is 12 bits, right or left aligned within the first 16 bits.
-For ADC1 only, the higher 16 bits will hold the result from ADC2 if
-an appropriate dual mode has been set @see adc_set_dual_mode.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@returns Unsigned int32 conversion result.
-*/
-
-uint32_t adc_read_regular(uint32_t adc)
-{
-	return ADC_DR(adc);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read from an Injected Conversion Result Register
-
-The result read back from the selected injected result register (one of four)
-is 12 bits, right or left aligned within the first 16 bits. The result can have
-a negative value if the injected channel offset has been set @see
-adc_set_injected_offset.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] reg Unsigned int8. Register number (1 ... 4).
-@returns Unsigned int32 conversion result.
-*/
-
-uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
-{
-	switch (reg) {
-	case 1:
-		return ADC_JDR1(adc);
-	case 2:
-		return ADC_JDR2(adc);
-	case 3:
-		return ADC_JDR3(adc);
-	case 4:
-		return ADC_JDR4(adc);
-	}
-	return 0;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Injected Channel Data Offset
-
-This value is subtracted from the injected channel results after conversion is
-complete, and can result in negative results. A separate value can be specified
-for each injected data register.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] reg Unsigned int8. Register number (1 ... 4).
-@param[in] offset Unsigned int32.
-*/
-
-void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
-{
-	switch (reg) {
-	case 1:
-		ADC_JOFR1(adc) = offset;
-		break;
-	case 2:
-		ADC_JOFR2(adc) = offset;
-		break;
-	case 3:
-		ADC_JOFR3(adc) = offset;
-		break;
-	case 4:
-		ADC_JOFR4(adc) = offset;
-		break;
-	}
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for Regular Conversions
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_analog_watchdog_regular(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_AWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog for Regular Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_analog_watchdog_regular(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for Injected Conversions
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_analog_watchdog_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JAWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog for Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_analog_watchdog_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Discontinuous Mode for Regular Conversions
-
-In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
-defined regular channel group. The subgroup is defined by the number of
-consecutive channels to be converted. After a subgroup has been converted
-the next trigger will start conversion of the immediately following subgroup
-of the same length or until the whole group has all been converted. When the
-the whole group has been converted, the next trigger will restart conversion
-of the subgroup at the beginning of the whole group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] length Unsigned int8. Number of channels in the group @ref
-adc_cr1_discnum.
-*/
-
-void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
-{
-	if ((length-1) > 7) {
-		return;
-	}
-	ADC_CR1(adc) |= ADC_CR1_DISCEN;
-	ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Discontinuous Mode for Regular Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_discontinuous_mode_regular(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Discontinuous Mode for Injected Conversions
-
-In this mode the ADC converts sequentially one channel of the defined group of
-injected channels, cycling back to the first channel in the group once the
-entire group has been converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_discontinuous_mode_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JDISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Discontinuous Mode for Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_discontinuous_mode_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Automatic Injected Conversions
-
-The ADC converts a defined injected group of channels immediately after the
-regular channels have been converted. The external trigger on the injected
-channels is disabled as required.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base
-*/
-
-void adc_enable_automatic_injected_group_conversion(uint32_t adc)
-{
-	adc_disable_external_trigger_injected(adc);
-	ADC_CR1(adc) |= ADC_CR1_JAUTO;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Automatic Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_automatic_injected_group_conversion(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@note The analog watchdog must be enabled for either or both of the regular or
-injected channels. If neither are enabled, the analog watchdog feature will be
-disabled.
-@ref adc_enable_analog_watchdog_injected, @ref
-adc_enable_analog_watchdog_regular.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for a Selected Channel
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@note The analog watchdog must be enabled for either or both of the regular or
-injected channels. If neither are enabled, the analog watchdog feature will be
-disabled. If both are enabled, the same channel number is monitored.
-@ref adc_enable_analog_watchdog_injected, @ref
-adc_enable_analog_watchdog_regular.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
-*/
-
-void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
-						    uint8_t channel)
-{
-	uint32_t reg32;
-
-	reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */
-	if (channel < 18) {
-		reg32 |= channel;
-	}
-	ADC_CR1(adc) = reg32;
-	ADC_CR1(adc) |= ADC_CR1_AWDSGL;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set Scan Mode
-
-In this mode a conversion consists of a scan of the predefined set of channels,
-regular and injected, each channel conversion immediately following the
-previous one. It can use single, continuous or discontinuous mode.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_scan_mode(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_SCAN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Scan Mode
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_scan_mode(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_SCAN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Injected End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_eoc_interrupt_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JEOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Injected End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_eoc_interrupt_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_awd_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_AWDIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_awd_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Regular End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_eoc_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_EOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Regular End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_eoc_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
-}
 
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Enable The Temperature Sensor
@@ -632,53 +224,6 @@ void adc_disable_temperature_sensor(uint32_t adc)
 	ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Software Triggered Conversion on Regular Channels
-
-This starts conversion on a set of defined regular channels if the ADC trigger
-is set to be a software trigger. It is cleared by hardware once conversion
-starts.
-
-Note this is a software trigger and requires triggering to be enabled and the
-trigger source to be set appropriately otherwise conversion will not start.
-This is not the same as the ADC start conversion operation.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_start_conversion_regular(uint32_t adc)
-{
-	/* Start conversion on regular channels. */
-	ADC_CR2(adc) |= ADC_CR2_SWSTART;
-
-	/* Wait until the ADC starts the conversion. */
-	while (ADC_CR2(adc) & ADC_CR2_SWSTART);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Software Triggered Conversion on Injected Channels
-
-This starts conversion on a set of defined injected channels if the ADC trigger
-is set to be a software trigger. It is cleared by hardware once conversion
-starts.
-
-Note this is a software trigger and requires triggering to be enabled and the
-trigger source to be set appropriately otherwise conversion will not start.
-This is not the same as the ADC start conversion operation.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_start_conversion_injected(uint32_t adc)
-{
-	/* Start conversion on injected channels. */
-	ADC_CR2(adc) |= ADC_CR2_JSWSTART;
-
-	/* Wait until the ADC starts the conversion. */
-	while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
-}
 
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Enable an External Trigger for Regular Channels
@@ -787,62 +332,6 @@ void adc_disable_external_trigger_injected(uint32_t adc)
 	ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Data as Left Aligned
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_set_left_aligned(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_ALIGN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Data as Right Aligned
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_set_right_aligned(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable DMA Transfers
-
-Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5.
-ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer
-mode.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_enable_dma(uint32_t adc)
-{
-	if ((adc == ADC1) | (adc == ADC3)) {
-		ADC_CR2(adc) |= ADC_CR2_DMA;
-	}
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable DMA Transfers
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_disable_dma(uint32_t adc)
-{
-	if ((adc == ADC1) | (adc == ADC3)) {
-		ADC_CR2(adc) &= ~ADC_CR2_DMA;
-	}
-}
-
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Initialize Calibration Registers
 
@@ -879,36 +368,6 @@ void adc_calibration(uint32_t adc)
 	while (ADC_CR2(adc) & ADC_CR2_CAL);
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Continuous Conversion Mode
-
-In this mode the ADC starts a new conversion of a single channel or a channel
-group immediately following completion of the previous channel group conversion.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_set_continuous_conversion_mode(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_CONT;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Single Conversion Mode
-
-In this mode the ADC performs a conversion of one channel or a channel group
-and stops.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_set_single_conversion_mode(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_CONT;
-}
-
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Power On
 
@@ -927,19 +386,6 @@ void adc_on(uint32_t adc)
 	ADC_CR2(adc) |= ADC_CR2_ADON;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Off
-
-Turn off the ADC to reduce power consumption to a few microamps.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-*/
-
-void adc_off(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_ADON;
-}
 
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Set the Sample Time for a Single Channel
@@ -951,6 +397,7 @@ adc_reg_base.
 @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
 adc_channel.
 @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
+ *  * NOTE Common with f2 and f37x and f4
 */
 
 void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
@@ -979,6 +426,7 @@ for all channels.
 @param[in] adc Unsigned int32. ADC block register address base @ref
 adc_reg_base.
 @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
+ *  * NOTE Common with f2 and f37x and f4
 */
 
 void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
@@ -997,130 +445,8 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
 	ADC_SMPR1(adc) = reg32;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set Analog Watchdog Upper Threshold
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] threshold Unsigned int8. Upper threshold value.
-*/
-
-void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
-{
-	uint32_t reg32 = 0;
-
-	reg32 = (uint32_t)threshold;
-	reg32 &= ~0xfffff000; /* Clear all bits above 11. */
-	ADC_HTR(adc) = reg32;
-}
 
 /*---------------------------------------------------------------------------*/
-/** @brief ADC Set Analog Watchdog Lower Threshold
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] threshold Unsigned int8. Lower threshold value.
-*/
-
-void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
-{
-	uint32_t reg32 = 0;
-
-	reg32 = (uint32_t)threshold;
-	reg32 &= ~0xfffff000; /* Clear all bits above 11. */
-	ADC_LTR(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set a Regular Channel Conversion Sequence
-
-Define a sequence of channels to be converted as a regular group with a length
-from 1 to 16 channels. If this is called during conversion, the current
-conversion is reset and conversion begins again with the newly defined group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] length Unsigned int8. Number of channels in the group.
-@param[in] channel Unsigned int8[]. Set of channels in sequence, integers
-0..18.
-*/
-
-void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
-{
-	uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
-	uint8_t i = 0;
-
-	/* Maximum sequence length is 16 channels. */
-	if (length > 16) {
-		return;
-	}
-
-	for (i = 1; i <= length; i++) {
-		if (i <= 6) {
-			reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
-		}
-		if ((i > 6) & (i <= 12)) {
-			reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
-		}
-		if ((i > 12) & (i <= 16)) {
-			reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
-		}
-	}
-	reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
-
-	ADC_SQR1(adc) = reg32_1;
-	ADC_SQR2(adc) = reg32_2;
-	ADC_SQR3(adc) = reg32_3;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set an Injected Channel Conversion Sequence
-
-Defines a sequence of channels to be converted as an injected group with a
-length from 1 to 4 channels. If this is called during conversion, the current
-conversion is reset and conversion begins again with the newly defined group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref
-adc_reg_base.
-@param[in] length Unsigned int8. Number of channels in the group.
-@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
-*/
-
-void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
-{
-	uint32_t reg32 = 0;
-	uint8_t i = 0;
-
-	/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
-	if ((length - 1) > 3) {
-		return;
-	}
-
-	for (i = 0; i < length; i++) {
-		reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
-	}
-
-	reg32 |= ADC_JSQR_JL_VAL(length);
-
-	ADC_JSQR(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-
-/* Aliases */
-
-#ifdef __GNUC__
-void adc_set_continous_conversion_mode(uint32_t adc)
-	__attribute__((alias("adc_set_continuous_conversion_mode")));
-void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
-	__attribute__((alias("adc_set_sample_time")));
-void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
-	__attribute__((alias("adc_set_sample_time_on_all_channels")));
-void adc_enable_jeoc_interrupt(uint32_t adc)
-	__attribute__((alias("adc_enable_eoc_interrupt_injected")));
-void adc_disable_jeoc_interrupt(uint32_t adc)
-	__attribute__((alias("adc_disable_eoc_interrupt_injected")));
-#endif
 
 /**@}*/
 
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index a21bbf9f..8f96e5fb 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -36,7 +36,7 @@ CFLAGS		= -Os -g \
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= adc.o can.o gpio.o pwr.o rcc.o rtc.o crypto.o
+OBJS		= adc.o adc_common_v1.o can.o gpio.o pwr.o rcc.o rtc.o crypto.o
 
 OBJS            += crc_common_all.o dac_common_all.o dma_common_f24.o \
                    gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \
diff --git a/lib/stm32/f4/adc.c b/lib/stm32/f4/adc.c
index 95cc4ae0..d03e70cf 100644
--- a/lib/stm32/f4/adc.c
+++ b/lib/stm32/f4/adc.c
@@ -86,411 +86,6 @@ LGPL License Terms @ref lgpl_license
 
 /**@{*/
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Off
-
-Turn off the ADC to reduce power consumption to a few microamps.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_off(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_ADON;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for Regular Conversions
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_analog_watchdog_regular(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_AWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog for Regular Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_analog_watchdog_regular(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for Injected Conversions
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_analog_watchdog_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JAWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog for Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_analog_watchdog_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Discontinuous Mode for Regular Conversions
-
-In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
-defined regular channel group. The subgroup is defined by the number of
-consecutive channels to be converted. After a subgroup has been converted
-the next trigger will start conversion of the immediately following subgroup
-of the same length or until the whole group has all been converted. When the
-the whole group has been converted, the next trigger will restart conversion
-of the subgroup at the beginning of the whole group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] length Unsigned int8. Number of channels in the group @ref
-adc_cr1_discnum
-*/
-
-void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
-{
-	if ((length-1) > 7) {
-		return;
-	}
-	ADC_CR1(adc) |= ADC_CR1_DISCEN;
-	ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Discontinuous Mode for Regular Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_discontinuous_mode_regular(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Discontinuous Mode for Injected Conversions
-
-In this mode the ADC converts sequentially one channel of the defined group of
-injected channels, cycling back to the first channel in the group once the
-entire group has been converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_discontinuous_mode_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JDISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Discontinuous Mode for Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_discontinuous_mode_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Automatic Injected Conversions
-
-The ADC converts a defined injected group of channels immediately after the
-regular channels have been converted. The external trigger on the injected
-channels is disabled as required.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_automatic_injected_group_conversion(uint32_t adc)
-{
-	adc_disable_external_trigger_injected(adc);
-	ADC_CR1(adc) |= ADC_CR1_JAUTO;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Automatic Injected Conversions
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_automatic_injected_group_conversion(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@note The analog watchdog must be enabled for either or both of the regular or
-injected channels. If neither are enabled, the analog watchdog feature will be
-disabled.
-@ref adc_enable_analog_watchdog_injected, @ref
-adc_enable_analog_watchdog_regular.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog for a Selected Channel
-
-The analog watchdog allows the monitoring of an analog signal between two
-threshold levels. The thresholds must be preset. Comparison is done before data
-alignment takes place, so the thresholds are left-aligned.
-
-@note The analog watchdog must be enabled for either or both of the regular or
-injected channels. If neither are enabled, the analog watchdog feature will be
-disabled. If both are enabled, the same channel number is monitored.
-@ref adc_enable_analog_watchdog_injected, @ref
-adc_enable_analog_watchdog_regular.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
-*/
-
-void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
-						    uint8_t channel)
-{
-	uint32_t reg32;
-
-	reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
-	if (channel < 18) {
-		reg32 |= channel;
-	}
-	ADC_CR1(adc) = reg32;
-	ADC_CR1(adc) |= ADC_CR1_AWDSGL;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set Scan Mode
-
-In this mode a conversion consists of a scan of the predefined set of channels,
-regular and injected, each channel conversion immediately following the
-previous one. It can use single, continuous or discontinuous mode.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_scan_mode(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_SCAN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Scan Mode
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_scan_mode(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_SCAN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Injected End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_eoc_interrupt_injected(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_JEOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Injected End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_eoc_interrupt_injected(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Analog Watchdog Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_awd_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_AWDIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Analog Watchdog Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_awd_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Regular End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_eoc_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) |= ADC_CR1_EOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable Regular End-Of-Conversion Interrupt
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_eoc_interrupt(uint32_t adc)
-{
-	ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Software Triggered Conversion on Regular Channels
-
-This starts conversion on a set of defined regular channels. It is cleared by
-hardware once conversion starts.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_start_conversion_regular(uint32_t adc)
-{
-	/* Start conversion on regular channels. */
-	ADC_CR2(adc) |= ADC_CR2_SWSTART;
-
-	/* Wait until the ADC starts the conversion. */
-	while (ADC_CR2(adc) & ADC_CR2_SWSTART);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Software Triggered Conversion on Injected Channels
-
-This starts conversion on a set of defined injected channels. It is cleared by
-hardware once conversion starts.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_start_conversion_injected(uint32_t adc)
-{
-	/* Start conversion on injected channels. */
-	ADC_CR2(adc) |= ADC_CR2_JSWSTART;
-
-	/* Wait until the ADC starts the conversion. */
-	while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Data as Left Aligned
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_set_left_aligned(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_ALIGN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Data as Right Aligned
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_set_right_aligned(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable DMA Transfers
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_enable_dma(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_DMA;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Disable DMA Transfers
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_dma(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_DMA;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Continuous Conversion Mode
-
-In this mode the ADC starts a new conversion of a single channel or a channel
-group immediately following completion of the previous channel group conversion.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_set_continuous_conversion_mode(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_CONT;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable Single Conversion Mode
-
-In this mode the ADC performs a conversion of one channel or a channel group
-and stops.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_set_single_conversion_mode(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_CONT;
-}
-
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Set the Sample Time for a Single Channel
 
@@ -500,6 +95,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
 @param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
 adc_channel
 @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+ * NOTE Common with f1, f2 and f37x
 */
 
 void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
@@ -527,6 +123,7 @@ for all channels.
 
 @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
 @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+ * NOTE Common with f1, f2 and f37x
 */
 
 void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
@@ -545,218 +142,13 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
 	ADC_SMPR1(adc) = reg32;
 }
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set Analog Watchdog Upper Threshold
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] threshold Unsigned int8. Upper threshold value
-*/
-
-void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
-{
-	uint32_t reg32 = 0;
-
-	reg32 = (uint32_t)threshold;
-	reg32 &= ~0xfffff000; /* Clear all bits above 11. */
-	ADC_HTR(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set Analog Watchdog Lower Threshold
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] threshold Unsigned int8. Lower threshold value
-*/
-
-void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
-{
-	uint32_t reg32 = 0;
-
-	reg32 = (uint32_t)threshold;
-	reg32 &= ~0xfffff000; /* Clear all bits above 11. */
-	ADC_LTR(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set a Regular Channel Conversion Sequence
-
-Define a sequence of channels to be converted as a regular group with a length
-from 1 to 16 channels. If this is called during conversion, the current
-conversion is reset and conversion begins again with the newly defined group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] length Unsigned int8. Number of channels in the group.
-@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
-*/
-
-void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
-{
-	uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
-	uint8_t i = 0;
-
-	/* Maximum sequence length is 16 channels. */
-	if (length > 16) {
-		return;
-	}
-
-	for (i = 1; i <= length; i++) {
-		if (i <= 6) {
-			reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
-		}
-		if ((i > 6) & (i <= 12)) {
-			reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
-		}
-		if ((i > 12) & (i <= 16)) {
-			reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
-		}
-	}
-	reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
-
-	ADC_SQR1(adc) = reg32_1;
-	ADC_SQR2(adc) = reg32_2;
-	ADC_SQR3(adc) = reg32_3;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set an Injected Channel Conversion Sequence
-
-Defines a sequence of channels to be converted as an injected group with a
-length from 1 to 4 channels. If this is called during conversion, the current
-conversion is reset and conversion begins again with the newly defined group.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] length Unsigned int8. Number of channels in the group.
-@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
-*/
-
-void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
-{
-	uint32_t reg32 = 0;
-	uint8_t i = 0;
-
-	/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
-	if ((length - 1) > 3) {
-		return;
-	}
-
-	for (i = 0; i < length; i++) {
-		reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
-	}
-
-	reg32 |= ADC_JSQR_JL_VAL(length);
-
-	ADC_JSQR(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read the End-of-Conversion Flag
-
-This flag is set after all channels of a regular or injected group have been
-converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@returns bool. End of conversion flag.
-*/
-
-bool adc_eoc(uint32_t adc)
-{
-	return (ADC_SR(adc) & ADC_SR_EOC) != 0;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
-
-This flag is set after all channels of an injected group have been converted.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@returns bool. End of conversion flag.
-*/
-
-bool adc_eoc_injected(uint32_t adc)
-{
-	return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read from the Regular Conversion Result Register
-
-The result read back is 12 bits, right or left aligned within the first 16 bits.
-For ADC1 only, the higher 16 bits will hold the result from ADC2 if
-an appropriate dual mode has been set @see adc_set_dual_mode.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@returns Unsigned int32 conversion result.
-*/
-
-uint32_t adc_read_regular(uint32_t adc)
-{
-	return ADC_DR(adc);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Read from an Injected Conversion Result Register
-
-The result read back from the selected injected result register (one of four)
-is 12 bits, right or left aligned within the first 16 bits. The result can have
-a negative value if the injected channel offset has been set @see
-adc_set_injected_offset.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] reg Unsigned int8. Register number (1 ... 4).
-@returns Unsigned int32 conversion result.
-*/
-
-uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
-{
-	switch (reg) {
-	case 1:
-		return ADC_JDR1(adc);
-	case 2:
-		return ADC_JDR2(adc);
-	case 3:
-		return ADC_JDR3(adc);
-	case 4:
-		return ADC_JDR4(adc);
-	}
-	return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-/** @brief ADC Set the Injected Channel Data Offset
-
-This value is subtracted from the injected channel results after conversion is
-complete, and can result in negative results. A separate value can be specified
-for each injected data register.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] reg Unsigned int8. Register number (1 ... 4).
-@param[in] offset Unsigned int32.
-*/
-
-void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
-{
-	switch (reg) {
-	case 1:
-		ADC_JOFR1(adc) = offset;
-		break;
-	case 2:
-		ADC_JOFR2(adc) = offset;
-		break;
-	case 3:
-		ADC_JOFR3(adc) = offset;
-		break;
-	case 4:
-		ADC_JOFR4(adc) = offset;
-		break;
-	}
-}
-
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Power On
 
 If the ADC is in power-down mode then it is powered up. The application needs
 to wait a time of about 3 microseconds for stabilization before using the ADC.
 If the ADC is already on this function call will have no effect.
+ * NOTE Common with L1 and F2
 
 @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
 */
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index bb39cfcd..85c54746 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -43,6 +43,7 @@ OBJS		+= usart_common_all.o usart_common_f124.o
 OBJS		+= exti_common_all.o
 OBJS		+= rcc_common_all.o
 OBJS		+= usb.o usb_control.o usb_standard.o usb_f103.o
+OBJS		+= adc.o adc_common_v1.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/l1/adc.c b/lib/stm32/l1/adc.c
new file mode 100644
index 00000000..fd025b6b
--- /dev/null
+++ b/lib/stm32/l1/adc.c
@@ -0,0 +1,201 @@
+/** @defgroup STM32L1xx_adc_file ADC
+
+@ingroup STM32L1xx
+
+@brief <b>libopencm3 STM32L1xx Analog to Digital Converters</b>
+
+@author @htmlonly &copy; @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au>
+
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/l1/adc.h>
+
+/**@{*/
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Power On
+
+If the ADC is in power-down mode then it is powered up. The application needs
+to wait a time of about 3 microseconds for stabilization before using the ADC.
+If the ADC is already on this function call will have no effect.
+ * NOTE Common with F4 and F2
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_power_on(uint32_t adc)
+{
+	ADC_CR2(adc) |= ADC_CR2_ADON;
+}
+
+
+/*----------------------------------------------------------------------------*/
+
+/** @brief ADC Set the Sample Time for a Single Channel
+
+The sampling time can be selected in ADC clock cycles from 4 to 384.
+
+@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
+@param[in] channel uint8. ADC Channel integer 0..18 or from @ref adc_channel.
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
+ */
+void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
+{
+	uint32_t reg32;
+
+	if (channel < 10) {
+		reg32 = ADC_SMPR3(adc);
+		reg32 &= ~(0x7 << (channel * 3));
+		reg32 |= (time << (channel * 3));
+		ADC_SMPR3(adc) = reg32;
+	} else if (channel < 20) {
+		reg32 = ADC_SMPR2(adc);
+		reg32 &= ~(0x7 << ((channel - 10) * 3));
+		reg32 |= (time << ((channel - 10) * 3));
+		ADC_SMPR2(adc) = reg32;
+	} else {
+		reg32 = ADC_SMPR1(adc);
+		reg32 &= ~(0x7 << ((channel - 20) * 3));
+		reg32 |= (time << ((channel - 20) * 3));
+		ADC_SMPR1(adc) = reg32;
+	}
+}
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for All Channels
+
+The sampling time can be selected in ADC clock cycles, same for
+all channels.
+
+@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
+*/
+
+void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
+{
+	uint8_t i;
+	uint32_t reg32 = 0;
+
+	for (i = 0; i <= 9; i++) {
+		reg32 |= (time << (i * 3));
+	}
+	ADC_SMPR0(adc) = reg32;
+	ADC_SMPR1(adc) = reg32;
+	ADC_SMPR2(adc) = reg32;
+	ADC_SMPR3(adc) = reg32;
+}
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Enable The Temperature Sensor
+
+This enables both the sensor and the reference voltage measurements on channels
+16 and 17.
+
+*/
+void adc_enable_temperature_sensor()
+{
+	ADC_CCR |= ADC_CCR_TSVREFE;
+}
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Disable The Temperature Sensor
+
+Disabling this will reduce power consumption from the sensor and the reference
+voltage measurements.
+
+*/
+void adc_disable_temperature_sensor()
+{
+	ADC_CCR &= ~ADC_CCR_TSVREFE;
+}
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Regular Channels
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+*/
+
+void adc_disable_external_trigger_regular(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
+}
+
+/*----------------------------------------------------------------------------*/
+/** @brief ADC Disable an External Trigger for Injected Channels
+
+@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
+*/
+
+void adc_disable_external_trigger_injected(uint32_t adc)
+{
+	ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Regular Channels
+
+This enables an external trigger for set of defined regular channels, and sets
+the polarity of the trigger event: rising or falling edge or both. Note that if
+the trigger polarity is zero, triggering is disabled.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular
+@param[in] polarity Unsigned int32. Trigger polarity @ref
+adc_trigger_polarity_regular
+*/
+
+void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
+					 uint32_t polarity)
+{
+	uint32_t reg32 = ADC_CR2(adc);
+
+	reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK);
+	reg32 |= (trigger | polarity);
+	ADC_CR2(adc) = reg32;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Enable an External Trigger for Injected Channels
+
+This enables an external trigger for set of defined injected channels, and sets
+the polarity of the trigger event: rising or falling edge or both.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected
+@param[in] polarity Unsigned int32. Trigger polarity @ref
+adc_trigger_polarity_injected
+*/
+
+void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
+					  uint32_t polarity)
+{
+	uint32_t reg32 = ADC_CR2(adc);
+
+	reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK);
+	reg32 |= (trigger | polarity);
+	ADC_CR2(adc) = reg32;
+}
+
+/**@}*/
+
+