From 3be6cd8f76739dde0f837c64adb83ec6bbc1f00b Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sat, 7 Apr 2012 09:01:39 +1200
Subject: [PATCH 01/13] Corrected bit definitions for capture/compare input
 selection.

Thanks to Linux Casassa.
---
 include/libopencm3/stm32/timer.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index c10d0159..71ff64cd 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -533,8 +533,8 @@
 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
  * TIMx_CCER). */
 #define TIM_CCMR1_CC1S_OUT		(0x0 << 0)
-#define TIM_CCMR1_CC1S_IN_TI2		(0x1 << 0)
-#define TIM_CCMR1_CC1S_IN_TI1		(0x2 << 0)
+#define TIM_CCMR1_CC1S_IN_TI2		(0x2 << 0)
+#define TIM_CCMR1_CC1S_IN_TI1		(0x1 << 0)
 #define TIM_CCMR1_CC1S_IN_TRC		(0x3 << 0)
 #define TIM_CCMR1_CC1S_MASK		(0x3 << 0)
 

From 567faa9b61b9124684dc454b05112e28d3b5a97f Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sat, 7 Apr 2012 20:31:56 +1200
Subject: [PATCH 02/13] Corrected parameters of timer_set_mode() to u32.

---
 include/libopencm3/stm32/timer.h | 4 ++--
 lib/stm32/f1/timer.c             | 4 ++--
 lib/stm32/f2/timer.c             | 4 ++--
 lib/stm32/f4/timer.c             | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 71ff64cd..54cc2284 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -857,8 +857,8 @@ void timer_enable_irq(u32 timer_peripheral, u32 irq);
 void timer_disable_irq(u32 timer_peripheral, u32 irq);
 bool timer_get_flag(u32 timer_peripheral, u32 flag);
 void timer_clear_flag(u32 timer_peripheral, u32 flag);
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
-		    u8 alignment, u8 direction);
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+		    u32 alignment, u32 direction);
 void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
 void timer_enable_preload(u32 timer_peripheral);
 void timer_disable_preload(u32 timer_peripheral);
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 8c32670e..85f81ea4 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -118,8 +118,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
-		    u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;
 
diff --git a/lib/stm32/f2/timer.c b/lib/stm32/f2/timer.c
index 3cd5e919..659f8a99 100644
--- a/lib/stm32/f2/timer.c
+++ b/lib/stm32/f2/timer.c
@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
-		    u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;
 
diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c
index bb7b0e7e..6d5ab9df 100644
--- a/lib/stm32/f4/timer.c
+++ b/lib/stm32/f4/timer.c
@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
 	TIM_SR(timer_peripheral) &= ~flag;
 }
 
-void timer_set_mode(u32 timer_peripheral, u8 clock_div,
-		    u8 alignment, u8 direction)
+void timer_set_mode(u32 timer_peripheral, u32 clock_div,
+		    u32 alignment, u32 direction)
 {
 	u32 cr1;
 

From a62473fbdfc4ed61e6b664310040fc789355009e Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sun, 8 Apr 2012 11:11:52 +1200
Subject: [PATCH 03/13] Added convenience funcions for timer input capture
 filter and prescaler.

---
 include/libopencm3/stm32/timer.h | 39 +++++++++++++++++++++++++++
 lib/stm32/f1/timer.c             | 45 ++++++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 54cc2284..836e0641 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -851,6 +851,42 @@ enum tim_oc_mode {
 	TIM_OCM_PWM2,
 };
 
+/* Input Capture channel designators */
+enum tim_ic_id {
+	TIM_IC1,
+	TIM_IC2,
+	TIM_IC3,
+	TIM_IC4,
+};
+
+/* Input Capture input filter */
+enum tim_ic_filter {
+	TIM_IC_OFF,
+	TIM_IC_CK_INT_N_2,
+	TIM_IC_CK_INT_N_4,
+	TIM_IC_CK_INT_N_8,
+	TIM_IC_DTF_DIV_2_N_6,
+	TIM_IC_DTF_DIV_2_N_8,
+	TIM_IC_DTF_DIV_4_N_6,
+	TIM_IC_DTF_DIV_4_N_8,
+	TIM_IC_DTF_DIV_8_N_6,
+	TIM_IC_DTF_DIV_8_N_8,
+	TIM_IC_DTF_DIV_16_N_5,
+	TIM_IC_DTF_DIV_16_N_6,
+	TIM_IC_DTF_DIV_16_N_8,
+	TIM_IC_DTF_DIV_32_N_5,
+	TIM_IC_DTF_DIV_32_N_6,
+	TIM_IC_DTF_DIV_32_N_8,
+};
+
+/* Input Capture input prescaler */
+enum tim_ic_psc {
+	TIM_IC_PSC_OFF,
+	TIM_IC_PSC_2,
+	TIM_IC_PSC_4,
+	TIM_IC_PSC_8,
+};
+
 /* --- TIM functions ------------------------------------------------------- */
 void timer_reset(u32 timer_peripheral);
 void timer_enable_irq(u32 timer_peripheral, u32 irq);
@@ -918,4 +954,7 @@ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
 void timer_generate_event(u32 timer_peripheral, u32 event);
 u32 timer_get_counter(u32 timer_peripheral);
 
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
+
 #endif
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 85f81ea4..8303f890 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -914,3 +914,48 @@ u32 timer_get_counter(u32 timer_peripheral)
 {
 	return TIM_CNT(timer_peripheral);
 }
+
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
+		TIM_CCMR1(timer) |= flt << 4;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
+		TIM_CCMR1(timer) |= flt << 12;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
+		TIM_CCMR2(timer) |= flt << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
+		TIM_CCMR2(timer) |= flt << 12;
+		break;
+	}
+}
+
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 2;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 10;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 10;
+		break;
+	}
+}
+

From 4b041697f4b2c742412c841d33ba41c873bc56bf Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sun, 8 Apr 2012 11:56:42 +1200
Subject: [PATCH 04/13] Added convenience function for timer input selection.

---
 include/libopencm3/stm32/timer.h | 11 +++++++++++
 lib/stm32/f1/timer.c             | 30 ++++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 836e0641..c7a49344 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -887,6 +887,16 @@ enum tim_ic_psc {
 	TIM_IC_PSC_8,
 };
 
+/* Input Capture input prescaler */
+enum tim_ic_input {
+	TIM_IC_OUT = 0,
+	TIM_IC_IN_TI1 = 1,
+	TIM_IC_IN_TI2 = 2,
+	TIM_IC_IN_TRC = 3,
+	TIM_IC_IN_TI3 = 5,
+	TIM_IC_IN_TI4 = 6,
+};
+
 /* --- TIM functions ------------------------------------------------------- */
 void timer_reset(u32 timer_peripheral);
 void timer_enable_irq(u32 timer_peripheral, u32 irq);
@@ -956,5 +966,6 @@ u32 timer_get_counter(u32 timer_peripheral);
 
 void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
 void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
+void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
 
 #endif
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 8303f890..4d0e88ef 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -959,3 +959,33 @@ void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
 	}
 }
 
+void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
+{
+	in &= 3;
+
+	if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
+	    ((in == TIM_IC_IN_TI1) || (in = TIM_IC_IN_TI2))) {
+		/* Input select bits are flipped for these combinations */
+		in ^= 3;
+	}
+	
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_CC1S_MASK;
+		TIM_CCMR1(timer) |= in;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_CC2S_MASK;
+		TIM_CCMR1(timer) |= in << 8;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_CC3S_MASK;
+		TIM_CCMR2(timer) |= in;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_CC4S_MASK;
+		TIM_CCMR2(timer) |= in << 8;
+		break;
+	}
+}
+

From a8ec86a52767b7d90bc1467d4557e2148ad5ce9e Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sun, 8 Apr 2012 13:55:16 +1200
Subject: [PATCH 05/13] Added functions for timer input capture polarity and
 enable/disable.

---
 include/libopencm3/stm32/timer.h |  9 +++++++++
 lib/stm32/f1/timer.c             | 18 ++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index c7a49344..a9d23299 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -897,6 +897,12 @@ enum tim_ic_input {
 	TIM_IC_IN_TI4 = 6,
 };
 
+/* Input Capture input prescaler */
+enum tim_ic_pol {
+	TIM_IC_RISING,
+	TIM_IC_FALLING,
+};
+
 /* --- TIM functions ------------------------------------------------------- */
 void timer_reset(u32 timer_peripheral);
 void timer_enable_irq(u32 timer_peripheral, u32 irq);
@@ -967,5 +973,8 @@ u32 timer_get_counter(u32 timer_peripheral);
 void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
 void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
 void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
+void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
+void timer_ic_enable(u32 timer, enum tim_ic_id ic);
+void timer_ic_disable(u32 timer, enum tim_ic_id ic);
 
 #endif
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 4d0e88ef..e1095f2f 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -989,3 +989,21 @@ void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
 	}
 }
 
+void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
+{
+	if (pol)
+		TIM_CCER(timer) |= (0x2 << (ic * 4));
+	else
+		TIM_CCER(timer) &= ~(0x2 << (ic * 4));
+}
+
+void timer_ic_enable(u32 timer, enum tim_ic_id ic)
+{
+	TIM_CCER(timer) |= (0x1 << (ic * 4));
+}
+
+void timer_ic_disable(u32 timer, enum tim_ic_id ic)
+{
+	TIM_CCER(timer) &= ~(0x1 << (ic * 4));
+}
+

From 8820277f091d46e9376daca6b08b9e909023fc24 Mon Sep 17 00:00:00 2001
From: Gareth McMullin <gareth@blacksphere.co.nz>
Date: Sun, 8 Apr 2012 14:12:21 +1200
Subject: [PATCH 06/13] Added functions for configuring timers in slave mode.

---
 include/libopencm3/stm32/timer.h |  6 ++++++
 lib/stm32/f1/timer.c             | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index a9d23299..3c8c8c2c 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -977,4 +977,10 @@ void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
 void timer_ic_enable(u32 timer, enum tim_ic_id ic);
 void timer_ic_disable(u32 timer, enum tim_ic_id ic);
 
+void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt);
+void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
+void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
+void timer_slave_set_mode(u32 timer, u8 mode);
+void timer_slave_set_trigger(u32 timer, u8 trigger);
+
 #endif
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index e1095f2f..cf5b4113 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -1007,3 +1007,35 @@ void timer_ic_disable(u32 timer, enum tim_ic_id ic)
 	TIM_CCER(timer) &= ~(0x1 << (ic * 4));
 }
 
+void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_ETF_MASK;
+	TIM_SMCR(timer) |= flt << 8;
+}
+
+void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_ETPS_MASK;
+	TIM_SMCR(timer) |= psc << 12;
+}
+
+void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
+{
+	if (pol)
+		TIM_SMCR(timer) |= TIM_SMCR_ETP;
+	else
+		TIM_SMCR(timer) &= ~TIM_SMCR_ETP;
+}
+
+void timer_slave_set_mode(u32 timer, u8 mode)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_SMS_MASK;
+	TIM_SMCR(timer) |= mode;
+}
+
+void timer_slave_set_trigger(u32 timer, u8 trigger)
+{
+	TIM_SMCR(timer) &= ~TIM_SMCR_TS_MASK;
+	TIM_SMCR(timer) |= trigger;
+}
+

From b97c59e462baf9dae0c21589c52d280e111ed142 Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Fri, 20 Apr 2012 21:08:38 -0700
Subject: [PATCH 07/13] Initial implementation of DAC registers for stm32 by
 Felix Held

---
 include/libopencm3/stm32/dac.h | 302 +++++++++++++++++++++++++++++++++
 1 file changed, 302 insertions(+)
 create mode 100644 include/libopencm3/stm32/dac.h

diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h
new file mode 100644
index 00000000..0402eb02
--- /dev/null
+++ b/include/libopencm3/stm32/dac.h
@@ -0,0 +1,302 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DAC_H
+#define LIBOPENCM3_DAC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+
+/* --- DAC registers ------------------------------------------------------- */
+
+/* DAC control register (DAC_CR) */
+#define DAC_CR				MMIO32(DAC_BASE + 0x00)
+
+/* DAC software trigger register (DAC_SWTRIGR) */
+#define DAC_SWTRIGR			MMIO32(DAC_BASE + 0x04)
+
+/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
+#define DAC_DHR12R1			MMIO32(DAC_BASE + 0x08)
+
+/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
+#define DAC_DHR12L1			MMIO32(DAC_BASE + 0x0C)
+
+/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
+#define DAC_DHR8R1			MMIO32(DAC_BASE + 0x10)
+
+/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
+#define DAC_DHR12R2			MMIO32(DAC_BASE + 0x14)
+
+/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
+#define DAC_DHR12L2			MMIO32(DAC_BASE + 0x18)
+
+/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
+#define DAC_DHR8R2			MMIO32(DAC_BASE + 0x1C)
+
+/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
+#define DAC_DHR12RD			MMIO32(DAC_BASE + 0x20)
+
+/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
+#define DAC_DHR12LD			MMIO32(DAC_BASE + 0x24)
+
+/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
+#define DAC_DHR8RD			MMIO32(DAC_BASE + 0x28)
+
+/* DAC channel1 data output register (DAC_DOR1) */
+#define DAC_DOR1			MMIO32(DAC_BASE + 0x2C)
+
+/* DAC channel2 data output register (DAC_DOR2) */
+#define DAC_DOR2			MMIO32(DAC_BASE + 0x30)
+
+
+/* --- DAC_CR values ------------------------------------------------------- */
+
+/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
+/* doesn't exist in most members of the stm32f1 family */
+#define DAC_CR_DMAUDRIE2		(1 << 29)
+
+/* DMAEN2: DAC channel2 DMA enable */
+#define DAC_CR_DMAEN2			(1 << 28)
+
+/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
+/* DAC_CR_MAMP2_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP2_SHIFT		24
+#define DAC_CR_MAMP2_1			(0x0 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_2			(0x1 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_3			(0x2 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_4			(0x3 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_5			(0x4 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_6			(0x5 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_7			(0x6 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_8			(0x7 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_9			(0x8 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_10			(0x9 << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_11			(0xA << DAC_CR_MAMP2_SHIFT)
+#define DAC_CR_MAMP2_12			(0xB << DAC_CR_MAMP2_SHIFT)
+
+/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ */
+#define DAC_CR_WAVE2_SHIFT		22
+#define DAC_CR_WAVE2_DIS		(0x0 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_NOISE		(0x1 << DAC_CR_WAVE2_SHIFT)
+#define DAC_CR_WAVE2_TRI		(0x2 << DAC_CR_WAVE2_SHIFT)
+
+/* TSEL2[2:0]: DAC channel2 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event
+ * T8: Timer 8 TRGO event
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL2_SHIFT		19
+#define DAC_CR_TSEL2_T6			(0x0 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T3			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T8			(0x1 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T7			(0x2 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T5			(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T15		(0x3 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T2			(0x4 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
+#define DAC_CR_TSEL2_SW			(0x7 << DAC_CR_TSEL2_SHIFT)
+
+/* TEN2: DAC channel2 trigger enable */
+#define DAC_CR_TEN2			(1 << 18)
+
+/* BOFF2: DAC channel2 output buffer disable */
+#define DAC_CR_BOFF2			(1 << 17)
+
+/* EN2: DAC channel2 enable */
+#define DAC_CR_EN2			(1 << 16)
+
+/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
+/* doesn't exist in most members of the stm32f1 family */
+#define DAC_CR_DMAUDRIE1	(1 << 13)
+
+/* DMAEN1: DAC channel1 DMA enable */
+#define DAC_CR_DMAEN1			(1 << 12)
+
+/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
+/* DAC_CR_MAMP1_n:
+ * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
+ */
+#define DAC_CR_MAMP1_SHIFT		8
+#define DAC_CR_MAMP1_1			(0x0 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_2			(0x1 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_3			(0x2 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_4			(0x3 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_5			(0x4 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_6			(0x5 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_7			(0x6 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_8			(0x7 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_9			(0x8 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_10			(0x9 << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_11			(0xA << DAC_CR_MAMP1_SHIFT)
+#define DAC_CR_MAMP1_12			(0xB << DAC_CR_MAMP1_SHIFT)
+
+/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
+/* Legend:
+ * DIS: wave generation disabled
+ * NOISE: Noise wave generation enabled
+ * TRI: Triangle wave generation enabled
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ */
+#define DAC_CR_WAVE1_SHIFT		6
+#define DAC_CR_WAVE1_DIS		(0x0 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_NOISE		(0x1 << DAC_CR_WAVE1_SHIFT)
+#define DAC_CR_WAVE1_TRI		(0x2 << DAC_CR_WAVE1_SHIFT)
+
+/* TSEL1[2:0]: DAC channel1 trigger selection */
+/* Legend:
+ *
+ * T6: Timer 6 TRGO event
+ * T3: Timer 3 TRGO event in connectivity line devices
+ * T8: Timer 8 TRGO event in high-density and XL-density devices
+ * T7: Timer 7 TRGO event
+ * T5: Timer 5 TRGO event
+ * T15: Timer 15 TRGO event
+ * T2: Timer 2 TRGO event
+ * T4: Timer 4 TRGO event
+ * E9: External line9
+ * SW: Software trigger
+ *
+ * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
+ * Note: T3 == T8; T5 == T15; not both present on one device
+ * Note: this is *not* valid for the STM32L1 family
+ */
+#define DAC_CR_TSEL1_SHIFT		3
+#define DAC_CR_TSEL1_T6			(0x0 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T3			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T8			(0x1 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T7			(0x2 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T5			(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T15		(0x3 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T2			(0x4 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
+#define DAC_CR_TSEL1_SW			(0x7 << DAC_CR_TSEL1_SHIFT)
+
+/* TEN1: DAC channel1 trigger enable */
+#define DAC_CR_TEN1			(1 << 2)
+
+/* BOFF1: DAC channel1 output buffer disable */
+#define DAC_CR_BOFF1			(1 << 1)
+
+/* EN1: DAC channel1 enable */
+#define DAC_CR_EN1			(1 << 0)
+
+
+/* --- DAC_SWTRIGR values -------------------------------------------------- */
+
+/* SWTRIG2: DAC channel2 software trigger */
+#define DAC_SWTRIGR_SWTRIG2		(1 << 1)
+
+/* SWTRIG1: DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG1		(1 << 0)
+
+
+/* --- DAC_DHR12R1 values -------------------------------------------------- */
+#define DAC_DHR12R1_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12R1_DACC1DHR_MSK	(0x0FFF << 0)
+
+
+/* --- DAC_DHR12L1 values -------------------------------------------------- */
+#define DAC_DHR12L1_DACC1DHR_LSB	(1 << 4)
+#define DAC_DHR12L1_DACC1DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8R1 values --------------------------------------------------- */
+#define DAC_DHR8R1_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8R1_DACC1DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DHR12R2 values -------------------------------------------------- */
+#define DAC_DHR12R2_DACC2DHR_LSB	(1 << 0)
+#define DAC_DHR12R2_DACC2DHR_MSK	(0x00FFF << 0)
+
+
+/* --- DAC_DHR12L2 values -------------------------------------------------- */
+#define DAC_DHR12L2_DACC2DHR_LSB	(1 << 4)
+#define DAC_DHR12L2_DACC2DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8R2 values --------------------------------------------------- */
+#define DAC_DHR8R2_DACC2DHR_LSB		(1 << 0)
+#define DAC_DHR8R2_DACC2DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DHR12RD values -------------------------------------------------- */
+#define DAC_DHR12RD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12RD_DACC2DHR_MSK	(0x0FFF << 16)
+#define DAC_DHR12RD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12RD_DACC1DHR_MSK	(0x0FFF << 0)
+
+
+/* --- DAC_DHR12LD values -------------------------------------------------- */
+#define DAC_DHR12LD_DACC2DHR_LSB	(1 << 16)
+#define DAC_DHR12LD_DACC2DHR_MSK	(0x0FFF << 20)
+#define DAC_DHR12LD_DACC1DHR_LSB	(1 << 0)
+#define DAC_DHR12LD_DACC1DHR_MSK	(0x0FFF << 4)
+
+
+/* --- DAC_DHR8RD values --------------------------------------------------- */
+#define DAC_DHR8RD_DACC2DHR_LSB		(1 << 8)
+#define DAC_DHR8RD_DACC2DHR_MSK		(0x00FF << 8)
+#define DAC_DHR8RD_DACC1DHR_LSB		(1 << 0)
+#define DAC_DHR8RD_DACC1DHR_MSK		(0x00FF << 0)
+
+
+/* --- DAC_DOR1 values ----------------------------------------------------- */
+#define DAC_DOR1_DACC1DOR_LSB		(1 << 0)
+#define DAC_DOR1_DACC1DOR_MSK		(0x0FFF << 0)
+
+
+/* --- DAC_DOR2 values ----------------------------------------------------- */
+#define DAC_DOR2_DACC2DOR_LSB		(1 << 0)
+#define DAC_DOR2_DACC2DOR_MSK		(0x0FFF << 0)
+
+
+/* --- Function prototypes ------------------------------------------------- */
+
+
+/* TODO */
+
+
+#endif

From 0d50b97ed5c61bd7c3936407656a5c70c3cdfa23 Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Fri, 20 Apr 2012 21:16:23 -0700
Subject: [PATCH 08/13] Correct DMA_CCR_MSIZE and PSIZE bit masks. Thanks Tomas
 Solic.

---
 include/libopencm3/stm32/f1/dma.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/libopencm3/stm32/f1/dma.h b/include/libopencm3/stm32/f1/dma.h
index 7f9abada..5aa01835 100644
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -252,14 +252,14 @@
 #define DMA_CCR_MSIZE_8BIT		(0x0 << 10)
 #define DMA_CCR_MSIZE_16BIT		(0x1 << 10)
 #define DMA_CCR_MSIZE_32BIT		(0x2 << 10)
-#define DMA_CCR_MSIZE_MASK		(0x2 << 10)
+#define DMA_CCR_MSIZE_MASK		(0x3 << 10)
 #define DMA_CCR_MSIZE_SHIFT		10
 
 /* PSIZE[9:8]: Peripheral size */
 #define DMA_CCR_PSIZE_8BIT		(0x0 << 8)
 #define DMA_CCR_PSIZE_16BIT		(0x1 << 8)
 #define DMA_CCR_PSIZE_32BIT		(0x2 << 8)
-#define DMA_CCR_PSIZE_MASK		(0x2 << 8)
+#define DMA_CCR_PSIZE_MASK		(0x3 << 8)
 #define DMA_CCR_PSIZE_SHIFT		8
 
 /* MINC: Memory increment mode */

From 5510e1fe3b68708e0b539cf615833fea52d389eb Mon Sep 17 00:00:00 2001
From: Tomaz Solc <tomaz.solc@tablix.org>
Date: Fri, 16 Mar 2012 10:14:00 +0100
Subject: [PATCH 09/13] Wait for writes to finish upon exiting RTC config

This fixes race condition when rtc_get_counter_val() call immediately follows
rtc_set_counter_val().
---
 lib/stm32/f1/rtc.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c
index 0b7769ec..08a49536 100644
--- a/lib/stm32/f1/rtc.c
+++ b/lib/stm32/f1/rtc.c
@@ -99,14 +99,13 @@ void rtc_enter_config_mode(void)
 
 void rtc_exit_config_mode(void)
 {
-	/* u32 reg32; */
+	u32 reg32;
 
 	/* Exit configuration mode. */
 	RTC_CRL &= ~RTC_CRL_CNF;
 
 	/* Wait until the RTOFF bit is 1 (our RTC register write finished). */
-	/* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */
-	/* TODO: Unnecessary since we poll the bit on config entry(?) */
+	while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
 }
 
 void rtc_set_alarm_time(u32 alarm_time)

From c3038bc876c0154a375a92e91d3cce271d48ae1c Mon Sep 17 00:00:00 2001
From: Tomaz Solc <tomaz.solc@tablix.org>
Date: Tue, 6 Mar 2012 11:41:29 +0100
Subject: [PATCH 10/13] Added rcc.h include, needed for osc_t.

---
 include/libopencm3/stm32/f1/rtc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/libopencm3/stm32/f1/rtc.h b/include/libopencm3/stm32/f1/rtc.h
index d9c26398..5e203ab9 100644
--- a/include/libopencm3/stm32/f1/rtc.h
+++ b/include/libopencm3/stm32/f1/rtc.h
@@ -23,6 +23,7 @@
 #include <libopencm3/stm32/memorymap.h>
 #include <libopencm3/cm3/common.h>
 #include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/f1/rcc.h>
 
 /* --- RTC registers ------------------------------------------------------- */
 

From bf6558918359a4aa81514f56168cdd8fe5c28efa Mon Sep 17 00:00:00 2001
From: Tomaz Solc <tomaz.solc@tablix.org>
Date: Mon, 5 Mar 2012 15:51:31 +0100
Subject: [PATCH 11/13] Support for exception handling in linker scripts.

This is needed even in plain C when 64 bit variable (e.g. long long int)
arithmetic is used. For example it is required when newlib is compiled with
--enable-newlib-io-long-long.

Conflicts:

	lib/stm32/f1/libopencm3_stm32f1.ld
	lib/stm32/f2/libopencm3_stm32f2.ld
---
 examples/stm32/f1/Makefile.include |  3 ++-
 examples/stm32/f2/Makefile.include |  4 ++--
 lib/stm32/f1/libopencm3_stm32f1.ld | 26 +++++++++++++-------------
 lib/stm32/f1/vector.c              |  4 ++--
 lib/stm32/f2/libopencm3_stm32f2.ld | 26 +++++++++++++-------------
 lib/stm32/f2/vector.c              |  4 ++--
 6 files changed, 34 insertions(+), 33 deletions(-)

diff --git a/examples/stm32/f1/Makefile.include b/examples/stm32/f1/Makefile.include
index b60bfb90..92ad689d 100644
--- a/examples/stm32/f1/Makefile.include
+++ b/examples/stm32/f1/Makefile.include
@@ -31,7 +31,8 @@ TOOLCHAIN_DIR   = ../../../../..
 CFLAGS		+= -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \
 		   -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F1
 LDSCRIPT	?= $(BINARY).ld
-LDFLAGS		+= -lc -lnosys -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f1 \
+LDFLAGS		+= -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \
+		   -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f1 \
 		   -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
 		   -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float
 OBJS		+= $(BINARY).o
diff --git a/examples/stm32/f2/Makefile.include b/examples/stm32/f2/Makefile.include
index 4faa27ef..f68da433 100644
--- a/examples/stm32/f2/Makefile.include
+++ b/examples/stm32/f2/Makefile.include
@@ -32,8 +32,8 @@ TOOLCHAIN_DIR   = ../../../../..
 CFLAGS		+= -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \
 		   -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F2
 LDSCRIPT	?= $(BINARY).ld
-LDFLAGS		+= -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \
-			 -L$(TOOLCHAIN_DIR)/lib/stm32/f2 \
+LDFLAGS		+= -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \
+		   -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f2 \
 		   -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \
 		   -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float
 OBJS		+= $(BINARY).o
diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld
index 0624b96d..e2f1bd1a 100644
--- a/lib/stm32/f1/libopencm3_stm32f1.ld
+++ b/lib/stm32/f1/libopencm3_stm32f1.ld
@@ -40,17 +40,22 @@ SECTIONS
 		. = ALIGN(4);
 	} >rom
 
-	/* exception index - required due to libgcc.a issuing /0 exceptions */
-	__exidx_start = .;
+	/*
+	* Another section used by C++ stuff, appears when using newlib with
+	* 64bit (long long) printf support
+	*/
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
 	.ARM.exidx : {
-		   *(.ARM.exidx*)
-	} > rom
-	__exidx_end = .;
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
 
+	. = ORIGIN(ram);
 
-	_etext = .;
-
-	.data : {
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
@@ -64,11 +69,6 @@ SECTIONS
 		_ebss = .;
 	} >ram
 
-	/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} >ram
-
 	. = ALIGN(4);
 	end = .;
 }
diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c
index fe61e29d..119ce309 100644
--- a/lib/stm32/f1/vector.c
+++ b/lib/stm32/f1/vector.c
@@ -20,7 +20,7 @@
 #define WEAK __attribute__ ((weak))
 
 /* Symbols exported by the linker script(s). */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
 
 void main(void);
 void reset_handler(void);
@@ -197,7 +197,7 @@ void reset_handler(void)
 
 	__asm__("MSR msp, %0" : : "r"(&_stack));
 
-	for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+	for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
 		*dest = *src;
 
 	while (dest < &_ebss)
diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld
index 0624b96d..e2f1bd1a 100644
--- a/lib/stm32/f2/libopencm3_stm32f2.ld
+++ b/lib/stm32/f2/libopencm3_stm32f2.ld
@@ -40,17 +40,22 @@ SECTIONS
 		. = ALIGN(4);
 	} >rom
 
-	/* exception index - required due to libgcc.a issuing /0 exceptions */
-	__exidx_start = .;
+	/*
+	* Another section used by C++ stuff, appears when using newlib with
+	* 64bit (long long) printf support
+	*/
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
 	.ARM.exidx : {
-		   *(.ARM.exidx*)
-	} > rom
-	__exidx_end = .;
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
 
+	. = ORIGIN(ram);
 
-	_etext = .;
-
-	.data : {
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
@@ -64,11 +69,6 @@ SECTIONS
 		_ebss = .;
 	} >ram
 
-	/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} >ram
-
 	. = ALIGN(4);
 	end = .;
 }
diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c
index 1c901da7..64d2426b 100644
--- a/lib/stm32/f2/vector.c
+++ b/lib/stm32/f2/vector.c
@@ -21,7 +21,7 @@
 #define WEAK __attribute__ ((weak))
 
 /* Symbols exported by the linker script(s): */
-extern unsigned _etext, _data, _edata, _ebss, _stack;
+extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
 
 void main(void);
 void reset_handler(void);
@@ -224,7 +224,7 @@ void reset_handler(void)
 
 	__asm__("MSR msp, %0" : : "r"(&_stack));
 
-	for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
+	for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
 		*dest = *src;
 
 	while (dest < &_ebss)

From 3b20a5e34e0c79a47fd774a7d68783476918861a Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Tue, 24 Apr 2012 09:34:39 +0200
Subject: [PATCH 12/13] Removed the load address statement from the .bss
 section.

Otherwise the linker will complain: "section has both a load address and
a load region"
---
 lib/stm32/f1/libopencm3_stm32f1.ld | 2 +-
 lib/stm32/f2/libopencm3_stm32f2.ld | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld
index e2f1bd1a..a7943149 100644
--- a/lib/stm32/f1/libopencm3_stm32f1.ld
+++ b/lib/stm32/f1/libopencm3_stm32f1.ld
@@ -55,7 +55,7 @@ SECTIONS
 
 	. = ORIGIN(ram);
 
-	.data : AT (__exidx_end) {
+	.data : {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld
index e2f1bd1a..a7943149 100644
--- a/lib/stm32/f2/libopencm3_stm32f2.ld
+++ b/lib/stm32/f2/libopencm3_stm32f2.ld
@@ -55,7 +55,7 @@ SECTIONS
 
 	. = ORIGIN(ram);
 
-	.data : AT (__exidx_end) {
+	.data : {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);

From 3596075ee0f189f8a95090c4fb5522844255a029 Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Wed, 25 Apr 2012 17:34:07 +0200
Subject: [PATCH 13/13] Fixed the linker scripts to be the way Tomaz Solc
 proposed.

Something went wrong when cherrypicking his commits in the pull request.
Sorry about that. :(
---
 lib/stm32/f1/libopencm3_stm32f1.ld | 13 ++++++++++---
 lib/stm32/f2/libopencm3_stm32f2.ld | 13 ++++++++++---
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/lib/stm32/f1/libopencm3_stm32f1.ld b/lib/stm32/f1/libopencm3_stm32f1.ld
index a7943149..a64a1f77 100644
--- a/lib/stm32/f1/libopencm3_stm32f1.ld
+++ b/lib/stm32/f1/libopencm3_stm32f1.ld
@@ -38,6 +38,7 @@ SECTIONS
 		. = ALIGN(4);
 		*(.rodata*)	/* Read-only data */
 		. = ALIGN(4);
+		_etext = .;
 	} >rom
 
 	/*
@@ -55,19 +56,25 @@ SECTIONS
 
 	. = ORIGIN(ram);
 
-	.data : {
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
 		_edata = .;
-	} >ram AT >rom
+	} >ram
 
 	.bss : {
 		*(.bss*)	/* Read-write zero initialized data */
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = .;
-	} >ram
+	} >ram AT >rom
+
+	/*
+	 * The .eh_frame section appears to be used for C++ exception handling.
+	 * You may need to fix this if you're using C++.
+	 */
+	/DISCARD/ : { *(.eh_frame) }
 
 	. = ALIGN(4);
 	end = .;
diff --git a/lib/stm32/f2/libopencm3_stm32f2.ld b/lib/stm32/f2/libopencm3_stm32f2.ld
index a7943149..a64a1f77 100644
--- a/lib/stm32/f2/libopencm3_stm32f2.ld
+++ b/lib/stm32/f2/libopencm3_stm32f2.ld
@@ -38,6 +38,7 @@ SECTIONS
 		. = ALIGN(4);
 		*(.rodata*)	/* Read-only data */
 		. = ALIGN(4);
+		_etext = .;
 	} >rom
 
 	/*
@@ -55,19 +56,25 @@ SECTIONS
 
 	. = ORIGIN(ram);
 
-	.data : {
+	.data : AT (__exidx_end) {
 		_data = .;
 		*(.data*)	/* Read-write initialized data */
 		. = ALIGN(4);
 		_edata = .;
-	} >ram AT >rom
+	} >ram
 
 	.bss : {
 		*(.bss*)	/* Read-write zero initialized data */
 		*(COMMON)
 		. = ALIGN(4);
 		_ebss = .;
-	} >ram
+	} >ram AT >rom
+
+	/*
+	 * The .eh_frame section appears to be used for C++ exception handling.
+	 * You may need to fix this if you're using C++.
+	 */
+	/DISCARD/ : { *(.eh_frame) }
 
 	. = ALIGN(4);
 	end = .;