From 17d7dca9aecf3c1ba187dd2669cd4d443eec3539 Mon Sep 17 00:00:00 2001 From: mean Date: Thu, 7 Apr 2022 14:19:48 +0200 Subject: [PATCH 1/5] build ch32 in its own file --- src/target/ch32f1.c | 82 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 73 insertions(+), 9 deletions(-) diff --git a/src/target/ch32f1.c b/src/target/ch32f1.c index 4f15c819..71e9f538 100644 --- a/src/target/ch32f1.c +++ b/src/target/ch32f1.c @@ -1,14 +1,37 @@ /* * This file is part of the Black Magic Debug project. * - * Copyright (C) 2022 Black Sphere Technologies Ltd. - * See CH32 Sample code from WCH StdPeriphLib_CH32F1/Examples/FLASH/FLASH_Program + * Copyright (C) 2011 Black Sphere Technologies Ltd. + * Written by Gareth McMullin * - * The CH32 seems to like the EOP bit to be cleared at the end of erase/flash operation - * The following code works fine in BMP hosted mode - * It does NOT work with a real BMP, only the first 128 bytes block is successfully written + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ + +/* This file implements CH32F1xx target specific functions. + The ch32 flash is rather slow so this code is using the so called fast mode (ch32 specific). + 128 bytes are copied to a write buffer, then the write buffer is committed to flash + /!\ There is some sort of bus stall/bus arbitration going on that does NOT work when + programmed through SWD/jtag + The workaround is to wait a few cycles before filling the write buffer. This is performed by reading the flash a few times + + */ + +#include "general.h" +#include "target.h" +#include "target_internal.h" +#include "cortexm.h" + #if PC_HOSTED == 1 #define DEBUG_CH DEBUG_INFO #define ERROR_CH DEBUG_WARN @@ -17,11 +40,56 @@ #define ERROR_CH DEBUG_WARN //DEBUG_WARN #endif +extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff static int ch32f1_flash_erase(struct target_flash *f, target_addr addr, size_t len); static int ch32f1_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len); + +#define FPEC_BASE 0x40022000 +#define FLASH_ACR (FPEC_BASE+0x00) +#define FLASH_KEYR (FPEC_BASE+0x04) +#define FLASH_OPTKEYR (FPEC_BASE+0x08) +#define FLASH_SR (FPEC_BASE+0x0C) +#define FLASH_CR (FPEC_BASE+0x10) +#define FLASH_AR (FPEC_BASE+0x14) +#define FLASH_OBR (FPEC_BASE+0x1C) +#define FLASH_WRPR (FPEC_BASE+0x20) + +#define FLASH_BANK2_OFFSET 0x40 +#define FLASH_BANK_SPLIT 0x08080000 + +#define FLASH_CR_OBL_LAUNCH (1<<13) +#define FLASH_CR_OPTWRE (1 << 9) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_CR_OPTER (1 << 5) +#define FLASH_CR_OPTPG (1 << 4) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) + +#define FLASH_OBR_RDPRT (1 << 1) + +#define FLASH_SR_BSY (1 << 0) + +#define FLASH_OBP_RDP 0x1FFFF800 +#define FLASH_OBP_RDP_KEY 0x5aa5 +#define FLASH_OBP_RDP_KEY_F3 0x55AA + +#define KEY1 0x45670123 +#define KEY2 0xCDEF89AB + +#define SR_ERROR_MASK 0x14 +#define SR_EOP 0x20 + +#define DBGMCU_IDCODE 0xE0042000 +#define DBGMCU_IDCODE_F0 0x40015800 + +#define FLASHSIZE 0x1FFFF7E0 +#define FLASHSIZE_F0 0x1FFFF7CC + #define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x #define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock @@ -57,10 +125,6 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era target_add_flash(t, f); } - - - - #define WAIT_BUSY() do { \ sr = target_mem_read32(t, FLASH_SR); \ if(target_check_error(t)) { \ From 733cf126633eb48e300475df5d03925cf1b2332c Mon Sep 17 00:00:00 2001 From: mean Date: Thu, 7 Apr 2022 15:00:18 +0200 Subject: [PATCH 2/5] cleanup --- src/target/ch32f1.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/target/ch32f1.c b/src/target/ch32f1.c index 71e9f538..b9cfc84b 100644 --- a/src/target/ch32f1.c +++ b/src/target/ch32f1.c @@ -207,7 +207,6 @@ bool ch32f1_probe(target *t) return false; } - uint32_t signature= target_mem_read32(t, FLASHSIZE); uint32_t flashSize=signature & 0xFFFF; @@ -215,9 +214,6 @@ bool ch32f1_probe(target *t) ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize*1024, 128); target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD/VL-LD/VL-MD"); t->driver = "CH32F1 medium density (stm32f1 clone)"; - - // make sure we have 2 wait states - //target_mem_write32(t, FLASH_ACR,2); return true; } /** @@ -229,9 +225,6 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len) target *t = f->t; DEBUG_CH("CH32: flash erase \n"); -// Make sure we have 2 wait states, prefetch disabled - //target_mem_write32(t, FLASH_ACR , 2); - if (ch32f1_flash_unlock(t)) { ERROR_CH("CH32: Unlock failed\n"); return -1; @@ -273,7 +266,6 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len) static bool ch32f1_wait_flash_ready(target *t,uint32_t adr) { - uint32_t ff; for(int i=0;i<32;i++) { ff=target_mem_read32(t,adr); From 17dca6f79124a12f68e07e0e9507c7cbaf16b508 Mon Sep 17 00:00:00 2001 From: mean Date: Thu, 7 Apr 2022 15:01:58 +0200 Subject: [PATCH 3/5] tabify --- src/target/ch32f1.c | 62 ++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/src/target/ch32f1.c b/src/target/ch32f1.c index b9cfc84b..cf030430 100644 --- a/src/target/ch32f1.c +++ b/src/target/ch32f1.c @@ -43,9 +43,9 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff static int ch32f1_flash_erase(struct target_flash *f, - target_addr addr, size_t len); + target_addr addr, size_t len); static int ch32f1_flash_write(struct target_flash *f, - target_addr dest, const void *src, size_t len); + target_addr dest, const void *src, size_t len); #define FPEC_BASE 0x40022000 #define FLASH_ACR (FPEC_BASE+0x00) @@ -87,25 +87,25 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff #define DBGMCU_IDCODE 0xE0042000 #define DBGMCU_IDCODE_F0 0x40015800 -#define FLASHSIZE 0x1FFFF7E0 +#define FLASHSIZE 0x1FFFF7E0 #define FLASHSIZE_F0 0x1FFFF7CC #define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x -#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock -#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program -#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase -#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load +#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock +#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program +#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase +#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load #define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset -#define FLASH_SR_EOP (1<<5) // End of programming +#define FLASH_SR_EOP (1<<5) // End of programming #define FLASH_BEGIN_ADDRESS_CH32 0x8000000 -#define FLASH_MAGIC (FPEC_BASE+0x34) +#define FLASH_MAGIC (FPEC_BASE+0x34) static volatile uint32_t magic,sr,ct; /** - \fn ch32f1_add_flash - \brief "fast" flash driver for CH32F10x chips + \fn ch32f1_add_flash + \brief "fast" flash driver for CH32F10x chips */ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t erasesize) { @@ -126,37 +126,37 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era } #define WAIT_BUSY() do { \ - sr = target_mem_read32(t, FLASH_SR); \ - if(target_check_error(t)) { \ - ERROR_CH("ch32f1 flash write: comm error\n"); \ - return -1; \ - } \ - } while (sr & FLASH_SR_BSY); + sr = target_mem_read32(t, FLASH_SR); \ + if(target_check_error(t)) { \ + ERROR_CH("ch32f1 flash write: comm error\n"); \ + return -1; \ + } \ + } while (sr & FLASH_SR_BSY); #define WAIT_EOP() do { \ - sr = target_mem_read32(t, FLASH_SR); \ - if(target_check_error(t)) { \ - ERROR_CH("ch32f1 flash write: comm error\n"); \ - return -1; \ - } \ - } while (!(sr & FLASH_SR_EOP)); + sr = target_mem_read32(t, FLASH_SR); \ + if(target_check_error(t)) { \ + ERROR_CH("ch32f1 flash write: comm error\n"); \ + return -1; \ + } \ + } while (!(sr & FLASH_SR_EOP)); -#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP) +#define CLEAR_EOP() target_mem_write32(t, FLASH_SR,FLASH_SR_EOP) #define SET_CR(bit) { ct = target_mem_read32(t, FLASH_CR); \ - ct|=(bit); \ - target_mem_write32(t, FLASH_CR, ct);} + ct|=(bit); \ + target_mem_write32(t, FLASH_CR, ct);} #define CLEAR_CR(bit) {ct = target_mem_read32(t, FLASH_CR); \ - ct&=~(bit); \ - target_mem_write32(t, FLASH_CR, ct);} + ct&=~(bit); \ + target_mem_write32(t, FLASH_CR, ct);} // Which one is the right value ? #define MAGIC_WORD 0x100 // #define MAGIC_WORD 0x100 #define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \ - target_mem_write32(t, FLASH_MAGIC , magic); } + target_mem_write32(t, FLASH_MAGIC , magic); } /** \fn ch32f1_flash_unlock @@ -188,7 +188,7 @@ static int ch32f1_flash_lock(target *t) /** \brief identify the ch32f1 chip - Actually grab all cortex m3 with designer = arm not caught earlier... + Actually grab all cortex m3 with designer = arm not caught earlier... */ bool ch32f1_probe(target *t) @@ -316,7 +316,7 @@ int ch32f1_buffer_clear(target *t) */ static int ch32f1_flash_write(struct target_flash *f, - target_addr dest, const void *src, size_t len) + target_addr dest, const void *src, size_t len) { target *t = f->t; size_t length = len; From 844ca65a8f9cc29fe5dabba84ac1339577aaf91b Mon Sep 17 00:00:00 2001 From: mean Date: Thu, 7 Apr 2022 15:17:20 +0200 Subject: [PATCH 4/5] cosmetic --- src/target/ch32f1.c | 111 +++++++++++++++++--------------------------- 1 file changed, 43 insertions(+), 68 deletions(-) diff --git a/src/target/ch32f1.c b/src/target/ch32f1.c index cf030430..33c782da 100644 --- a/src/target/ch32f1.c +++ b/src/target/ch32f1.c @@ -47,59 +47,35 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff static int ch32f1_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len); -#define FPEC_BASE 0x40022000 -#define FLASH_ACR (FPEC_BASE+0x00) -#define FLASH_KEYR (FPEC_BASE+0x04) -#define FLASH_OPTKEYR (FPEC_BASE+0x08) -#define FLASH_SR (FPEC_BASE+0x0C) -#define FLASH_CR (FPEC_BASE+0x10) -#define FLASH_AR (FPEC_BASE+0x14) -#define FLASH_OBR (FPEC_BASE+0x1C) -#define FLASH_WRPR (FPEC_BASE+0x20) -#define FLASH_BANK2_OFFSET 0x40 -#define FLASH_BANK_SPLIT 0x08080000 +// these are common with stm32f1/gd32f1/... +#define FPEC_BASE 0x40022000 +#define FLASH_ACR (FPEC_BASE+0x00) +#define FLASH_KEYR (FPEC_BASE+0x04) +#define FLASH_SR (FPEC_BASE+0x0C) +#define FLASH_CR (FPEC_BASE+0x10) +#define FLASH_AR (FPEC_BASE+0x14) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_SR_BSY (1 << 0) +#define KEY1 0x45670123 +#define KEY2 0xCDEF89AB +#define SR_ERROR_MASK 0x14 +#define SR_EOP 0x20 +#define DBGMCU_IDCODE 0xE0042000 +#define FLASHSIZE 0x1FFFF7E0 -#define FLASH_CR_OBL_LAUNCH (1<<13) -#define FLASH_CR_OPTWRE (1 << 9) -#define FLASH_CR_LOCK (1 << 7) -#define FLASH_CR_STRT (1 << 6) -#define FLASH_CR_OPTER (1 << 5) -#define FLASH_CR_OPTPG (1 << 4) -#define FLASH_CR_MER (1 << 2) -#define FLASH_CR_PER (1 << 1) -#define FLASH_CR_PG (1 << 0) +// these are specific to ch32f1 +#define FLASH_MAGIC (FPEC_BASE+0x34) +#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x +#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock +#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program +#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase +#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load +#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset +#define FLASH_SR_EOP (1<<5) // End of programming +#define FLASH_BEGIN_ADDRESS_CH32 0x8000000 -#define FLASH_OBR_RDPRT (1 << 1) - -#define FLASH_SR_BSY (1 << 0) - -#define FLASH_OBP_RDP 0x1FFFF800 -#define FLASH_OBP_RDP_KEY 0x5aa5 -#define FLASH_OBP_RDP_KEY_F3 0x55AA - -#define KEY1 0x45670123 -#define KEY2 0xCDEF89AB - -#define SR_ERROR_MASK 0x14 -#define SR_EOP 0x20 - -#define DBGMCU_IDCODE 0xE0042000 -#define DBGMCU_IDCODE_F0 0x40015800 - -#define FLASHSIZE 0x1FFFF7E0 -#define FLASHSIZE_F0 0x1FFFF7CC - -#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x - -#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock -#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program -#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase -#define FLASH_CR_BUF_LOAD_CH32 (1<<18) // Buffer load -#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset -#define FLASH_SR_EOP (1<<5) // End of programming -#define FLASH_BEGIN_ADDRESS_CH32 0x8000000 -#define FLASH_MAGIC (FPEC_BASE+0x34) static volatile uint32_t magic,sr,ct; @@ -125,7 +101,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era target_add_flash(t, f); } -#define WAIT_BUSY() do { \ +#define WAIT_BUSY() do { \ sr = target_mem_read32(t, FLASH_SR); \ if(target_check_error(t)) { \ ERROR_CH("ch32f1 flash write: comm error\n"); \ @@ -154,7 +130,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era // Which one is the right value ? #define MAGIC_WORD 0x100 -// #define MAGIC_WORD 0x100 +// #define MAGIC_WORD 0x1000 #define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \ target_mem_write32(t, FLASH_MAGIC , magic); } @@ -172,8 +148,7 @@ static int ch32f1_flash_unlock(target *t) target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1); target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2); uint32_t cr = target_mem_read32(t, FLASH_CR); - if (cr & FLASH_CR_FLOCK_CH32) - { + if (cr & FLASH_CR_FLOCK_CH32){ ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr); return -1; } @@ -267,10 +242,10 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len) static bool ch32f1_wait_flash_ready(target *t,uint32_t adr) { uint32_t ff; - for(int i=0;i<32;i++) { - ff=target_mem_read32(t,adr); + for(int i = 0; i < 32; i++) { + ff = target_mem_read32(t,adr); } - if(ff!=0xffffffffUL) { + if(ff != 0xffffffffUL) { ERROR_CH("ch32f1 Not erased properly at %x or flash access issue\n",adr); return false; } @@ -283,8 +258,8 @@ static bool ch32f1_wait_flash_ready(target *t,uint32_t adr) static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t offset) { - const uint32_t *ss=(const uint32_t *)(src+offset); - uint32_t dd=dest+offset; + const uint32_t *ss = (const uint32_t *)(src+offset); + uint32_t dd = dest+offset; SET_CR(FLASH_CR_FTPG_CH32); target_mem_write32(t, dd+0,ss[0]); @@ -326,7 +301,7 @@ static int ch32f1_flash_write(struct target_flash *f, #endif DEBUG_CH("CH32: flash write 0x%x ,size=%d\n",dest,len); - while(length>0) + while(length > 0) { if(ch32f1_flash_unlock(t)) { ERROR_CH("ch32f1 cannot fast unlock\n"); @@ -340,7 +315,7 @@ static int ch32f1_flash_write(struct target_flash *f, if(!ch32f1_wait_flash_ready(t,dest)) { return -1; } - for(int i=0;i<8;i++) { + for(int i = 0; i < 8; i++) { if(ch32f1_upload(t,dest,src, 16*i)) { ERROR_CH("Cannot upload to buffer\n"); return -1; @@ -357,12 +332,12 @@ static int ch32f1_flash_write(struct target_flash *f, MAGIC((dest)); // next - if(length>128) - length-=128; + if(length > 128) + length -=128; else - length=0; - dest+=128; - src+=128; + length = 0; + dest += 128; + src += 128; sr = target_mem_read32(t, FLASH_SR); // 13 ch32f1_flash_lock(t); @@ -374,8 +349,8 @@ static int ch32f1_flash_write(struct target_flash *f, } #ifdef CH32_VERIFY DEBUG_CH("Verifying\n"); - size_t i=0; - for(i=0;i Date: Thu, 7 Apr 2022 15:45:05 +0200 Subject: [PATCH 5/5] remove static vars --- src/target/ch32f1.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/target/ch32f1.c b/src/target/ch32f1.c index 33c782da..8da38951 100644 --- a/src/target/ch32f1.c +++ b/src/target/ch32f1.c @@ -77,7 +77,7 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff #define FLASH_BEGIN_ADDRESS_CH32 0x8000000 -static volatile uint32_t magic,sr,ct; + /** \fn ch32f1_add_flash @@ -156,6 +156,7 @@ static int ch32f1_flash_unlock(target *t) } static int ch32f1_flash_lock(target *t) { + volatile uint32_t ct; DEBUG_CH("CH32: flash lock \n"); SET_CR(FLASH_CR_LOCK); return 0; @@ -182,8 +183,8 @@ bool ch32f1_probe(target *t) return false; } - uint32_t signature= target_mem_read32(t, FLASHSIZE); - uint32_t flashSize=signature & 0xFFFF; + uint32_t signature = target_mem_read32(t, FLASHSIZE); + uint32_t flashSize = signature & 0xFFFF; target_add_ram(t, 0x20000000, 0x5000); ch32f1_add_flash(t, FLASH_BEGIN_ADDRESS_CH32, flashSize*1024, 128); @@ -197,6 +198,7 @@ bool ch32f1_probe(target *t) */ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len) { + volatile uint32_t ct, sr, magic; target *t = f->t; DEBUG_CH("CH32: flash erase \n"); @@ -258,6 +260,7 @@ static bool ch32f1_wait_flash_ready(target *t,uint32_t adr) static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t offset) { + volatile uint32_t ct, sr, magic; const uint32_t *ss = (const uint32_t *)(src+offset); uint32_t dd = dest+offset; @@ -279,6 +282,7 @@ static int ch32f1_upload(target *t, uint32_t dest, const void *src, uint32_t of */ int ch32f1_buffer_clear(target *t) { + volatile uint32_t ct,sr; SET_CR(FLASH_CR_FTPG_CH32); // Fast page program 4- SET_CR(FLASH_CR_BUF_RESET_CH32); // BUF_RESET 5- WAIT_BUSY(); // 6- @@ -293,6 +297,7 @@ int ch32f1_buffer_clear(target *t) static int ch32f1_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len) { + volatile uint32_t ct, sr, magic; target *t = f->t; size_t length = len; #ifdef CH32_VERIFY