diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index aa993e86..faef4346 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -37,6 +37,8 @@ LGPL License Terms @ref lgpl_license #include +/**@{*/ + /* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 @@ -51,10 +53,7 @@ LGPL License Terms @ref lgpl_license /* ITR1_RMP */ /****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal -Trigger 1 Remap -@ingroup timer_defines - +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Internal Trigger 1 Remap @{*/ /** Internal Trigger 1 remapped to timer 10 output compare */ #define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) @@ -67,9 +66,7 @@ Trigger 1 Remap /* ITR2_RMP */ /****************************************************************************/ -/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap -@ingroup timer_defines - +/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Internal Trigger 2 Remap @{*/ /** Internal Trigger 1 remapped to timer 11 output compare */ #define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) @@ -86,4 +83,6 @@ void timer_set_option(uint32_t timer_peripheral, uint32_t option); END_DECLS +/**@}*/ + #endif diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index fa701dd1..43f8d541 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -38,8 +38,7 @@ Set timer options register on TIM2 or TIM3, used for trigger remapping. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: -@ref tim3_opt_trigger_remap. +@param[in] option Desired option @ref tim2_opt_trigger_remap and @ref tim3_opt_trigger_remap */ void timer_set_option(uint32_t timer_peripheral, uint32_t option)