From 2e25d678bad00ceb9ab8ce46d3aa9df3254096da Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 15 Oct 2015 01:03:18 +0000 Subject: [PATCH] Surround all macro parameters with () Followup from c72f3d588a637101262d5e2b276dc6cc5d926a6d --- include/libopencm3/lm4f/usb.h | 6 ++--- .../libopencm3/stm32/common/i2c_common_all.h | 18 +++++++-------- include/libopencm3/stm32/f0/adc.h | 18 +++++++-------- include/libopencm3/stm32/f0/i2c.h | 22 +++++++++---------- include/libopencm3/stm32/f3/i2c.h | 22 +++++++++---------- include/libopencm3/stm32/l0/timer.h | 18 +++++++-------- include/libopencm3/stm32/otg_common.h | 2 +- include/libopencm3/stm32/tools.h | 16 +++++++------- lib/lm4f/gpio.c | 4 ++-- lib/stm32/common/timer_common_all.c | 4 ++-- 10 files changed, 65 insertions(+), 65 deletions(-) diff --git a/include/libopencm3/lm4f/usb.h b/include/libopencm3/lm4f/usb.h index 2a4cd2ad..0463d4b1 100644 --- a/include/libopencm3/lm4f/usb.h +++ b/include/libopencm3/lm4f/usb.h @@ -79,9 +79,9 @@ #define USB_TEST MMIO8(USB_BASE + 0x0F) /* USB FIFO Endpoint [0-7] */ -#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04) -#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04) -#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04) +#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + (n)*0x04) +#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + (n)*0x04) +#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + (n)*0x04) /* USB Transmit Dynamic FIFO Sizing */ #define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62) diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_all.h index a5fc8ae6..42acea0c 100644 --- a/include/libopencm3/stm32/common/i2c_common_all.h +++ b/include/libopencm3/stm32/common/i2c_common_all.h @@ -49,47 +49,47 @@ specific memorymap.h header before including this header file.*/ /* --- I2C registers ------------------------------------------------------- */ /* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) /* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) /* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) /* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) /* Data register (I2Cx_DR) */ -#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C_DR(i2c_base) MMIO32((i2c_base) + 0x10) #define I2C1_DR I2C_DR(I2C1) #define I2C2_DR I2C_DR(I2C2) /* Status register 1 (I2Cx_SR1) */ -#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C_SR1(i2c_base) MMIO32((i2c_base) + 0x14) #define I2C1_SR1 I2C_SR1(I2C1) #define I2C2_SR1 I2C_SR1(I2C2) /* Status register 2 (I2Cx_SR2) */ -#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C_SR2(i2c_base) MMIO32((i2c_base) + 0x18) #define I2C1_SR2 I2C_SR2(I2C1) #define I2C2_SR2 I2C_SR2(I2C2) /* Clock control register (I2Cx_CCR) */ -#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C_CCR(i2c_base) MMIO32((i2c_base) + 0x1c) #define I2C1_CCR I2C_CCR(I2C1) #define I2C2_CCR I2C_CCR(I2C2) /* TRISE register (I2Cx_CCR) */ -#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C_TRISE(i2c_base) MMIO32((i2c_base) + 0x20) #define I2C1_TRISE I2C_TRISE(I2C1) #define I2C2_TRISE I2C_TRISE(I2C2) diff --git a/include/libopencm3/stm32/f0/adc.h b/include/libopencm3/stm32/f0/adc.h index c76fefbc..169f817e 100644 --- a/include/libopencm3/stm32/f0/adc.h +++ b/include/libopencm3/stm32/f0/adc.h @@ -50,45 +50,45 @@ /*****************************************************************************/ /* ADC interrupt and status register */ -#define ADC_ISR(base) MMIO32(base + 0x00) +#define ADC_ISR(base) MMIO32((base) + 0x00) #define ADC1_ISR ADC_ISR(ADC) /* Interrupt Enable Register */ -#define ADC_IER(base) MMIO32(base + 0x04) +#define ADC_IER(base) MMIO32((base) + 0x04) #define ADC1_IER ADC_IER(ADC) /* Control Register */ -#define ADC_CR(base) MMIO32(base + 0x08) +#define ADC_CR(base) MMIO32((base) + 0x08) #define ADC1_CR ADC_CR(ADC) /* Configuration Register 1 */ -#define ADC_CFGR1(base) MMIO32(base + 0x0C) +#define ADC_CFGR1(base) MMIO32((base) + 0x0C) #define ADC1_CFGR1 ADC_CFGR1(ADC) /* Configuration Register 2 */ -#define ADC_CFGR2(base) MMIO32(base + 0x10) +#define ADC_CFGR2(base) MMIO32((base) + 0x10) #define ADC1_CFGR2 ADC_CFGR2(ADC) /* Sample Time Register 1 */ -#define ADC_SMPR(base) MMIO32(base + 0x14) +#define ADC_SMPR(base) MMIO32((base) + 0x14) #define ADC1_SMPR ADC_SMPR(ADC) /* Watchdog Threshold Register */ -#define ADC_TR(base) MMIO32(base + 0x20) +#define ADC_TR(base) MMIO32((base) + 0x20) #define ADC1_TR ADC_TR(ADC) /* Channel Select Register */ -#define ADC_CHSELR(base) MMIO32(base + 0x28) +#define ADC_CHSELR(base) MMIO32((base) + 0x28) #define ADC1_CHSELR ADC_CHSELR(ADC) /* Regular Data Register */ -#define ADC_DR(base) MMIO32(base + 0x40) +#define ADC_DR(base) MMIO32((base) + 0x40) #define ADC1_DR ADC_DR(ADC) diff --git a/include/libopencm3/stm32/f0/i2c.h b/include/libopencm3/stm32/f0/i2c.h index 06ff2dd9..ea7d98d3 100644 --- a/include/libopencm3/stm32/f0/i2c.h +++ b/include/libopencm3/stm32/f0/i2c.h @@ -43,47 +43,47 @@ /* Register definitions */ /*****************************************************************************/ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) -#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C_TIMINGR(i2c_base) MMIO32((i2c_base) + 0x10) #define I2C1_TIMINGR I2C_TIMINGR(I2C1) #define I2C2_TIMINGR I2C_TIMINGR(I2C2) -#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C_TIMEOUTR(i2c_base) MMIO32((i2c_base) + 0x14) #define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) #define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) -#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C_ISR(i2c_base) MMIO32((i2c_base) + 0x18) #define I2C1_ISR I2C_ISR(I2C1) #define I2C2_ISR I2C_ISR(I2C2) -#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) +#define I2C_ICR(i2c_base) MMIO32((i2c_base) + 0x1C) #define I2C1_ICR I2C_ICR(I2C1) #define I2C2_ICR I2C_ICR(I2C2) -#define I2C_PECR(i2c_base) MMIO8(i2c_base + 0x20) +#define I2C_PECR(i2c_base) MMIO8((i2c_base) + 0x20) #define I2C1_PECR I2C_PECR(I2C1) #define I2C2_PECR I2C_PECR(I2C2) -#define I2C_RXDR(i2c_base) MMIO8(i2c_base + 0x24) +#define I2C_RXDR(i2c_base) MMIO8((i2c_base) + 0x24) #define I2C1_RXDR I2C_RXDR(I2C1) #define I2C2_RXDR I2C_RXDR(I2C2) -#define I2C_TXDR(i2c_base) MMIO8(i2c_base + 0x28) +#define I2C_TXDR(i2c_base) MMIO8((i2c_base) + 0x28) #define I2C1_TXDR I2C_TXDR(I2C1) #define I2C2_TXDR I2C_TXDR(I2C2) diff --git a/include/libopencm3/stm32/f3/i2c.h b/include/libopencm3/stm32/f3/i2c.h index a16ff959..6554d680 100644 --- a/include/libopencm3/stm32/f3/i2c.h +++ b/include/libopencm3/stm32/f3/i2c.h @@ -47,57 +47,57 @@ /* --- I2C registers ------------------------------------------------------- */ /* Control register 1 (I2Cx_CR1) */ -#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00) #define I2C1_CR1 I2C_CR1(I2C1) #define I2C2_CR1 I2C_CR1(I2C2) /* Control register 2 (I2Cx_CR2) */ -#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04) #define I2C1_CR2 I2C_CR2(I2C1) #define I2C2_CR2 I2C_CR2(I2C2) /* Own address register 1 (I2Cx_OAR1) */ -#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08) #define I2C1_OAR1 I2C_OAR1(I2C1) #define I2C2_OAR1 I2C_OAR1(I2C2) /* Own address register 2 (I2Cx_OAR2) */ -#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c) #define I2C1_OAR2 I2C_OAR2(I2C1) #define I2C2_OAR2 I2C_OAR2(I2C2) /* Timing register (I2Cx_TIMINGR) */ -#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C_TIMINGR(i2c_base) MMIO32((i2c_base) + 0x10) #define I2C1_TIMINGR I2C_TIMINGR(I2C1) #define I2C2_TIMINGR I2C_TIMINGR(I2C2) /* Timeout register (I2Cx_TIMEOUTR) */ -#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C_TIMEOUTR(i2c_base) MMIO32((i2c_base) + 0x14) #define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) #define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) /* Interrupt and Status register (I2Cx_ISR) */ -#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C_ISR(i2c_base) MMIO32((i2c_base) + 0x18) #define I2C1_ISR I2C_ISR(I2C1) #define I2C2_ISR I2C_ISR(I2C2) /* Interrupt clear register (I2Cx_ICR) */ -#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) +#define I2C_ICR(i2c_base) MMIO32((i2c_base) + 0x1C) #define I2C1_ICR I2C_ICR(I2C1) #define I2C2_ICR I2C_ICR(I2C2) /* PEC register (I2Cx_PECR) */ -#define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C_PECR(i2c_base) MMIO32((i2c_base) + 0x20) #define I2C1_PECR I2C_PECR(I2C1) #define I2C2_PECR I2C_PECR(I2C2) /* Receive data register (I2Cx_RXDR) */ -#define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24) +#define I2C_RXDR(i2c_base) MMIO32((i2c_base) + 0x24) #define I2C1_RXDR I2C_RXDR(I2C1) #define I2C2_RXDR I2C_RXDR(I2C2) /* Transmit data register (I2Cx_TXDR) */ -#define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28) +#define I2C_TXDR(i2c_base) MMIO32((i2c_base) + 0x28) #define I2C1_TXDR I2C_TXDR(I2C1) #define I2C2_TXDR I2C_TXDR(I2C2) diff --git a/include/libopencm3/stm32/l0/timer.h b/include/libopencm3/stm32/l0/timer.h index ba140a7d..c2ed35a8 100644 --- a/include/libopencm3/stm32/l0/timer.h +++ b/include/libopencm3/stm32/l0/timer.h @@ -39,7 +39,7 @@ LGPL License Terms @ref lgpl_license /* Timer 2/21/22 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM21_OR TIM_OR(TIM21) #define TIM22_OR TIM_OR(TIM22) @@ -96,14 +96,14 @@ LGPL License Terms @ref lgpl_license /* --- LPTIM (low power timer) ------------------------------------------- */ -#define LPTIM_ISR(tim_base) MMIO32(tim_base + 0x00) -#define LPTIM_ICR(tim_base) MMIO32(tim_base + 0x04) -#define LPTIM_IER(tim_base) MMIO32(tim_base + 0x08) -#define LPTIM_CFGR(tim_base) MMIO32(tim_base + 0x0C) -#define LPTIM_CR(tim_base) MMIO32(tim_base + 0x10) -#define LPTIM_CMP(tim_base) MMIO32(tim_base + 0x14) -#define LPTIM_ARR(tim_base) MMIO32(tim_base + 0x18) -#define LPTIM_CNT(tim_base) MMIO32(tim_base + 0x1C) +#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) +#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) +#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) +#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) +#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) +#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) +#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) +#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) #define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) #define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) diff --git a/include/libopencm3/stm32/otg_common.h b/include/libopencm3/stm32/otg_common.h index 7a2e39d5..e5732051 100644 --- a/include/libopencm3/stm32/otg_common.h +++ b/include/libopencm3/stm32/otg_common.h @@ -42,7 +42,7 @@ #define OTG_GCCFG 0x038 #define OTG_CID 0x03C #define OTG_HPTXFSIZ 0x100 -#define OTG_DIEPTXF(x) (0x104 + 4*(x-1)) +#define OTG_DIEPTXF(x) (0x104 + 4*((x)-1)) /* Host-mode Control and Status Registers */ #define OTG_HCFG 0x400 diff --git a/include/libopencm3/stm32/tools.h b/include/libopencm3/stm32/tools.h index 807aa60b..af9f66ba 100644 --- a/include/libopencm3/stm32/tools.h +++ b/include/libopencm3/stm32/tools.h @@ -25,23 +25,23 @@ */ /* Get register content. */ -#define GET_REG(REG) ((uint16_t) *REG) +#define GET_REG(REG) ((uint16_t) *(REG)) /* Set register content. */ -#define SET_REG(REG, VAL) (*REG = (uint16_t)VAL) +#define SET_REG(REG, VAL) (*(REG) = (uint16_t)(VAL)) /* Clear register bit. */ -#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) +#define CLR_REG_BIT(REG, BIT) SET_REG((REG), (~(BIT))) /* Clear register bit masking out some bits that must not be touched. */ #define CLR_REG_BIT_MSK_AND_SET(REG, MSK, BIT, EXTRA_BITS) \ - SET_REG(REG, (GET_REG(REG) & MSK & (~BIT)) | (EXTRA_BITS)) + SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS)) #define CLR_REG_BIT_MSK(REG, MSK, BIT) \ - CLR_REG_BIT_MSK_AND_SET(REG, MSK, BIT, 0) + CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0) /* Get masked out bit value. */ -#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) +#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & (BIT)) /* * Set/reset a bit in a masked window by using toggle mechanism. @@ -62,10 +62,10 @@ do { \ toggle_mask ^= bit_selector; \ } \ } \ - SET_REG(REG, toggle_mask | (EXTRA_BITS)); \ + SET_REG((REG), toggle_mask | (EXTRA_BITS)); \ } while (0) #define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ - TOG_SET_REG_BIT_MSK_AND_SET(REG, MSK, BIT, 0) + TOG_SET_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0) #endif diff --git a/lib/lm4f/gpio.c b/lib/lm4f/gpio.c index 22399bd8..0a103cf5 100644 --- a/lib/lm4f/gpio.c +++ b/lib/lm4f/gpio.c @@ -299,8 +299,8 @@ void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype, } } -#define PCTL_AF(pin, af) (af << (pin << 2)) -#define PCTL_MASK(pin) PCTL_AF(pin, 0xf) +#define PCTL_AF(pin, af) ((af) << ((pin) << 2)) +#define PCTL_MASK(pin) PCTL_AF((pin), 0xf) /** * \brief Multiplex group of pins to the given alternate function * diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index ac187742..c24bd6ba 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -117,9 +117,9 @@ knob. #define ADVANCED_TIMERS (defined(TIM1_BASE) || defined(TIM8_BASE)) #if defined(TIM8) -#define TIMER_IS_ADVANCED(periph) ((periph == TIM1) || (periph == TIM8)) +#define TIMER_IS_ADVANCED(periph) (((periph) == TIM1) || ((periph) == TIM8)) #else -#define TIMER_IS_ADVANCED(periph) (periph == TIM1) +#define TIMER_IS_ADVANCED(periph) ((periph) == TIM1) #endif /*---------------------------------------------------------------------------*/