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[flash] f2: use "proper" bit definition naming.

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Part 3 of 4: updated f2 to use flash_<reg>_bit instead of just
flash_bit
This commit is contained in:
Karl Palsson 2013-01-23 13:25:28 +00:00
parent 1eb4e6ed29
commit 316b068cb4
3 changed files with 93 additions and 93 deletions
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112
include/libopencm3/stm32/f2/flash.h
View File

@ -43,76 +43,76 @@
/* --- FLASH_ACR values ---------------------------------------------------- */ /* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_DCRST (1 << 12) #define FLASH_ACR_DCRST (1 << 12)
#define FLASH_ICRST (1 << 11) #define FLASH_ACR_ICRST (1 << 11)
#define FLASH_DCE (1 << 10) #define FLASH_ACR_DCE (1 << 10)
#define FLASH_ICE (1 << 9) #define FLASH_ACR_ICE (1 << 9)
#define FLASH_PRFTEN (1 << 8) #define FLASH_ACR_PRFTEN (1 << 8)
#define FLASH_LATENCY_0WS 0x00 #define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_LATENCY_1WS 0x01 #define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_LATENCY_2WS 0x02 #define FLASH_ACR_LATENCY_2WS 0x02
#define FLASH_LATENCY_3WS 0x03 #define FLASH_ACR_LATENCY_3WS 0x03
#define FLASH_LATENCY_4WS 0x04 #define FLASH_ACR_LATENCY_4WS 0x04
#define FLASH_LATENCY_5WS 0x05 #define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_LATENCY_6WS 0x06 #define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_LATENCY_7WS 0x07 #define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */ /* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_BSY (1 << 16) #define FLASH_SR_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7) #define FLASH_SR_PGSERR (1 << 7)
#define FLASH_PGPERR (1 << 6) #define FLASH_SR_PGPERR (1 << 6)
#define FLASH_PGAERR (1 << 5) #define FLASH_SR_PGAERR (1 << 5)
#define FLASH_WRPERR (1 << 4) #define FLASH_SR_WRPERR (1 << 4)
#define FLASH_OPERR (1 << 1) #define FLASH_SR_OPERR (1 << 1)
#define FLASH_EOP (1 << 0) #define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */ /* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_LOCK (1 << 31) #define FLASH_CR_LOCK (1 << 31)
#define FLASH_ERRIE (1 << 25) #define FLASH_CR_ERRIE (1 << 25)
#define FLASH_EOPIE (1 << 24) #define FLASH_CR_EOPIE (1 << 24)
#define FLASH_STRT (1 << 16) #define FLASH_CR_STRT (1 << 16)
#define FLASH_MER (1 << 2) #define FLASH_CR_MER (1 << 2)
#define FLASH_SER (1 << 1) #define FLASH_CR_SER (1 << 1)
#define FLASH_PG (1 << 0) #define FLASH_CR_PG (1 << 0)
#define FLASH_SECTOR_0 (0x00 << 3) #define FLASH_CR_SECTOR_0 (0x00 << 3)
#define FLASH_SECTOR_1 (0x01 << 3) #define FLASH_CR_SECTOR_1 (0x01 << 3)
#define FLASH_SECTOR_2 (0x02 << 3) #define FLASH_CR_SECTOR_2 (0x02 << 3)
#define FLASH_SECTOR_3 (0x03 << 3) #define FLASH_CR_SECTOR_3 (0x03 << 3)
#define FLASH_SECTOR_4 (0x04 << 3) #define FLASH_CR_SECTOR_4 (0x04 << 3)
#define FLASH_SECTOR_5 (0x05 << 3) #define FLASH_CR_SECTOR_5 (0x05 << 3)
#define FLASH_SECTOR_6 (0x06 << 3) #define FLASH_CR_SECTOR_6 (0x06 << 3)
#define FLASH_SECTOR_7 (0x07 << 3) #define FLASH_CR_SECTOR_7 (0x07 << 3)
#define FLASH_SECTOR_8 (0x08 << 3) #define FLASH_CR_SECTOR_8 (0x08 << 3)
#define FLASH_SECTOR_9 (0x09 << 3) #define FLASH_CR_SECTOR_9 (0x09 << 3)
#define FLASH_SECTOR_10 (0x0a << 3) #define FLASH_CR_SECTOR_10 (0x0a << 3)
#define FLASH_SECTOR_11 (0x0b << 3) #define FLASH_CR_SECTOR_11 (0x0b << 3)
#define FLASH_PROGRAM_X8 (0x00 << 8) #define FLASH_CR_PROGRAM_X8 (0x00 << 8)
#define FLASH_PROGRAM_X16 (0x01 << 8) #define FLASH_CR_PROGRAM_X16 (0x01 << 8)
#define FLASH_PROGRAM_X32 (0x02 << 8) #define FLASH_CR_PROGRAM_X32 (0x02 << 8)
#define FLASH_PROGRAM_X64 (0x03 << 8) #define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */ /* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */ /* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */ /* FLASH_OBR[15:8]: RDP */
#define FLASH_NRST_STDBY (1 << 7) #define FLASH_OPTCR_NRST_STDBY (1 << 7)
#define FLASH_NRST_STOP (1 << 6) #define FLASH_OPTCR_NRST_STOP (1 << 6)
#define FLASH_WDG_SW (1 << 5) #define FLASH_OPTCR_WDG_SW (1 << 5)
#define FLASH_OPTSTRT (1 << 1) #define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTLOCK (1 << 0) #define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_BOR_LEVEL_3 (0x00 << 2) #define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_BOR_LEVEL_2 (0x01 << 2) #define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_BOR_LEVEL_1 (0x02 << 2) #define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_BOR_OFF (0x03 << 2) #define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/ /* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEY1 ((u32)0x45670123) #define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEY2 ((u32)0xcdef89ab) #define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEY1 ((u32)0x08192a3b) #define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEY2 ((u32)0x4c5d6e7f) #define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */

72
lib/stm32/f2/flash.c
View File

@ -28,42 +28,42 @@ static inline void flash_set_program_size(u32 psize)
void flash_data_cache_enable(void) void flash_data_cache_enable(void)
{ {
FLASH_ACR |= FLASH_DCE; FLASH_ACR |= FLASH_ACR_DCE;
} }
void flash_dcache_disable(void) void flash_dcache_disable(void)
{ {
FLASH_ACR &= ~FLASH_DCE; FLASH_ACR &= ~FLASH_ACR_DCE;
} }
void flash_icache_enable(void) void flash_icache_enable(void)
{ {
FLASH_ACR |= FLASH_ICE; FLASH_ACR |= FLASH_ACR_ICE;
} }
void flash_icache_disable(void) void flash_icache_disable(void)
{ {
FLASH_ACR &= ~FLASH_ICE; FLASH_ACR &= ~FLASH_ACR_ICE;
} }
void flash_prefetch_enable(void) void flash_prefetch_enable(void)
{ {
FLASH_ACR |= FLASH_PRFTEN; FLASH_ACR |= FLASH_ACR_PRFTEN;
} }
void flash_prefetch_disable(void) void flash_prefetch_disable(void)
{ {
FLASH_ACR &= ~FLASH_PRFTEN; FLASH_ACR &= ~FLASH_ACR_PRFTEN;
} }
void flash_dcache_reset(void) void flash_dcache_reset(void)
{ {
FLASH_ACR |= FLASH_DCRST; FLASH_ACR |= FLASH_ACR_DCRST;
} }
void flash_icache_reset(void) void flash_icache_reset(void)
{ {
FLASH_ACR |= FLASH_ICRST; FLASH_ACR |= FLASH_ACR_ICRST;
} }
void flash_set_ws(u32 ws) void flash_set_ws(u32 ws)
@ -79,43 +79,43 @@ void flash_set_ws(u32 ws)
void flash_unlock(void) void flash_unlock(void)
{ {
/* Authorize the FPEC access. */ /* Authorize the FPEC access. */
FLASH_KEYR = FLASH_KEY1; FLASH_KEYR = FLASH_KEYR_KEY1;
FLASH_KEYR = FLASH_KEY2; FLASH_KEYR = FLASH_KEYR_KEY2;
} }
void flash_lock(void) void flash_lock(void)
{ {
FLASH_CR |= FLASH_LOCK; FLASH_CR |= FLASH_CR_LOCK;
} }
void flash_clear_pgserr_flag(void) void flash_clear_pgserr_flag(void)
{ {
FLASH_SR |= FLASH_PGSERR; FLASH_SR |= FLASH_SR_PGSERR;
} }
void flash_clear_pgperr_flag(void) void flash_clear_pgperr_flag(void)
{ {
FLASH_SR |= FLASH_PGPERR; FLASH_SR |= FLASH_SR_PGPERR;
} }
void flash_clear_pgaerr_flag(void) void flash_clear_pgaerr_flag(void)
{ {
FLASH_SR |= FLASH_PGAERR; FLASH_SR |= FLASH_SR_PGAERR;
} }
void flash_clear_eop_flag(void) void flash_clear_eop_flag(void)
{ {
FLASH_SR |= FLASH_EOP; FLASH_SR |= FLASH_SR_EOP;
} }
void flash_clear_wrperr_flag(void) void flash_clear_wrperr_flag(void)
{ {
FLASH_SR |= FLASH_WRPERR; FLASH_SR |= FLASH_SR_WRPERR;
} }
void flash_clear_bsy_flag(void) void flash_clear_bsy_flag(void)
{ {
FLASH_SR &= ~FLASH_BSY; FLASH_SR &= ~FLASH_SR_BSY;
} }
void flash_clear_status_flags(void) void flash_clear_status_flags(void)
@ -130,18 +130,18 @@ void flash_clear_status_flags(void)
void flash_unlock_option_bytes(void) void flash_unlock_option_bytes(void)
{ {
FLASH_OPTKEYR = FLASH_OPTKEY1; FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
FLASH_OPTKEYR = FLASH_OPTKEY2; FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
} }
void flash_lock_option_bytes(void) void flash_lock_option_bytes(void)
{ {
FLASH_OPTCR |= FLASH_OPTLOCK; FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
} }
void flash_wait_for_last_operation(void) void flash_wait_for_last_operation(void)
{ {
while ((FLASH_SR & FLASH_BSY) == FLASH_BSY) while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
; ;
} }
@ -152,7 +152,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_set_program_size(program_size); flash_set_program_size(program_size);
/* Enable writes to flash. */ /* Enable writes to flash. */
FLASH_CR |= FLASH_PG; FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */ /* Program the first half of the word. */
MMIO64(address) = data; MMIO64(address) = data;
@ -161,7 +161,7 @@ void flash_program_double_word(u32 address, u64 data, u32 program_size)
flash_wait_for_last_operation(); flash_wait_for_last_operation();
/* Disable writes to flash. */ /* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG; FLASH_CR &= ~FLASH_CR_PG;
} }
void flash_program_word(u32 address, u32 data, u32 program_size) void flash_program_word(u32 address, u32 data, u32 program_size)
@ -171,7 +171,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_set_program_size(program_size); flash_set_program_size(program_size);
/* Enable writes to flash. */ /* Enable writes to flash. */
FLASH_CR |= FLASH_PG; FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */ /* Program the first half of the word. */
MMIO32(address) = data; MMIO32(address) = data;
@ -180,7 +180,7 @@ void flash_program_word(u32 address, u32 data, u32 program_size)
flash_wait_for_last_operation(); flash_wait_for_last_operation();
/* Disable writes to flash. */ /* Disable writes to flash. */
FLASH_CR &= ~FLASH_PG; FLASH_CR &= ~FLASH_CR_PG;
} }
void flash_program_half_word(u32 address, u16 data, u32 program_size) void flash_program_half_word(u32 address, u16 data, u32 program_size)
@ -188,13 +188,13 @@ void flash_program_half_word(u32 address, u16 data, u32 program_size)
flash_wait_for_last_operation(); flash_wait_for_last_operation();
flash_set_program_size(program_size); flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG; FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data; MMIO16(address) = data;
flash_wait_for_last_operation(); flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
} }
void flash_program_byte(u32 address, u8 data, u32 program_size) void flash_program_byte(u32 address, u8 data, u32 program_size)
@ -202,13 +202,13 @@ void flash_program_byte(u32 address, u8 data, u32 program_size)
flash_wait_for_last_operation(); flash_wait_for_last_operation();
flash_set_program_size(program_size); flash_set_program_size(program_size);
FLASH_CR |= FLASH_PG; FLASH_CR |= FLASH_CR_PG;
MMIO8(address) = data; MMIO8(address) = data;
flash_wait_for_last_operation(); flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */ FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
} }
void flash_erase_sector(u32 sector, u32 program_size) void flash_erase_sector(u32 sector, u32 program_size)
@ -218,10 +218,10 @@ void flash_erase_sector(u32 sector, u32 program_size)
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
FLASH_CR |= sector; FLASH_CR |= sector;
FLASH_CR |= FLASH_STRT; FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation(); flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_SER; FLASH_CR &= ~FLASH_CR_SER;
FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3); FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
} }
@ -230,21 +230,21 @@ void flash_erase_all_sectors(u32 program_size)
flash_wait_for_last_operation(); flash_wait_for_last_operation();
flash_set_program_size(program_size); flash_set_program_size(program_size);
FLASH_CR |= FLASH_MER; /* Enable mass erase. */ FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
FLASH_CR |= FLASH_STRT; /* Trigger the erase. */ FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
flash_wait_for_last_operation(); flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */ FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
} }
void flash_program_option_bytes(u32 data) void flash_program_option_bytes(u32 data)
{ {
flash_wait_for_last_operation(); flash_wait_for_last_operation();
if (FLASH_OPTCR & FLASH_OPTLOCK) if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
flash_unlock_option_bytes(); flash_unlock_option_bytes();
FLASH_OPTCR = data & ~0x3; FLASH_OPTCR = data & ~0x3;
FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */ FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
flash_wait_for_last_operation(); flash_wait_for_last_operation();
} }

2
lib/stm32/f2/rcc.c
View File

@ -37,7 +37,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000, .apb1_frequency = 30000000,
.apb2_frequency = 60000000, .apb2_frequency = 60000000,
}, },