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Changed to use stdint types.

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This commit is contained in:
Piotr Esden-Tempski 2013-06-12 19:11:22 -07:00
parent 7df63fcae0
commit 34de1e776e
127 changed files with 1886 additions and 1895 deletions
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17
include/libopencm3/cm3/common.h
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@ -23,15 +23,6 @@
#include <stdint.h>
#include <stdbool.h>
/* Type definitions for shorter and nicer code */
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
/* This must be placed around external function declaration for C++
* support. */
#ifdef __cplusplus
@ -56,10 +47,10 @@ typedef uint64_t u64;
/* Generic memory-mapped I/O accessor functions */
#define MMIO8(addr) (*(volatile u8 *)(addr))
#define MMIO16(addr) (*(volatile u16 *)(addr))
#define MMIO32(addr) (*(volatile u32 *)(addr))
#define MMIO64(addr) (*(volatile u64 *)(addr))
#define MMIO8(addr) (*(volatile uint8_t *)(addr))
#define MMIO16(addr) (*(volatile uint16_t *)(addr))
#define MMIO32(addr) (*(volatile uint32_t *)(addr))
#define MMIO64(addr) (*(volatile uint64_t *)(addr))
/* Generic bit definition */
#define BIT0 (1<<0)

2
include/libopencm3/cm3/fpb.h
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@ -33,7 +33,7 @@
#define FPB_REMAP MMIO32(FPB_BASE + 4)
/* Flash Patch Comparator (FPB_COMPx) */
#define FPB_COMP (volatile u32 *)(FPB_BASE + 8)
#define FPB_COMP (volatile uint32_t *)(FPB_BASE + 8)
/* TODO: PID, CID */

4
include/libopencm3/cm3/itm.h
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@ -25,10 +25,10 @@
/* --- ITM registers ------------------------------------------------------- */
/* Stimulus Port x (ITM_STIM[x]) */
#define ITM_STIM ((volatile u32*)(ITM_BASE))
#define ITM_STIM ((volatile uint32_t*)(ITM_BASE))
/* Trace Enable ports (ITM_TER[x]) */
#define ITM_TER ((volatile u32*)(ITM_BASE + 0xE00))
#define ITM_TER ((volatile uint32_t*)(ITM_BASE + 0xE00))
/* Trace Privilege (ITM_TPR) */
#define ITM_TPR MMIO32(ITM_BASE + 0xE40)

18
include/libopencm3/cm3/nvic.h
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@ -118,15 +118,15 @@ IRQ numbers -3 and -6 to -9 are reserved
BEGIN_DECLS
void nvic_enable_irq(u8 irqn);
void nvic_disable_irq(u8 irqn);
u8 nvic_get_pending_irq(u8 irqn);
void nvic_set_pending_irq(u8 irqn);
void nvic_clear_pending_irq(u8 irqn);
u8 nvic_get_active_irq(u8 irqn);
u8 nvic_get_irq_enabled(u8 irqn);
void nvic_set_priority(u8 irqn, u8 priority);
void nvic_generate_software_interrupt(u16 irqn);
void nvic_enable_irq(uint8_t irqn);
void nvic_disable_irq(uint8_t irqn);
uint8_t nvic_get_pending_irq(uint8_t irqn);
void nvic_set_pending_irq(uint8_t irqn);
void nvic_clear_pending_irq(uint8_t irqn);
uint8_t nvic_get_active_irq(uint8_t irqn);
uint8_t nvic_get_irq_enabled(uint8_t irqn);
void nvic_set_priority(uint8_t irqn, uint8_t priority);
void nvic_generate_software_interrupt(uint16_t irqn);
void WEAK reset_handler(void);
void WEAK nmi_handler(void);

18
include/libopencm3/cm3/scb.h
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@ -366,14 +366,14 @@
BEGIN_DECLS
struct scb_exception_stack_frame {
u32 r0;
u32 r1;
u32 r2;
u32 r3;
u32 r12;
u32 lr;
u32 pc;
u32 xpsr;
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
} __packed;
#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
@ -384,7 +384,7 @@ struct scb_exception_stack_frame {
void scb_reset_core(void) __attribute__((noreturn, naked));
void scb_reset_system(void) __attribute__((noreturn, naked));
void scb_set_priority_grouping(u32 prigroup);
void scb_set_priority_grouping(uint32_t prigroup);
/* TODO: */

6
include/libopencm3/cm3/sync.h
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@ -29,15 +29,15 @@
/* --- Exclusive load and store instructions ------------------------------- */
u32 __ldrex(volatile u32 *addr);
u32 __strex(u32 val, volatile u32 *addr);
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);
void __dmb(void);
/* --- Convenience functions ----------------------------------------------- */
/* Here we implement some simple synchronisation primatives. */
typedef u32 mutex_t;
typedef uint32_t mutex_t;
#define MUTEX_UNLOCKED 0
#define MUTEX_LOCKED 1

12
include/libopencm3/cm3/systick.h
View File

@ -95,17 +95,17 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void systick_set_reload(u32 value);
u32 systick_get_reload(void);
u32 systick_get_value(void);
void systick_set_clocksource(u8 clocksource);
void systick_set_reload(uint32_t value);
uint32_t systick_get_reload(void);
uint32_t systick_get_value(void);
void systick_set_clocksource(uint8_t clocksource);
void systick_interrupt_enable(void);
void systick_interrupt_disable(void);
void systick_counter_enable(void);
void systick_counter_disable(void);
u8 systick_get_countflag(void);
uint8_t systick_get_countflag(void);
u32 systick_get_calib(void);
uint32_t systick_get_calib(void);
END_DECLS

6
include/libopencm3/lm3s/gpio.h
View File

@ -64,7 +64,7 @@ LGPL License Terms @ref lgpl_license
/* --- GPIO registers ------------------------------------------------------ */
#define GPIO_DATA(port) ((volatile u32 *)(port + 0x000))
#define GPIO_DATA(port) ((volatile uint32_t *)(port + 0x000))
#define GPIO_DIR(port) MMIO32(port + 0x400)
#define GPIO_IS(port) MMIO32(port + 0x404)
#define GPIO_IBE(port) MMIO32(port + 0x408)
@ -88,8 +88,8 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void gpio_set(u32 gpioport, u8 gpios);
void gpio_clear(u32 gpioport, u8 gpios);
void gpio_set(uint32_t gpioport, uint8_t gpios);
void gpio_clear(uint32_t gpioport, uint8_t gpios);
END_DECLS

38
include/libopencm3/lm4f/gpio.h
View File

@ -90,7 +90,7 @@
* ---------------------------------------------------------------------------*/
/* GPIO Data */
#define GPIO_DATA(port) ((volatile u32 *)(port + 0x000))
#define GPIO_DATA(port) ((volatile uint32_t *)(port + 0x000))
/* GPIO Direction */
#define GPIO_DIR(port) MMIO32(port + 0x400)
@ -217,14 +217,14 @@ enum gpio_trigger {
BEGIN_DECLS
void gpio_enable_ahb_aperture(void);
void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
u8 gpios);
void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, u8 gpios);
void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios);
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
uint8_t gpios);
void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, uint8_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios);
void gpio_toggle(u32 gpioport, u8 gpios);
void gpio_unlock_commit(u32 gpioport, u8 gpios);
void gpio_toggle(uint32_t gpioport, uint8_t gpios);
void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios);
/* Let's keep these ones inlined. GPIO control should be fast */
/** @ingroup gpio_control
@ -246,7 +246,7 @@ void gpio_unlock_commit(u32 gpioport, u8 gpios);
* @return The level of the GPIO port. The pins not specified in gpios are
* masked to zero.
*/
static inline u8 gpio_read(u32 gpioport, u8 gpios)
static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios)
{
return GPIO_DATA(gpioport)[gpios];
}
@ -266,7 +266,7 @@ static inline u8 gpio_read(u32 gpioport, u8 gpios)
* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
* 1 to GPIO1. and so on.
*/
static inline void gpio_write(u32 gpioport, u8 gpios, u8 data)
static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data)
{
/* ipaddr[9:2] mask the bits to be set, hence the array index */
GPIO_DATA(gpioport)[gpios] = data;
@ -281,7 +281,7 @@ static inline void gpio_write(u32 gpioport, u8 gpios, u8 data)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_set(u32 gpioport, u8 gpios)
static inline void gpio_set(uint32_t gpioport, uint8_t gpios)
{
gpio_write(gpioport, gpios, 0xff);
}
@ -295,7 +295,7 @@ static inline void gpio_set(u32 gpioport, u8 gpios)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_clear(u32 gpioport, u8 gpios)
static inline void gpio_clear(uint32_t gpioport, uint8_t gpios)
{
gpio_write(gpioport, gpios, 0);
}
@ -311,7 +311,7 @@ static inline void gpio_clear(u32 gpioport, u8 gpios)
*
* @return The level of all the pins on the GPIO port.
*/
static inline u8 gpio_port_read(u32 gpioport)
static inline uint8_t gpio_port_read(uint32_t gpioport)
{
return gpio_read(gpioport, GPIO_ALL);
}
@ -329,15 +329,15 @@ static inline u8 gpio_port_read(u32 gpioport)
* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
* 1 to GPIO1. and so on.
*/
static inline void gpio_port_write(u32 gpioport, u8 data)
static inline void gpio_port_write(uint32_t gpioport, uint8_t data)
{
gpio_write(gpioport, GPIO_ALL, data);
}
/** @} */
void gpio_configure_trigger(u32 gpioport, enum gpio_trigger trigger, u8 gpios);
void gpio_enable_interrupts(u32 gpioport, u8 gpios);
void gpio_disable_interrupts(u32 gpioport, u8 gpios);
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios);
void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios);
void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios);
/* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */
@ -348,7 +348,7 @@ void gpio_disable_interrupts(u32 gpioport, u8 gpios);
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] srcpins source pin or group of pins to check.
*/
static inline bool gpio_is_interrupt_source(u32 gpioport, u8 srcpins)
static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins)
{
return GPIO_MIS(gpioport) & srcpins;
}
@ -364,7 +364,7 @@ static inline bool gpio_is_interrupt_source(u32 gpioport, u8 srcpins)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_clear_interrupt_flag(u32 gpioport, u8 gpios)
static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios)
{
GPIO_ICR(gpioport) |= gpios;
}

8
include/libopencm3/lm4f/rcc.h
View File

@ -116,15 +116,15 @@ void rcc_pll_on(void);
void rcc_set_osc_source(osc_src_t src);
void rcc_pll_bypass_disable(void);
void rcc_pll_bypass_enable(void);
void rcc_set_pll_divisor(u8 div400);
void rcc_set_pll_divisor(uint8_t div400);
void rcc_set_pwm_divisor(pwm_clkdiv_t div);
void rcc_usb_pll_off(void);
void rcc_usb_pll_on(void);
void rcc_wait_for_pll_ready(void);
/* High-level clock API */
void rcc_change_pll_divisor(u8 plldiv400);
u32 rcc_get_system_clock_frequency(void);
void rcc_sysclk_config(osc_src_t src, xtal_t xtal, u8 pll_div400);
void rcc_change_pll_divisor(uint8_t plldiv400);
uint32_t rcc_get_system_clock_frequency(void);
void rcc_sysclk_config(osc_src_t src, xtal_t xtal, uint8_t pll_div400);
END_DECLS

96
include/libopencm3/lm4f/systemcontrol.h
View File

@ -490,17 +490,17 @@ typedef enum {
/*
* Run clock control
*/
RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
RCC_WD1,
RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
RCC_TIMER1,
RCC_TIMER2,
RCC_TIMER3,
RCC_TIMER4,
RCC_TIMER5,
RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_GPIOB,
RCC_GPIOC,
RCC_GPIOD,
@ -516,11 +516,11 @@ typedef enum {
RCC_GPIOP,
RCC_GPIOQ,
RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
RCC_UART1,
RCC_UART2,
RCC_UART3,
@ -529,37 +529,37 @@ typedef enum {
RCC_UART6,
RCC_UART7,
RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
RCC_SSI1,
RCC_SSI2,
RCC_SSI3,
RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
RCC_I2C1,
RCC_I2C2,
RCC_I2C3,
RCC_I2C4,
RCC_I2C5,
RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
RCC_CAN1,
RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
RCC_ADC1,
RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
RCC_PWM1,
RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
RCC_QEI1,
RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
RCC_WTIMER1,
RCC_WTIMER2,
RCC_WTIMER3,
@ -570,17 +570,17 @@ typedef enum {
/*
* Sleep clock control
*/
SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
SCC_WD1,
SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
SCC_TIMER1,
SCC_TIMER2,
SCC_TIMER3,
SCC_TIMER4,
SCC_TIMER5,
SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_GPIOB,
SCC_GPIOC,
SCC_GPIOD,
@ -596,11 +596,11 @@ typedef enum {
SCC_GPIOP,
SCC_GPIOQ,
SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
SCC_UART1,
SCC_UART2,
SCC_UART3,
@ -609,37 +609,37 @@ typedef enum {
SCC_UART6,
SCC_UART7,
SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
SCC_SSI1,
SCC_SSI2,
SCC_SSI3,
SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
SCC_I2C1,
SCC_I2C2,
SCC_I2C3,
SCC_I2C4,
SCC_I2C5,
SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
SCC_CAN1,
SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
SCC_ADC1,
SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
SCC_PWM1,
SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
SCC_QEI1,
SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
SCC_WTIMER1,
SCC_WTIMER2,
SCC_WTIMER3,
@ -649,17 +649,17 @@ typedef enum {
/*
* Deep-sleep clock control
*/
DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
DCC_WD1,
DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
DCC_TIMER1,
DCC_TIMER2,
DCC_TIMER3,
DCC_TIMER4,
DCC_TIMER5,
DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_GPIOB,
DCC_GPIOC,
DCC_GPIOD,
@ -675,11 +675,11 @@ typedef enum {
DCC_GPIOP,
DCC_GPIOQ,
DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
DCC_UART1,
DCC_UART2,
DCC_UART3,
@ -688,37 +688,37 @@ typedef enum {
DCC_UART6,
DCC_UART7,
DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
DCC_SSI1,
DCC_SSI2,
DCC_SSI3,
DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
DCC_I2C1,
DCC_I2C2,
DCC_I2C3,
DCC_I2C4,
DCC_I2C5,
DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
DCC_CAN1,
DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
DCC_ADC1,
DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
DCC_PWM1,
DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
DCC_QEI1,
DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
DCC_WTIMER1,
DCC_WTIMER2,
DCC_WTIMER3,

70
include/libopencm3/lm4f/uart.h
View File

@ -442,32 +442,32 @@ enum uart_fifo_tx_trigger_level {
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
void uart_set_baudrate(u32 uart, u32 baud);
void uart_set_databits(u32 uart, u8 databits);
void uart_set_stopbits(u32 uart, u8 stopbits);
void uart_set_parity(u32 uart, enum uart_parity parity);
void uart_set_mode(u32 uart, u32 mode);
void uart_set_flow_control(u32 uart, enum uart_flowctl flow);
void uart_enable(u32 uart);
void uart_disable(u32 uart);
void uart_clock_from_piosc(u32 uart);
void uart_clock_from_sysclk(u32 uart);
void uart_set_baudrate(uint32_t uart, uint32_t baud);
void uart_set_databits(uint32_t uart, uint8_t databits);
void uart_set_stopbits(uint32_t uart, uint8_t stopbits);
void uart_set_parity(uint32_t uart, enum uart_parity parity);
void uart_set_mode(uint32_t uart, uint32_t mode);
void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow);
void uart_enable(uint32_t uart);
void uart_disable(uint32_t uart);
void uart_clock_from_piosc(uint32_t uart);
void uart_clock_from_sysclk(uint32_t uart);
void uart_send(u32 uart, u16 data);
u16 uart_recv(u32 uart);
void uart_wait_send_ready(u32 uart);
void uart_wait_recv_ready(u32 uart);
void uart_send_blocking(u32 uart, u16 data);
u16 uart_recv_blocking(u32 uart);
void uart_send(uint32_t uart, uint16_t data);
uint16_t uart_recv(uint32_t uart);
void uart_wait_send_ready(uint32_t uart);
void uart_wait_recv_ready(uint32_t uart);
void uart_send_blocking(uint32_t uart, uint16_t data);
uint16_t uart_recv_blocking(uint32_t uart);
void uart_enable_rx_dma(u32 uart);
void uart_disable_rx_dma(u32 uart);
void uart_enable_tx_dma(u32 uart);
void uart_disable_tx_dma(u32 uart);
void uart_enable_rx_dma(uint32_t uart);
void uart_disable_rx_dma(uint32_t uart);
void uart_enable_tx_dma(uint32_t uart);
void uart_disable_tx_dma(uint32_t uart);
void uart_enable_fifo(u32 uart);
void uart_disable_fifo(u32 uart);
void uart_set_fifo_trigger_levels(u32 uart,
void uart_enable_fifo(uint32_t uart);
void uart_disable_fifo(uint32_t uart);
void uart_set_fifo_trigger_levels(uint32_t uart,
enum uart_fifo_rx_trigger_level rx_level,
enum uart_fifo_tx_trigger_level tx_level);
@ -480,7 +480,7 @@ void uart_set_fifo_trigger_levels(u32 uart,
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_full(u32 uart)
bool uart_is_tx_fifo_full(uint32_t uart)
{
return UART_FR(uart) & UART_FR_TXFF;
}
@ -492,7 +492,7 @@ bool uart_is_tx_fifo_full(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_empty(u32 uart)
bool uart_is_tx_fifo_empty(uint32_t uart)
{
return UART_FR(uart) & UART_FR_TXFE;
}
@ -503,7 +503,7 @@ bool uart_is_tx_fifo_empty(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_full(u32 uart)
bool uart_is_rx_fifo_full(uint32_t uart)
{
return UART_FR(uart) & UART_FR_RXFF;
}
@ -514,19 +514,19 @@ bool uart_is_rx_fifo_full(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_empty(u32 uart)
bool uart_is_rx_fifo_empty(uint32_t uart)
{
return UART_FR(uart) & UART_FR_RXFE;
}
/**@}*/
void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints);
void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints);
void uart_enable_rx_interrupt(u32 uart);
void uart_disable_rx_interrupt(u32 uart);
void uart_enable_tx_interrupt(u32 uart);
void uart_disable_tx_interrupt(u32 uart);
void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints);
void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
void uart_enable_rx_interrupt(uint32_t uart);
void uart_disable_rx_interrupt(uint32_t uart);
void uart_enable_tx_interrupt(uint32_t uart);
void uart_disable_tx_interrupt(uint32_t uart);
void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints);
/* Let's keep this one inlined. It's designed to be used in ISRs */
/** @ingroup uart_irq
@ -537,7 +537,7 @@ void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints);
* @param[in] source source to check.
*/
static inline
bool uart_is_interrupt_source(u32 uart, enum uart_interrupt_flag source)
bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source)
{
return UART_MIS(uart) & source;
}

2
include/libopencm3/lpc13xx/gpio.h
View File

@ -115,7 +115,7 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void gpio_set(u32 gpioport, u16 gpios);
void gpio_set(uint32_t gpioport, uint16_t gpios);
END_DECLS

4
include/libopencm3/lpc17xx/gpio.h
View File

@ -150,8 +150,8 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void gpio_set(u32 gpioport, u32 gpios);
void gpio_clear(u32 gpioport, u32 gpios);
void gpio_set(uint32_t gpioport, uint32_t gpios);
void gpio_clear(uint32_t gpioport, uint32_t gpios);
END_DECLS

6
include/libopencm3/lpc43xx/gpio.h
View File

@ -171,9 +171,9 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void gpio_set(u32 gpioport, u32 gpios);
void gpio_clear(u32 gpioport, u32 gpios);
void gpio_toggle(u32 gpioport, u32 gpios);
void gpio_set(uint32_t gpioport, uint32_t gpios);
void gpio_clear(uint32_t gpioport, uint32_t gpios);
void gpio_toggle(uint32_t gpioport, uint32_t gpios);
END_DECLS

4
include/libopencm3/lpc43xx/i2c.h
View File

@ -153,8 +153,8 @@ BEGIN_DECLS
void i2c0_init(void);
void i2c0_tx_start(void);
void i2c0_tx_byte(u8 byte);
u8 i2c0_rx_byte(void);
void i2c0_tx_byte(uint8_t byte);
uint8_t i2c0_rx_byte(void);
void i2c0_stop(void);
END_DECLS

2
include/libopencm3/lpc43xx/scu.h
View File

@ -771,7 +771,7 @@ typedef enum {
BEGIN_DECLS
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf);
void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf);
END_DECLS

8
include/libopencm3/lpc43xx/ssp.h
View File

@ -188,15 +188,15 @@ void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
u8 clk_prescale,
uint8_t serial_clock_rate,
uint8_t clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option);
u16 ssp_read(ssp_num_t ssp_num);
uint16_t ssp_read(ssp_num_t ssp_num);
void ssp_write(ssp_num_t ssp_num, u16 data);
void ssp_write(ssp_num_t ssp_num, uint16_t data);
END_DECLS

2
include/libopencm3/sam/eefc.h
View File

@ -69,7 +69,7 @@
#define EEFC_FSR_FCMDE (0x01 << 1)
#define EEFC_FSR_FRDY (0x01 << 0)
static inline void eefc_set_latency(u8 wait)
static inline void eefc_set_latency(uint8_t wait)
{
#if defined(SAM3X)
EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);

8
include/libopencm3/sam/gpio.h
View File

@ -33,19 +33,19 @@ enum gpio_flags {
GPIO_FLAG_PULL_UP = 8,
};
void gpio_init(u32 gpioport, u32 pins, enum gpio_flags flags);
void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags);
static inline void gpio_set(u32 gpioport, u32 gpios)
static inline void gpio_set(uint32_t gpioport, uint32_t gpios)
{
PIO_SODR(gpioport) = gpios;
}
static inline void gpio_clear(u32 gpioport, u32 gpios)
static inline void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
PIO_CODR(gpioport) = gpios;
}
void gpio_toggle(u32 gpioport, u32 gpios);
void gpio_toggle(uint32_t gpioport, uint32_t gpios);
#endif

10
include/libopencm3/sam/pmc.h
View File

@ -125,7 +125,7 @@
#define PMC_SR_LOCKA (0x01 << 1)
#define PMC_SR_MOSCXTS (0x01 << 0)
extern u32 pmc_mck_frequency;
extern uint32_t pmc_mck_frequency;
enum mck_src {
MCK_SRC_SLOW = 0,
@ -135,10 +135,10 @@ enum mck_src {
};
void pmc_mck_set_source(enum mck_src src);
void pmc_xtal_enable(bool en, u8 startup_time);
void pmc_plla_config(u8 mul, u8 div);
void pmc_peripheral_clock_enable(u8 pid);
void pmc_peripheral_clock_disable(u8 pid);
void pmc_xtal_enable(bool en, uint8_t startup_time);
void pmc_plla_config(uint8_t mul, uint8_t div);
void pmc_peripheral_clock_enable(uint8_t pid);
void pmc_peripheral_clock_disable(uint8_t pid);
void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
void pmc_clock_setup_in_rc_4mhz_out_84mhz(void);

4
include/libopencm3/sam/pwm.h
View File

@ -86,12 +86,12 @@
# error "Processor family not defined."
#endif
static inline void pwm_set_period(int ch, u32 period)
static inline void pwm_set_period(int ch, uint32_t period)
{
PWM_CPRD(ch) = period;
}
static inline void pwm_set_duty(int ch, u32 duty)
static inline void pwm_set_duty(int ch, uint32_t duty)
{
PWM_CDTY(ch) = duty;
}

32
include/libopencm3/sam/usart.h
View File

@ -196,22 +196,22 @@ enum usart_flowcontrol {
USART_FLOWCONTROL_RTS_CTS,
};
void usart_set_baudrate(u32 usart, u32 baud);
void usart_set_databits(u32 usart, int bits);
void usart_set_stopbits(u32 usart, enum usart_stopbits);
void usart_set_parity(u32 usart, enum usart_parity);
void usart_set_mode(u32 usart, enum usart_mode);
void usart_set_flow_control(u32 usart, enum usart_flowcontrol);
void usart_enable(u32 usart);
void usart_disable(u32 usart);
void usart_send(u32 usart, u16 data);
u16 usart_recv(u32 usart);
void usart_wait_send_ready(u32 usart);
void usart_wait_recv_ready(u32 usart);
void usart_send_blocking(u32 usart, u16 data);
u16 usart_recv_blocking(u32 usart);
void usart_enable_rx_interrupt(u32 usart);
void usart_disable_rx_interrupt(u32 usart);
void usart_set_baudrate(uint32_t usart, uint32_t baud);
void usart_set_databits(uint32_t usart, int bits);
void usart_set_stopbits(uint32_t usart, enum usart_stopbits);
void usart_set_parity(uint32_t usart, enum usart_parity);
void usart_set_mode(uint32_t usart, enum usart_mode);
void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol);
void usart_enable(uint32_t usart);
void usart_disable(uint32_t usart);
void usart_send(uint32_t usart, uint16_t data);
uint16_t usart_recv(uint32_t usart);
void usart_wait_send_ready(uint32_t usart);
void usart_wait_recv_ready(uint32_t usart);
void usart_send_blocking(uint32_t usart, uint16_t data);
uint16_t usart_recv_blocking(uint32_t usart);
void usart_enable_rx_interrupt(uint32_t usart);
void usart_disable_rx_interrupt(uint32_t usart);
#endif

40
include/libopencm3/stm32/can.h
View File

@ -644,31 +644,31 @@ LGPL License Terms @ref lgpl_license
BEGIN_DECLS
void can_reset(u32 canport);
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
void can_reset(uint32_t canport);
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
bool loopback, bool silent);
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
u32 fr1, u32 fr2, u32 fifo, bool enable);
void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
u16 id2, u16 mask2, u32 fifo, bool enable);
void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
u32 fifo, bool enable);
void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
u16 id3, u16 id4, u32 fifo, bool enable);
void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
u32 fifo, bool enable);
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable);
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable);
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
uint32_t fifo, bool enable);
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4, uint32_t fifo, bool enable);
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
uint32_t fifo, bool enable);
void can_enable_irq(u32 canport, u32 irq);
void can_disable_irq(u32 canport, u32 irq);
void can_enable_irq(uint32_t canport, uint32_t irq);
void can_disable_irq(uint32_t canport, uint32_t irq);
int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data);
void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
bool *rtr, u32 *fmi, u8 *length, u8 *data);
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data);
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data);
void can_fifo_release(u32 canport, u8 fifo);
bool can_available_mailbox(u32 canport);
void can_fifo_release(uint32_t canport, uint8_t fifo);
bool can_available_mailbox(uint32_t canport);
END_DECLS
#endif

4
include/libopencm3/stm32/common/crc_common_all.h
View File

@ -81,7 +81,7 @@ void crc_reset(void);
* @param data new word to add to the crc calculator
* @return final crc calculator value
*/
u32 crc_calculate(u32 data);
uint32_t crc_calculate(uint32_t data);
/**
* Add a block of data to the CRC calculator and return the final result
@ -89,7 +89,7 @@ u32 crc_calculate(u32 data);
* @param size length of data, in 32bit increments
* @return final CRC calculator value
*/
u32 crc_calculate_block(u32 *datap, int size);
uint32_t crc_calculate_block(uint32_t *datap, int size);
END_DECLS

10
include/libopencm3/stm32/common/dac_common_all.h
View File

@ -400,12 +400,12 @@ void dac_dma_enable(data_channel dac_channel);
void dac_dma_disable(data_channel dac_channel);
void dac_trigger_enable(data_channel dac_channel);
void dac_trigger_disable(data_channel dac_channel);
void dac_set_trigger_source(u32 dac_trig_src);
void dac_set_waveform_generation(u32 dac_wave_ens);
void dac_set_trigger_source(uint32_t dac_trig_src);
void dac_set_waveform_generation(uint32_t dac_wave_ens);
void dac_disable_waveform_generation(data_channel dac_channel);
void dac_set_waveform_characteristics(u32 dac_mamp);
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel);
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format);
void dac_set_waveform_characteristics(uint32_t dac_mamp);
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, data_channel dac_channel);
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, data_align dac_data_format);
void dac_software_trigger(data_channel dac_channel);
END_DECLS

50
include/libopencm3/stm32/common/dma_common_f13.h
View File

@ -385,31 +385,31 @@ group.
BEGIN_DECLS
void dma_channel_reset(u32 dma, u8 channel);
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts);
bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts);
void dma_enable_mem2mem_mode(u32 dma, u8 channel);
void dma_set_priority(u32 dma, u8 channel, u32 prio);
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
void dma_enable_memory_increment_mode(u32 dma, u8 channel);
void dma_disable_memory_increment_mode(u32 dma, u8 channel);
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
void dma_enable_circular_mode(u32 dma, u8 channel);
void dma_set_read_from_peripheral(u32 dma, u8 channel);
void dma_set_read_from_memory(u32 dma, u8 channel);
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel);
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel);
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel);
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel);
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel);
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel);
void dma_enable_channel(u32 dma, u8 channel);
void dma_disable_channel(u32 dma, u8 channel);
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
void dma_channel_reset(uint32_t dma, uint8_t channel);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts);
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel);
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_circular_mode(uint32_t dma, uint8_t channel);
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel);
void dma_set_read_from_memory(uint32_t dma, uint8_t channel);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_channel(uint32_t dma, uint8_t channel);
void dma_disable_channel(uint32_t dma, uint8_t channel);
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number);
END_DECLS

84
include/libopencm3/stm32/common/dma_common_f24.h
View File

@ -572,48 +572,48 @@ BEGIN_DECLS
* different configuration options.
*/
void dma_stream_reset(u32 dma, u8 stream);
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts);
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt);
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction);
void dma_set_priority(u32 dma, u8 stream, u32 prio);
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size);
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size);
void dma_enable_memory_increment_mode(u32 dma, u8 stream);
void dma_disable_memory_increment_mode(u32 dma, u8 channel);
void dma_enable_peripheral_increment_mode(u32 dma, u8 stream);
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream);
void dma_enable_circular_mode(u32 dma, u8 stream);
void dma_channel_select(u32 dma, u8 stream, u32 channel);
void dma_set_memory_burst(u32 dma, u8 stream, u32 burst);
void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst);
void dma_set_initial_target(u32 dma, u8 stream, u8 memory);
u8 dma_get_target(u32 dma, u8 stream);
void dma_enable_double_buffer_mode(u32 dma, u8 stream);
void dma_disable_double_buffer_mode(u32 dma, u8 stream);
void dma_set_peripheral_flow_control(u32 dma, u8 stream);
void dma_set_dma_flow_control(u32 dma, u8 stream);
void dma_enable_transfer_error_interrupt(u32 dma, u8 stream);
void dma_disable_transfer_error_interrupt(u32 dma, u8 stream);
void dma_enable_half_transfer_interrupt(u32 dma, u8 stream);
void dma_disable_half_transfer_interrupt(u32 dma, u8 stream);
void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream);
void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream);
u32 dma_fifo_status(u32 dma, u8 stream);
void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream);
void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream);
void dma_enable_fifo_error_interrupt(u32 dma, u8 stream);
void dma_disable_fifo_error_interrupt(u32 dma, u8 stream);
void dma_enable_direct_mode(u32 dma, u8 stream);
void dma_enable_fifo_mode(u32 dma, u8 stream);
void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold);
void dma_enable_stream(u32 dma, u8 stream);
void dma_disable_stream(u32 dma, u8 stream);
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address);
void dma_set_memory_address(u32 dma, u8 stream, u32 address);
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address);
void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
void dma_stream_reset(uint32_t dma, uint8_t stream);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt);
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction);
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_enable_circular_mode(uint32_t dma, uint8_t stream);
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel);
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory);
uint8_t dma_get_target(uint32_t dma, uint8_t stream);
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream);
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode(uint32_t dma, uint8_t stream);
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream);
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold);
void dma_enable_stream(uint32_t dma, uint8_t stream);
void dma_disable_stream(uint32_t dma, uint8_t stream);
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number);
END_DECLS
/**@}*/

26
include/libopencm3/stm32/common/flash_common_f24.h
View File

@ -110,10 +110,10 @@
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)
#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
@ -127,7 +127,7 @@ void flash_prefetch_enable(void);
void flash_prefetch_disable(void);
void flash_dcache_reset(void);
void flash_icache_reset(void);
void flash_set_ws(u32 ws);
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgserr_flag(void);
@ -139,15 +139,15 @@ void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
void flash_unlock_option_bytes(void);
void flash_lock_option_bytes(void);
void flash_erase_all_sectors(u32 program_size);
void flash_erase_sector(u8 sector, u32 program_size);
void flash_program_double_word(u32 address, u64 data);
void flash_program_word(u32 address, u32 data);
void flash_program_half_word(u32 address, u16 data);
void flash_program_byte(u32 address, u8 data);
void flash_program(u32 address, u8 *data, u32 len);
void flash_erase_all_sectors(uint32_t program_size);
void flash_erase_sector(uint8_t sector, uint32_t program_size);
void flash_program_double_word(uint32_t address, uint64_t data);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_program_byte(uint32_t address, uint8_t data);
void flash_program(uint32_t address, uint8_t *data, uint32_t len);
void flash_wait_for_last_operation(void);
void flash_program_option_bytes(u32 data);
void flash_program_option_bytes(uint32_t data);
END_DECLS

14
include/libopencm3/stm32/common/gpio_common_all.h
View File

@ -74,13 +74,13 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void gpio_set(u32 gpioport, u16 gpios);
void gpio_clear(u32 gpioport, u16 gpios);
u16 gpio_get(u32 gpioport, u16 gpios);
void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
void gpio_set(uint32_t gpioport, uint16_t gpios);
void gpio_clear(uint32_t gpioport, uint16_t gpios);
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios);
void gpio_toggle(uint32_t gpioport, uint16_t gpios);
uint16_t gpio_port_read(uint32_t gpioport);
void gpio_port_write(uint32_t gpioport, uint16_t data);
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios);
END_DECLS

6
include/libopencm3/stm32/common/gpio_common_f24.h
View File

@ -287,9 +287,9 @@ BEGIN_DECLS
* sounding functions that have very different functionality.
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
END_DECLS
/**@}*/

14
include/libopencm3/stm32/common/hash_common_f24.h
View File

@ -161,15 +161,15 @@ Mikhail Avkhimenia <mikhail@avkhimenia.net>
BEGIN_DECLS
void hash_set_mode(u8 mode);
void hash_set_algorithm(u8 algorithm);
void hash_set_data_type(u8 datatype);
void hash_set_key_length(u8 keylength);
void hash_set_last_word_valid_bits(u8 validbits);
void hash_set_mode(uint8_t mode);
void hash_set_algorithm(uint8_t algorithm);
void hash_set_data_type(uint8_t datatype);
void hash_set_key_length(uint8_t keylength);
void hash_set_last_word_valid_bits(uint8_t validbits);
void hash_init(void);
void hash_add_data(u32 data);
void hash_add_data(uint32_t data);
void hash_digest(void);
void hash_get_result(u32 *data);
void hash_get_result(uint32_t *data);
END_DECLS
/**@}*/

54
include/libopencm3/stm32/common/i2c_common_all.h
View File

@ -357,33 +357,33 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void i2c_reset(u32 i2c);
void i2c_peripheral_enable(u32 i2c);
void i2c_peripheral_disable(u32 i2c);
void i2c_send_start(u32 i2c);
void i2c_send_stop(u32 i2c);
void i2c_clear_stop(u32 i2c);
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
void i2c_set_fast_mode(u32 i2c);
void i2c_set_standard_mode(u32 i2c);
void i2c_set_clock_frequency(u32 i2c, u8 freq);
void i2c_set_ccr(u32 i2c, u16 freq);
void i2c_set_trise(u32 i2c, u16 trise);
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
void i2c_send_data(u32 i2c, u8 data);
uint8_t i2c_get_data(u32 i2c);
void i2c_enable_interrupt(u32 i2c, u32 interrupt);
void i2c_disable_interrupt(u32 i2c, u32 interrupt);
void i2c_enable_ack(u32 i2c);
void i2c_disable_ack(u32 i2c);
void i2c_nack_next(u32 i2c);
void i2c_nack_current(u32 i2c);
void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
void i2c_enable_dma(u32 i2c);
void i2c_disable_dma(u32 i2c);
void i2c_set_dma_last_transfer(u32 i2c);
void i2c_clear_dma_last_transfer(u32 i2c);
void i2c_reset(uint32_t i2c);
void i2c_peripheral_enable(uint32_t i2c);
void i2c_peripheral_disable(uint32_t i2c);
void i2c_send_start(uint32_t i2c);
void i2c_send_stop(uint32_t i2c);
void i2c_clear_stop(uint32_t i2c);
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
void i2c_set_fast_mode(uint32_t i2c);
void i2c_set_standard_mode(uint32_t i2c);
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
void i2c_set_ccr(uint32_t i2c, uint16_t freq);
void i2c_set_trise(uint32_t i2c, uint16_t trise);
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite);
void i2c_send_data(uint32_t i2c, uint8_t data);
uint8_t i2c_get_data(uint32_t i2c);
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
void i2c_enable_ack(uint32_t i2c);
void i2c_disable_ack(uint32_t i2c);
void i2c_nack_next(uint32_t i2c);
void i2c_nack_current(uint32_t i2c);
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle);
void i2c_enable_dma(uint32_t i2c);
void i2c_disable_dma(uint32_t i2c);
void i2c_set_dma_last_transfer(uint32_t i2c);
void i2c_clear_dma_last_transfer(uint32_t i2c);
END_DECLS

2
include/libopencm3/stm32/common/iwdg_common_all.h
View File

@ -106,7 +106,7 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void iwdg_start(void);
void iwdg_set_period_ms(u32 period);
void iwdg_set_period_ms(uint32_t period);
bool iwdg_reload_busy(void);
bool iwdg_prescaler_busy(void);
void iwdg_reset(void);

2
include/libopencm3/stm32/common/pwr_common_all.h
View File

@ -108,7 +108,7 @@ BEGIN_DECLS
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(u32 pvd_level);
void pwr_enable_power_voltage_detect(uint32_t pvd_level);
void pwr_disable_power_voltage_detect(void);
void pwr_clear_standby_flag(void);
void pwr_clear_wakeup_flag(void);

4
include/libopencm3/stm32/common/rtc_common_bcd.h
View File

@ -330,11 +330,11 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void rtc_set_prescaler(u32 sync, u32 async);
void rtc_set_prescaler(uint32_t sync, uint32_t async);
void rtc_wait_for_synchro(void);
void rtc_lock(void);
void rtc_unlock(void);
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel);
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel);
void rtc_clear_wakeup_flag(void);
END_DECLS

92
include/libopencm3/stm32/common/spi_common_all.h
View File

@ -355,52 +355,52 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void spi_reset(u32 spi_peripheral);
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
void spi_enable(u32 spi);
void spi_disable(u32 spi);
u16 spi_clean_disable(u32 spi);
void spi_write(u32 spi, u16 data);
void spi_send(u32 spi, u16 data);
u16 spi_read(u32 spi);
u16 spi_xfer(u32 spi, u16 data);
void spi_set_bidirectional_mode(u32 spi);
void spi_set_unidirectional_mode(u32 spi);
void spi_set_bidirectional_receive_only_mode(u32 spi);
void spi_set_bidirectional_transmit_only_mode(u32 spi);
void spi_enable_crc(u32 spi);
void spi_disable_crc(u32 spi);
void spi_set_next_tx_from_buffer(u32 spi);
void spi_set_next_tx_from_crc(u32 spi);
void spi_set_dff_8bit(u32 spi);
void spi_set_dff_16bit(u32 spi);
void spi_set_full_duplex_mode(u32 spi);
void spi_set_receive_only_mode(u32 spi);
void spi_disable_software_slave_management(u32 spi);
void spi_enable_software_slave_management(u32 spi);
void spi_set_nss_high(u32 spi);
void spi_set_nss_low(u32 spi);
void spi_send_lsb_first(u32 spi);
void spi_send_msb_first(u32 spi);
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
void spi_set_master_mode(u32 spi);
void spi_set_slave_mode(u32 spi);
void spi_set_clock_polarity_1(u32 spi);
void spi_set_clock_polarity_0(u32 spi);
void spi_set_clock_phase_1(u32 spi);
void spi_set_clock_phase_0(u32 spi);
void spi_enable_tx_buffer_empty_interrupt(u32 spi);
void spi_disable_tx_buffer_empty_interrupt(u32 spi);
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
void spi_enable_error_interrupt(u32 spi);
void spi_disable_error_interrupt(u32 spi);
void spi_enable_ss_output(u32 spi);
void spi_disable_ss_output(u32 spi);
void spi_enable_tx_dma(u32 spi);
void spi_disable_tx_dma(u32 spi);
void spi_enable_rx_dma(u32 spi);
void spi_disable_rx_dma(u32 spi);
void spi_reset(uint32_t spi_peripheral);
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst);
void spi_enable(uint32_t spi);
void spi_disable(uint32_t spi);
uint16_t spi_clean_disable(uint32_t spi);
void spi_write(uint32_t spi, uint16_t data);
void spi_send(uint32_t spi, uint16_t data);
uint16_t spi_read(uint32_t spi);
uint16_t spi_xfer(uint32_t spi, uint16_t data);
void spi_set_bidirectional_mode(uint32_t spi);
void spi_set_unidirectional_mode(uint32_t spi);
void spi_set_bidirectional_receive_only_mode(uint32_t spi);
void spi_set_bidirectional_transmit_only_mode(uint32_t spi);
void spi_enable_crc(uint32_t spi);
void spi_disable_crc(uint32_t spi);
void spi_set_next_tx_from_buffer(uint32_t spi);
void spi_set_next_tx_from_crc(uint32_t spi);
void spi_set_dff_8bit(uint32_t spi);
void spi_set_dff_16bit(uint32_t spi);
void spi_set_full_duplex_mode(uint32_t spi);
void spi_set_receive_only_mode(uint32_t spi);
void spi_disable_software_slave_management(uint32_t spi);
void spi_enable_software_slave_management(uint32_t spi);
void spi_set_nss_high(uint32_t spi);
void spi_set_nss_low(uint32_t spi);
void spi_send_lsb_first(uint32_t spi);
void spi_send_msb_first(uint32_t spi);
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate);
void spi_set_master_mode(uint32_t spi);
void spi_set_slave_mode(uint32_t spi);
void spi_set_clock_polarity_1(uint32_t spi);
void spi_set_clock_polarity_0(uint32_t spi);
void spi_set_clock_phase_1(uint32_t spi);
void spi_set_clock_phase_0(uint32_t spi);
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi);
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi);
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi);
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi);
void spi_enable_error_interrupt(uint32_t spi);
void spi_disable_error_interrupt(uint32_t spi);
void spi_enable_ss_output(uint32_t spi);
void spi_disable_ss_output(uint32_t spi);
void spi_enable_tx_dma(uint32_t spi);
void spi_disable_tx_dma(uint32_t spi);
void spi_enable_rx_dma(uint32_t spi);
void spi_disable_rx_dma(uint32_t spi);
END_DECLS

154
include/libopencm3/stm32/common/timer_common_all.h
View File

@ -1029,86 +1029,86 @@ enum tim_et_pol {
BEGIN_DECLS
void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
bool timer_interrupt_source(u32 timer_peripheral, u32 flag);
bool timer_get_flag(u32 timer_peripheral, u32 flag);
void timer_clear_flag(u32 timer_peripheral, u32 flag);
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction);
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
void timer_enable_preload(u32 timer_peripheral);
void timer_disable_preload(u32 timer_peripheral);
void timer_set_alignment(u32 timer_peripheral, u32 alignment);
void timer_direction_up(u32 timer_peripheral);
void timer_direction_down(u32 timer_peripheral);
void timer_one_shot_mode(u32 timer_peripheral);
void timer_continuous_mode(u32 timer_peripheral);
void timer_update_on_any(u32 timer_peripheral);
void timer_update_on_overflow(u32 timer_peripheral);
void timer_enable_update_event(u32 timer_peripheral);
void timer_disable_update_event(u32 timer_peripheral);
void timer_enable_counter(u32 timer_peripheral);
void timer_disable_counter(u32 timer_peripheral);
void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs);
void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs);
void timer_set_ti1_ch123_xor(u32 timer_peripheral);
void timer_set_ti1_ch1(u32 timer_peripheral);
void timer_set_master_mode(u32 timer_peripheral, u32 mode);
void timer_set_dma_on_compare_event(u32 timer_peripheral);
void timer_set_dma_on_update_event(u32 timer_peripheral);
void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral);
void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral);
void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral);
void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral);
void timer_set_prescaler(u32 timer_peripheral, u32 value);
void timer_set_repetition_counter(u32 timer_peripheral, u32 value);
void timer_set_period(u32 timer_peripheral, u32 period);
void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
void timer_reset(uint32_t timer_peripheral);
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq);
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq);
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag);
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag);
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag);
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
uint32_t alignment, uint32_t direction);
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div);
void timer_enable_preload(uint32_t timer_peripheral);
void timer_disable_preload(uint32_t timer_peripheral);
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment);
void timer_direction_up(uint32_t timer_peripheral);
void timer_direction_down(uint32_t timer_peripheral);
void timer_one_shot_mode(uint32_t timer_peripheral);
void timer_continuous_mode(uint32_t timer_peripheral);
void timer_update_on_any(uint32_t timer_peripheral);
void timer_update_on_overflow(uint32_t timer_peripheral);
void timer_enable_update_event(uint32_t timer_peripheral);
void timer_disable_update_event(uint32_t timer_peripheral);
void timer_enable_counter(uint32_t timer_peripheral);
void timer_disable_counter(uint32_t timer_peripheral);
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral);
void timer_set_ti1_ch1(uint32_t timer_peripheral);
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode);
void timer_set_dma_on_compare_event(uint32_t timer_peripheral);
void timer_set_dma_on_update_event(uint32_t timer_peripheral);
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral);
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral);
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral);
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral);
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value);
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value);
void timer_set_period(uint32_t timer_peripheral, uint32_t period);
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode);
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value);
void timer_enable_break_main_output(u32 timer_peripheral);
void timer_disable_break_main_output(u32 timer_peripheral);
void timer_enable_break_automatic_output(u32 timer_peripheral);
void timer_disable_break_automatic_output(u32 timer_peripheral);
void timer_set_break_polarity_high(u32 timer_peripheral);
void timer_set_break_polarity_low(u32 timer_peripheral);
void timer_enable_break(u32 timer_peripheral);
void timer_disable_break(u32 timer_peripheral);
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral);
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral);
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral);
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral);
void timer_set_break_lock(u32 timer_peripheral, u32 lock);
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
void timer_generate_event(u32 timer_peripheral, u32 event);
u32 timer_get_counter(u32 timer_peripheral);
void timer_set_counter(u32 timer_peripheral, u32 count);
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value);
void timer_enable_break_main_output(uint32_t timer_peripheral);
void timer_disable_break_main_output(uint32_t timer_peripheral);
void timer_enable_break_automatic_output(uint32_t timer_peripheral);
void timer_disable_break_automatic_output(uint32_t timer_peripheral);
void timer_set_break_polarity_high(uint32_t timer_peripheral);
void timer_set_break_polarity_low(uint32_t timer_peripheral);
void timer_enable_break(uint32_t timer_peripheral);
void timer_disable_break(uint32_t timer_peripheral);
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral);
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral);
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral);
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral);
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock);
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime);
void timer_generate_event(uint32_t timer_peripheral, uint32_t event);
uint32_t timer_get_counter(uint32_t timer_peripheral);
void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
void timer_ic_enable(u32 timer, enum tim_ic_id ic);
void timer_ic_disable(u32 timer, enum tim_ic_id ic);
void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, enum tim_ic_psc psc);
void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, enum tim_ic_input in);
void timer_ic_enable(uint32_t timer, enum tim_ic_id ic);
void timer_ic_disable(uint32_t timer, enum tim_ic_id ic);
void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt);
void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
void timer_slave_set_polarity(u32 timer, enum tim_et_pol pol);
void timer_slave_set_mode(u32 timer, u8 mode);
void timer_slave_set_trigger(u32 timer, u8 trigger);
void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt);
void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc);
void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol);
void timer_slave_set_mode(uint32_t timer, uint8_t mode);
void timer_slave_set_trigger(uint32_t timer, uint8_t trigger);
END_DECLS

4
include/libopencm3/stm32/common/timer_common_f24.h
View File

@ -98,8 +98,8 @@ enum tim_ic_pol {
BEGIN_DECLS
void timer_set_option(u32 timer_peripheral, u32 option);
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
END_DECLS

52
include/libopencm3/stm32/common/usart_common_all.h
View File

@ -346,32 +346,32 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void usart_set_baudrate(u32 usart, u32 baud);
void usart_set_databits(u32 usart, u32 bits);
void usart_set_stopbits(u32 usart, u32 stopbits);
void usart_set_parity(u32 usart, u32 parity);
void usart_set_mode(u32 usart, u32 mode);
void usart_set_flow_control(u32 usart, u32 flowcontrol);
void usart_enable(u32 usart);
void usart_disable(u32 usart);
void usart_send(u32 usart, u16 data);
u16 usart_recv(u32 usart);
void usart_wait_send_ready(u32 usart);
void usart_wait_recv_ready(u32 usart);
void usart_send_blocking(u32 usart, u16 data);
u16 usart_recv_blocking(u32 usart);
void usart_enable_rx_dma(u32 usart);
void usart_disable_rx_dma(u32 usart);
void usart_enable_tx_dma(u32 usart);
void usart_disable_tx_dma(u32 usart);
void usart_enable_rx_interrupt(u32 usart);
void usart_disable_rx_interrupt(u32 usart);
void usart_enable_tx_interrupt(u32 usart);
void usart_disable_tx_interrupt(u32 usart);
void usart_enable_error_interrupt(u32 usart);
void usart_disable_error_interrupt(u32 usart);
bool usart_get_flag(u32 usart, u32 flag);
bool usart_get_interrupt_source(u32 usart, u32 flag);
void usart_set_baudrate(uint32_t usart, uint32_t baud);
void usart_set_databits(uint32_t usart, uint32_t bits);
void usart_set_stopbits(uint32_t usart, uint32_t stopbits);
void usart_set_parity(uint32_t usart, uint32_t parity);
void usart_set_mode(uint32_t usart, uint32_t mode);
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol);
void usart_enable(uint32_t usart);
void usart_disable(uint32_t usart);
void usart_send(uint32_t usart, uint16_t data);
uint16_t usart_recv(uint32_t usart);
void usart_wait_send_ready(uint32_t usart);
void usart_wait_recv_ready(uint32_t usart);
void usart_send_blocking(uint32_t usart, uint16_t data);
uint16_t usart_recv_blocking(uint32_t usart);
void usart_enable_rx_dma(uint32_t usart);
void usart_disable_rx_dma(uint32_t usart);
void usart_enable_tx_dma(uint32_t usart);
void usart_disable_tx_dma(uint32_t usart);
void usart_enable_rx_interrupt(uint32_t usart);
void usart_disable_rx_interrupt(uint32_t usart);
void usart_enable_tx_interrupt(uint32_t usart);
void usart_disable_tx_interrupt(uint32_t usart);
void usart_enable_error_interrupt(uint32_t usart);
void usart_disable_error_interrupt(uint32_t usart);
bool usart_get_flag(uint32_t usart, uint32_t flag);
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
END_DECLS

6
include/libopencm3/stm32/desig.h
View File

@ -42,14 +42,14 @@ BEGIN_DECLS
* Read the onboard flash size
* @return flash size in KB
*/
u16 desig_get_flash_size(void);
uint16_t desig_get_flash_size(void);
/**
* Read the full 96 bit unique identifier
* Note: ST specifies that bits 31..16 are _also_ reserved for future use
* @param result pointer to at least 3xu32s (96 bits)
* @param result pointer to at least 3xuint32_ts (96 bits)
*/
void desig_get_unique_id(u32 result[]);
void desig_get_unique_id(uint32_t result[]);
/**
* Read the full 96 bit unique identifier and return it as a

12
include/libopencm3/stm32/exti.h
View File

@ -66,12 +66,12 @@ typedef enum trigger_e {
BEGIN_DECLS
void exti_set_trigger(u32 extis, exti_trigger_type trig);
void exti_enable_request(u32 extis);
void exti_disable_request(u32 extis);
void exti_reset_request(u32 extis);
void exti_select_source(u32 exti, u32 gpioport);
u32 exti_get_flag_status(u32 exti);
void exti_set_trigger(uint32_t extis, exti_trigger_type trig);
void exti_enable_request(uint32_t extis);
void exti_disable_request(uint32_t extis);
void exti_reset_request(uint32_t extis);
void exti_select_source(uint32_t exti, uint32_t gpioport);
uint32_t exti_get_flag_status(uint32_t exti);
END_DECLS

116
include/libopencm3/stm32/f1/adc.h
View File

@ -635,70 +635,70 @@ and ADC2
BEGIN_DECLS
void adc_power_on(u32 adc);
void adc_start_conversion_direct(u32 adc);
void adc_set_single_channel(u32 adc, u8 channel);
void adc_set_dual_mode(u32 mode);
bool adc_eoc(u32 adc);
bool adc_eoc_injected(u32 adc);
u32 adc_read_regular(u32 adc);
u32 adc_read_injected(u32 adc, u8 reg);
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
void adc_disable_discontinuous_mode_regular(u32 adc);
void adc_enable_discontinuous_mode_injected(u32 adc);
void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
void adc_enable_eoc_interrupt_injected(u32 adc);
void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
void adc_disable_eoc_interrupt(u32 adc);
void adc_enable_temperature_sensor(u32 adc);
void adc_disable_temperature_sensor(u32 adc);
void adc_start_conversion_regular(u32 adc);
void adc_start_conversion_injected(u32 adc);
void adc_enable_external_trigger_regular(u32 adc, u32 trigger);
void adc_disable_external_trigger_regular(u32 adc);
void adc_enable_external_trigger_injected(u32 adc, u32 trigger);
void adc_disable_external_trigger_injected(u32 adc);
void adc_set_left_aligned(u32 adc);
void adc_set_right_aligned(u32 adc);
void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_reset_calibration(u32 adc);
void adc_calibration(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
void adc_on(u32 adc)
void adc_power_on(uint32_t adc);
void adc_start_conversion_direct(uint32_t adc);
void adc_set_single_channel(uint32_t adc, uint8_t channel);
void adc_set_dual_mode(uint32_t mode);
bool adc_eoc(uint32_t adc);
bool adc_eoc_injected(uint32_t adc);
uint32_t adc_read_regular(uint32_t adc);
uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
void adc_enable_analog_watchdog_regular(uint32_t adc);
void adc_disable_analog_watchdog_regular(uint32_t adc);
void adc_enable_analog_watchdog_injected(uint32_t adc);
void adc_disable_analog_watchdog_injected(uint32_t adc);
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
void adc_disable_discontinuous_mode_regular(uint32_t adc);
void adc_enable_discontinuous_mode_injected(uint32_t adc);
void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
void adc_enable_scan_mode(uint32_t adc);
void adc_disable_scan_mode(uint32_t adc);
void adc_enable_eoc_interrupt_injected(uint32_t adc);
void adc_disable_eoc_interrupt_injected(uint32_t adc);
void adc_enable_awd_interrupt(uint32_t adc);
void adc_disable_awd_interrupt(uint32_t adc);
void adc_enable_eoc_interrupt(uint32_t adc);
void adc_disable_eoc_interrupt(uint32_t adc);
void adc_enable_temperature_sensor(uint32_t adc);
void adc_disable_temperature_sensor(uint32_t adc);
void adc_start_conversion_regular(uint32_t adc);
void adc_start_conversion_injected(uint32_t adc);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
void adc_disable_external_trigger_regular(uint32_t adc);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
void adc_disable_external_trigger_injected(uint32_t adc);
void adc_set_left_aligned(uint32_t adc);
void adc_set_right_aligned(uint32_t adc);
void adc_enable_dma(uint32_t adc);
void adc_disable_dma(uint32_t adc);
void adc_reset_calibration(uint32_t adc);
void adc_calibration(uint32_t adc);
void adc_set_continuous_conversion_mode(uint32_t adc);
void adc_set_single_conversion_mode(uint32_t adc);
void adc_on(uint32_t adc)
LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_off(u32 adc);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
void adc_off(uint32_t adc);
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_continous_conversion_mode(u32 adc)
void adc_set_continous_conversion_mode(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(u32 adc)
void adc_enable_jeoc_interrupt(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(u32 adc)
void adc_disable_jeoc_interrupt(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
END_DECLS

4
include/libopencm3/stm32/f1/ethernet.h
View File

@ -202,8 +202,8 @@
BEGIN_DECLS
void eth_smi_write(u8 phy, u8 reg, u16 data);
u16 eth_smi_read(u8 phy, u8 reg);
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data);
uint16_t eth_smi_read(uint8_t phy, uint8_t reg);
END_DECLS

18
include/libopencm3/stm32/f1/flash.h
View File

@ -83,9 +83,9 @@
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_RDP_KEY ((u16)0x00a5)
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
#define FLASH_RDP_KEY ((uint16_t)0x00a5)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
@ -95,7 +95,7 @@ void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
void flash_halfcycle_disable(void);
void flash_set_ws(u32 ws);
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgerr_flag(void);
@ -103,15 +103,15 @@ void flash_clear_eop_flag(void);
void flash_clear_wrprterr_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
u32 flash_get_status_flags(void);
uint32_t flash_get_status_flags(void);
void flash_unlock_option_bytes(void);
void flash_erase_all_pages(void);
void flash_erase_page(u32 page_address);
void flash_program_word(u32 address, u32 data);
void flash_program_half_word(u32 address, u16 data);
void flash_erase_page(uint32_t page_address);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(u32 address, u16 data);
void flash_program_option_bytes(uint32_t address, uint16_t data);
END_DECLS

8
include/libopencm3/stm32/f1/gpio.h
View File

@ -948,10 +948,10 @@ Line Devices only
BEGIN_DECLS
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
void gpio_set_eventout(u8 evoutport, u8 evoutpin);
void gpio_primary_remap(u32 swjenable, u32 maps);
void gpio_secondary_remap(u32 maps);
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios);
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin);
void gpio_primary_remap(uint32_t swjenable, uint32_t maps);
void gpio_secondary_remap(uint32_t maps);
END_DECLS

6
include/libopencm3/stm32/f1/memorymap.h
View File

@ -25,9 +25,9 @@
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all busses */
#define FLASH_BASE ((u32)0x08000000)
#define PERIPH_BASE ((u32)0x40000000)
#define INFO_BASE ((u32)0x1ffff000)
#define FLASH_BASE ((uint32_t)0x08000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ffff000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)

44
include/libopencm3/stm32/f1/rcc.h
View File

@ -490,8 +490,8 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR2_PREDIV2_DIV16 0xf
/* --- Variable definitions ------------------------------------------------ */
extern u32 rcc_ppre1_frequency;
extern u32 rcc_ppre2_frequency;
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
@ -512,28 +512,28 @@ void rcc_osc_on(osc_t osc);
void rcc_osc_off(osc_t osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_set_mco(u32 mcosrc);
void rcc_set_mco(uint32_t mcosrc);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_multiplication_factor(u32 mul);
void rcc_set_pll2_multiplication_factor(u32 mul);
void rcc_set_pll3_multiplication_factor(u32 mul);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_pllxtpre(u32 pllxtpre);
void rcc_set_adcpre(u32 adcpre);
void rcc_set_ppre2(u32 ppre2);
void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_usbpre(u32 usbpre);
void rcc_set_prediv1(u32 prediv);
void rcc_set_prediv2(u32 prediv);
void rcc_set_prediv1_source(u32 rccsrc);
u32 rcc_system_clock_source(void);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_multiplication_factor(uint32_t mul);
void rcc_set_pll2_multiplication_factor(uint32_t mul);
void rcc_set_pll3_multiplication_factor(uint32_t mul);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_pllxtpre(uint32_t pllxtpre);
void rcc_set_adcpre(uint32_t adcpre);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_usbpre(uint32_t usbpre);
void rcc_set_prediv1(uint32_t prediv);
void rcc_set_prediv2(uint32_t prediv);
void rcc_set_prediv1_source(uint32_t rccsrc);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
void rcc_clock_setup_in_hsi_out_24mhz(void);

16
include/libopencm3/stm32/f1/rtc.h
View File

@ -150,20 +150,20 @@ BEGIN_DECLS
void rtc_awake_from_off(osc_t clock_source);
void rtc_enter_config_mode(void);
void rtc_exit_config_mode(void);
void rtc_set_alarm_time(u32 alarm_time);
void rtc_set_alarm_time(uint32_t alarm_time);
void rtc_enable_alarm(void);
void rtc_disable_alarm(void);
void rtc_set_prescale_val(u32 prescale_val);
u32 rtc_get_counter_val(void);
u32 rtc_get_prescale_div_val(void);
u32 rtc_get_alarm_val(void);
void rtc_set_counter_val(u32 counter_val);
void rtc_set_prescale_val(uint32_t prescale_val);
uint32_t rtc_get_counter_val(void);
uint32_t rtc_get_prescale_div_val(void);
uint32_t rtc_get_alarm_val(void);
void rtc_set_counter_val(uint32_t counter_val);
void rtc_interrupt_enable(rtcflag_t flag_val);
void rtc_interrupt_disable(rtcflag_t flag_val);
void rtc_clear_flag(rtcflag_t flag_val);
u32 rtc_check_flag(rtcflag_t flag_val);
uint32_t rtc_check_flag(rtcflag_t flag_val);
void rtc_awake_from_standby(void);
void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val);
END_DECLS

2
include/libopencm3/stm32/f1/timer.h
View File

@ -47,7 +47,7 @@ enum tim_ic_pol {
BEGIN_DECLS
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
END_DECLS

24
include/libopencm3/stm32/f1/usb.h
View File

@ -49,17 +49,17 @@ LGPL License Terms @ref lgpl_license
/* --- USB general registers ----------------------------------------------- */
/* USB Control register */
#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
#define USB_CNTR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x40))
/* USB Interrupt status register */
#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
#define USB_ISTR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x44))
/* USB Frame number register */
#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
#define USB_FNR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x48))
/* USB Device address register */
#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
#define USB_DADDR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x4C))
/* USB Buffer table address register */
#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
#define USB_BTABLE_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x50))
/* USB EP register */
#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
#define USB_EP_REG(EP) ((volatile uint32_t *)(USB_DEV_FS_BASE) + (EP))
/* --- USB control register masks / bits ----------------------------------- */
@ -245,16 +245,16 @@ LGPL License Terms @ref lgpl_license
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
#define USB_EP_TX_ADDR(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
#define USB_EP_TX_COUNT(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
#define USB_EP_RX_ADDR(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
#define USB_EP_RX_COUNT(EP) \
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
/* --- USB BTABLE manipulators --------------------------------------------- */
@ -268,10 +268,10 @@ LGPL License Terms @ref lgpl_license
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_BUFF(EP) \
(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2))
#define USB_GET_EP_RX_BUFF(EP) \
(USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2))
#endif

64
include/libopencm3/stm32/f1/usb_desc.h
View File

@ -28,61 +28,61 @@
#define USB_DT_ENDPOINT 0x05
struct usb_desc_head {
u8 length; /* Descriptor size 0x012 */
u8 type; /* Descriptor type ID */
uint8_t length; /* Descriptor size 0x012 */
uint8_t type; /* Descriptor type ID */
};
struct usb_device_desc {
struct usb_desc_head h; /* Size 0x12, ID 0x01 */
u16 bcd_usb; /* USB Version */
u8 class; /* Device class */
u8 sub_class; /* Subclass code */
u8 protocol; /* Protocol code */
u8 max_psize; /* Maximum packet size -> 64bytes */
u16 vendor; /* Vendor number */
u16 product; /* Device number */
u16 bcd_dev; /* Device version */
u8 man_desc; /* Index of manufacturer string desc */
u8 prod_desc; /* Index of product string desc */
u8 sn_desc; /* Index of serial number string desc */
u8 num_conf; /* Number of possible configurations */
uint16_t bcd_usb; /* USB Version */
uint8_t class; /* Device class */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t max_psize; /* Maximum packet size -> 64bytes */
uint16_t vendor; /* Vendor number */
uint16_t product; /* Device number */
uint16_t bcd_dev; /* Device version */
uint8_t man_desc; /* Index of manufacturer string desc */
uint8_t prod_desc; /* Index of product string desc */
uint8_t sn_desc; /* Index of serial number string desc */
uint8_t num_conf; /* Number of possible configurations */
};
struct usb_conf_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x02 */
u16 tot_leng; /* Total length of data */
u8 num_int; /* Number of interfaces */
u8 conf_val; /* Configuration selector */
u8 conf_desc; /* Index of conf string desc */
u8 attr; /* Attribute bitmap:
uint16_t tot_leng; /* Total length of data */
uint8_t num_int; /* Number of interfaces */
uint8_t conf_val; /* Configuration selector */
uint8_t conf_desc; /* Index of conf string desc */
uint8_t attr; /* Attribute bitmap:
* 7 : Bus powered
* 6 : Self powered
* 5 : Remote wakeup
* 4..0 : Reserved -> 0000
*/
u8 max_power; /* Maximum power consumption in 2mA steps */
uint8_t max_power; /* Maximum power consumption in 2mA steps */
};
struct usb_int_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x04 */
u8 iface_num; /* Interface id number */
u8 alt_setting; /* Alternative setting selector */
u8 num_endp; /* Endpoints used */
u8 class; /* Interface class */
u8 sub_class; /* Subclass code */
u8 protocol; /* Protocol code */
u8 iface_desc; /* Index of interface string desc */
uint8_t iface_num; /* Interface id number */
uint8_t alt_setting; /* Alternative setting selector */
uint8_t num_endp; /* Endpoints used */
uint8_t class; /* Interface class */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t iface_desc; /* Index of interface string desc */
};
struct usb_ep_desc {
struct usb_desc_head h; /* Size 0x07, Id 0x05 */
u8 ep_addr; /* Endpoint address:
uint8_t ep_addr; /* Endpoint address:
0..3 : Endpoint Number
4..6 : Reserved -> 0
7 : Direction 0=out 1=in */
u8 ep_attr; /* Endpoint attributes */
u16 max_psize; /* Maximum packet size -> 64bytes */
u8 interval; /* Interval for polling endpoint
uint8_t ep_attr; /* Endpoint attributes */
uint16_t max_psize; /* Maximum packet size -> 64bytes */
uint8_t interval; /* Interval for polling endpoint
data. Ignored for bulk & control
endpoints. */
};
@ -95,7 +95,7 @@ struct usb_conf_desc {
struct usb_string_desc {
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
u16 string[]; /* String UTF16 encoded */
uint16_t string[]; /* String UTF16 encoded */
};
#endif

30
include/libopencm3/stm32/f2/rcc.h
View File

@ -450,8 +450,8 @@
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
/* --- Variable definitions ------------------------------------------------ */
extern u32 rcc_ppre1_frequency;
extern u32 rcc_ppre2_frequency;
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
@ -495,19 +495,19 @@ void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_ppre2(u32 ppre2);
void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_rtcpre(u32 rtcpre);
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq);
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq);
u32 rcc_system_clock_source(void);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);

114
include/libopencm3/stm32/f4/adc.h
View File

@ -791,64 +791,64 @@ injected channels.
BEGIN_DECLS
void adc_power_on(u32 adc);
void adc_off(u32 adc);
void adc_enable_analog_watchdog_regular(u32 adc);
void adc_disable_analog_watchdog_regular(u32 adc);
void adc_enable_analog_watchdog_injected(u32 adc);
void adc_disable_analog_watchdog_injected(u32 adc);
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
void adc_disable_discontinuous_mode_regular(u32 adc);
void adc_enable_discontinuous_mode_injected(u32 adc);
void adc_disable_discontinuous_mode_injected(u32 adc);
void adc_enable_automatic_injected_group_conversion(u32 adc);
void adc_disable_automatic_injected_group_conversion(u32 adc);
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
void adc_enable_scan_mode(u32 adc);
void adc_disable_scan_mode(u32 adc);
void adc_enable_eoc_interrupt_injected(u32 adc);
void adc_disable_eoc_interrupt_injected(u32 adc);
void adc_enable_awd_interrupt(u32 adc);
void adc_disable_awd_interrupt(u32 adc);
void adc_enable_eoc_interrupt(u32 adc);
void adc_disable_eoc_interrupt(u32 adc);
void adc_start_conversion_regular(u32 adc);
void adc_start_conversion_injected(u32 adc);
void adc_disable_external_trigger_regular(u32 adc);
void adc_disable_external_trigger_injected(u32 adc);
void adc_set_left_aligned(u32 adc);
void adc_set_right_aligned(u32 adc);
void adc_enable_dma(u32 adc);
void adc_disable_dma(u32 adc);
void adc_set_continuous_conversion_mode(u32 adc);
void adc_set_single_conversion_mode(u32 adc);
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
bool adc_eoc(u32 adc);
bool adc_eoc_injected(u32 adc);
u32 adc_read_regular(u32 adc);
u32 adc_read_injected(u32 adc, u8 reg);
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
void adc_power_on(uint32_t adc);
void adc_off(uint32_t adc);
void adc_enable_analog_watchdog_regular(uint32_t adc);
void adc_disable_analog_watchdog_regular(uint32_t adc);
void adc_enable_analog_watchdog_injected(uint32_t adc);
void adc_disable_analog_watchdog_injected(uint32_t adc);
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
void adc_disable_discontinuous_mode_regular(uint32_t adc);
void adc_enable_discontinuous_mode_injected(uint32_t adc);
void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
void adc_enable_scan_mode(uint32_t adc);
void adc_disable_scan_mode(uint32_t adc);
void adc_enable_eoc_interrupt_injected(uint32_t adc);
void adc_disable_eoc_interrupt_injected(uint32_t adc);
void adc_enable_awd_interrupt(uint32_t adc);
void adc_disable_awd_interrupt(uint32_t adc);
void adc_enable_eoc_interrupt(uint32_t adc);
void adc_disable_eoc_interrupt(uint32_t adc);
void adc_start_conversion_regular(uint32_t adc);
void adc_start_conversion_injected(uint32_t adc);
void adc_disable_external_trigger_regular(uint32_t adc);
void adc_disable_external_trigger_injected(uint32_t adc);
void adc_set_left_aligned(uint32_t adc);
void adc_set_right_aligned(uint32_t adc);
void adc_enable_dma(uint32_t adc);
void adc_disable_dma(uint32_t adc);
void adc_set_continuous_conversion_mode(uint32_t adc);
void adc_set_single_conversion_mode(uint32_t adc);
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
bool adc_eoc(uint32_t adc);
bool adc_eoc_injected(uint32_t adc);
uint32_t adc_read_regular(uint32_t adc);
uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
void adc_set_clk_prescale(u32 prescaler);
void adc_set_multi_mode(u32 mode);
void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity);
void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity);
void adc_set_resolution(u32 adc, u16 resolution);
void adc_enable_overrun_interrupt(u32 adc);
void adc_disable_overrun_interrupt(u32 adc);
bool adc_get_overrun_flag(u32 adc);
void adc_clear_overrun_flag(u32 adc);
bool adc_awd(u32 adc);
void adc_eoc_after_each(u32 adc);
void adc_eoc_after_group(u32 adc);
void adc_set_dma_continue(u32 adc);
void adc_set_dma_terminate(u32 adc);
void adc_set_clk_prescale(uint32_t prescaler);
void adc_set_multi_mode(uint32_t mode);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity);
void adc_set_resolution(uint32_t adc, uint16_t resolution);
void adc_enable_overrun_interrupt(uint32_t adc);
void adc_disable_overrun_interrupt(uint32_t adc);
bool adc_get_overrun_flag(uint32_t adc);
void adc_clear_overrun_flag(uint32_t adc);
bool adc_awd(uint32_t adc);
void adc_eoc_after_each(uint32_t adc);
void adc_eoc_after_group(uint32_t adc);
void adc_set_dma_continue(uint32_t adc);
void adc_set_dma_terminate(uint32_t adc);
void adc_enable_temperature_sensor(void);
void adc_disable_temperature_sensor(void);

30
include/libopencm3/stm32/f4/rcc.h
View File

@ -451,8 +451,8 @@
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
/* --- Variable definitions ------------------------------------------------ */
extern u32 rcc_ppre1_frequency;
extern u32 rcc_ppre2_frequency;
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
@ -501,19 +501,19 @@ void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_ppre2(u32 ppre2);
void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_rtcpre(u32 rtcpre);
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq);
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq);
u32 rcc_system_clock_source(void);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);

18
include/libopencm3/stm32/l1/flash.h
View File

@ -69,20 +69,20 @@
#define FLASH_PECR_PELOCK (1 << 0)
/* Power down key register (FLASH_PDKEYR) */
#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637)
#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD)
/* Program/erase key register (FLASH_PEKEYR) */
#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF)
#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405)
/* Program memory key register (FLASH_PRGKEYR) */
#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF)
#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516)
/* Option byte key register (FLASH_OPTKEYR) */
#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8)
#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627)
/* --- FLASH_SR values ----------------------------------------------------- */
@ -119,7 +119,7 @@ void flash_64bit_enable(void);
void flash_64bit_disable(void);
void flash_prefetch_enable(void);
void flash_prefetch_disable(void);
void flash_set_ws(u32 ws);
void flash_set_ws(uint32_t ws);
END_DECLS

6
include/libopencm3/stm32/l1/gpio.h
View File

@ -251,9 +251,9 @@ BEGIN_DECLS
* TODO: this should all really be moved to a "common" gpio header
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
END_DECLS

4
include/libopencm3/stm32/l1/memorymap.h
View File

@ -26,8 +26,8 @@
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE ((u32)0x40000000)
#define INFO_BASE ((u32)0x1ff00000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ff00000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)

34
include/libopencm3/stm32/l1/rcc.h
View File

@ -412,8 +412,8 @@ extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
/* --- Variable definitions ------------------------------------------------ */
extern u32 rcc_ppre1_frequency;
extern u32 rcc_ppre2_frequency;
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
@ -437,21 +437,21 @@ void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
void rcc_set_sysclk_source(u32 clk);
void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor);
void rcc_set_pll_source(u32 pllsrc);
void rcc_set_adcpre(u32 adcpre);
void rcc_set_ppre2(u32 ppre2);
void rcc_set_ppre1(u32 ppre1);
void rcc_set_hpre(u32 hpre);
void rcc_set_usbpre(u32 usbpre);
void rcc_set_rtcpre(u32 rtcpre);
u32 rcc_system_clock_source(void);
void rcc_rtc_select_clock(u32 clock);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_adcpre(uint32_t adcpre);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_usbpre(uint32_t usbpre);
void rcc_set_rtcpre(uint32_t rtcpre);
uint32_t rcc_system_clock_source(void);
void rcc_rtc_select_clock(uint32_t clock);
void rcc_clock_setup_msi(const clock_scale_t *clock);
void rcc_clock_setup_hsi(const clock_scale_t *clock);
void rcc_clock_setup_pll(const clock_scale_t *clock);

2
include/libopencm3/stm32/l1/timer.h
View File

@ -82,7 +82,7 @@ Trigger 1 Remap
BEGIN_DECLS
void timer_set_option(u32 timer_peripheral, u32 option);
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
END_DECLS

2
include/libopencm3/stm32/otg_fs.h
View File

@ -89,7 +89,7 @@
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
/* Data FIFO */
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + \
#define OTG_FS_FIFO(x) ((volatile uint32_t*)(USB_OTG_FS_BASE + \
(((x) + 1) << 12)))
/* Global CSRs */

2
include/libopencm3/stm32/otg_hs.h
View File

@ -145,7 +145,7 @@
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
/* Data FIFO */
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \
#define OTG_HS_FIFO(x) ((volatile uint32_t*)(USB_OTG_HS_BASE + \
OTG_FIFO(x)))
/* Global CSRs */

8
include/libopencm3/stm32/tools.h
View File

@ -25,10 +25,10 @@
*/
/* Get register content. */
#define GET_REG(REG) ((u16) *REG)
#define GET_REG(REG) ((uint16_t) *REG)
/* Set register content. */
#define SET_REG(REG, VAL) (*REG = (u16)VAL)
#define SET_REG(REG, VAL) (*REG = (uint16_t)VAL)
/* Clear register bit. */
#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
@ -52,8 +52,8 @@
*/
#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
do { \
register u16 toggle_mask = GET_REG(REG) & (MSK); \
register u16 bit_selector; \
register uint16_t toggle_mask = GET_REG(REG) & (MSK); \
register uint16_t bit_selector; \
for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
if ((bit_selector & (BIT)) != 0) \
toggle_mask ^= bit_selector; \

54
include/libopencm3/usb/cdc.h
View File

@ -74,19 +74,19 @@ LGPL License Terms @ref lgpl_license
/* Table 15: Class-Specific Descriptor Header Format */
struct usb_cdc_header_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
u16 bcdCDC;
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint16_t bcdCDC;
} __attribute__((packed));
/* Table 16: Union Interface Functional Descriptor */
struct usb_cdc_union_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
u8 bControlInterface;
u8 bSubordinateInterface0;
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bControlInterface;
uint8_t bSubordinateInterface0;
/* ... */
} __packed;
@ -98,19 +98,19 @@ struct usb_cdc_union_descriptor {
/* Table 3: Call Management Functional Descriptor */
struct usb_cdc_call_management_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
u8 bmCapabilities;
u8 bDataInterface;
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
uint8_t bDataInterface;
} __packed;
/* Table 4: Abstract Control Management Functional Descriptor */
struct usb_cdc_acm_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
u8 bmCapabilities;
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
} __packed;
/* Table 13: Class-Specific Request Codes for PSTN subclasses */
@ -122,10 +122,10 @@ struct usb_cdc_acm_descriptor {
/* Table 17: Line Coding Structure */
struct usb_cdc_line_coding {
u32 dwDTERate;
u8 bCharFormat;
u8 bParityType;
u8 bDataBits;
uint32_t dwDTERate;
uint8_t bCharFormat;
uint8_t bParityType;
uint8_t bDataBits;
} __packed;
/* Table 30: Class-Specific Notification Codes for PSTN subclasses */
@ -135,11 +135,11 @@ struct usb_cdc_line_coding {
/* Notification Structure */
struct usb_cdc_notification {
u8 bmRequestType;
u8 bNotification;
u16 wValue;
u16 wIndex;
u16 wLength;
uint8_t bmRequestType;
uint8_t bNotification;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} __packed;
#endif

12
include/libopencm3/usb/dfu.h
View File

@ -83,17 +83,17 @@ enum dfu_state {
#define DFU_FUNCTIONAL 0x21
struct usb_dfu_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bmAttributes;
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bmAttributes;
#define USB_DFU_CAN_DOWNLOAD 0x01
#define USB_DFU_CAN_UPLOAD 0x02
#define USB_DFU_MANIFEST_TOLERANT 0x04
#define USB_DFU_WILL_DETACH 0x08
u16 wDetachTimeout;
u16 wTransferSize;
u16 bcdDFUVersion;
uint16_t wDetachTimeout;
uint16_t wTransferSize;
uint16_t bcdDFUVersion;
} __packed;
#endif

10
include/libopencm3/usb/hid.h
View File

@ -46,11 +46,11 @@ LGPL License Terms @ref lgpl_license
#define USB_DT_REPORT 0x22
struct usb_hid_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdHID;
u8 bCountryCode;
u8 bNumDescriptors;
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
} __packed;
#endif

30
include/libopencm3/usb/usbd.h
View File

@ -63,7 +63,7 @@ extern usbd_device * usbd_init(const usbd_driver *driver,
const struct usb_device_descriptor *dev,
const struct usb_config_descriptor *conf,
const char **strings, int num_strings,
u8 *control_buffer, u16 control_buffer_size);
uint8_t *control_buffer, uint16_t control_buffer_size);
extern void usbd_register_reset_callback(usbd_device *usbd_dev,
void (*callback)(void));
@ -75,39 +75,39 @@ extern void usbd_register_sof_callback(usbd_device *usbd_dev,
void (*callback)(void));
typedef int (*usbd_control_callback)(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf, u16 *len,
struct usb_setup_data *req, uint8_t **buf, uint16_t *len,
void (**complete)(usbd_device *usbd_dev,
struct usb_setup_data *req));
/* <usb_control.c> */
extern int usbd_register_control_callback(usbd_device *usbd_dev, u8 type,
u8 type_mask,
extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type,
uint8_t type_mask,
usbd_control_callback callback);
/* <usb_standard.c> */
extern void usbd_register_set_config_callback(usbd_device *usbd_dev,
void (*callback)(usbd_device *usbd_dev, u16 wValue));
void (*callback)(usbd_device *usbd_dev, uint16_t wValue));
/* Functions to be provided by the hardware abstraction layer */
extern void usbd_poll(usbd_device *usbd_dev);
extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected);
extern void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback)(usbd_device *usbd_dev, u8 ep));
extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep));
extern u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len);
extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
extern u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr,
void *buf, u16 len);
extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len);
extern void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall);
extern u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr);
extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
extern void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak);
extern void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
/* Optional */
extern void usbd_cable_connect(usbd_device *usbd_dev, u8 on);
extern void usbd_cable_connect(usbd_device *usbd_dev, uint8_t on);
END_DECLS

124
include/libopencm3/usb/usbstd.h
View File

@ -54,11 +54,11 @@ LGPL License Terms @ref lgpl_license
/* USB Setup Data structure - Table 9-2 */
struct usb_setup_data {
u8 bmRequestType;
u8 bRequest;
u16 wValue;
u16 wIndex;
u16 wLength;
uint8_t bmRequestType;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} __packed;
/* Class Definition */
@ -117,20 +117,20 @@ struct usb_setup_data {
/* USB Standard Device Descriptor - Table 9-8 */
struct usb_device_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdUSB;
u8 bDeviceClass;
u8 bDeviceSubClass;
u8 bDeviceProtocol;
u8 bMaxPacketSize0;
u16 idVendor;
u16 idProduct;
u16 bcdDevice;
u8 iManufacturer;
u8 iProduct;
u8 iSerialNumber;
u8 bNumConfigurations;
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} __packed;
#define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor)
@ -139,27 +139,27 @@ struct usb_device_descriptor {
* Not used in this implementation.
*/
struct usb_device_qualifier_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdUSB;
u8 bDeviceClass;
u8 bDeviceSubClass;
u8 bDeviceProtocol;
u8 bMaxPacketSize0;
u8 bNumConfigurations;
u8 bReserved;
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint8_t bNumConfigurations;
uint8_t bReserved;
} __packed;
/* USB Standard Configuration Descriptor - Table 9-10 */
struct usb_config_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wTotalLength;
u8 bNumInterfaces;
u8 bConfigurationValue;
u8 iConfiguration;
u8 bmAttributes;
u8 bMaxPower;
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
/* Descriptor ends here. The following are used internally: */
const struct usb_interface {
@ -180,15 +180,15 @@ struct usb_config_descriptor {
/* USB Standard Interface Descriptor - Table 9-12 */
struct usb_interface_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bInterfaceNumber;
u8 bAlternateSetting;
u8 bNumEndpoints;
u8 bInterfaceClass;
u8 bInterfaceSubClass;
u8 bInterfaceProtocol;
u8 iInterface;
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
/* Descriptor ends here. The following are used internally: */
const struct usb_endpoint_descriptor *endpoint;
@ -199,12 +199,12 @@ struct usb_interface_descriptor {
/* USB Standard Endpoint Descriptor - Table 9-13 */
struct usb_endpoint_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bEndpointAddress;
u8 bmAttributes;
u16 wMaxPacketSize;
u8 bInterval;
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
} __packed;
#define USB_DT_ENDPOINT_SIZE sizeof(struct usb_endpoint_descriptor)
@ -227,21 +227,21 @@ struct usb_endpoint_descriptor {
* Table 9-16 specified UNICODE String Descriptor.
*/
struct usb_string_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wData[];
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wData[];
} __packed;
/* From ECN: Interface Association Descriptors, Table 9-Z */
struct usb_iface_assoc_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bFirstInterface;
u8 bInterfaceCount;
u8 bFunctionClass;
u8 bFunctionSubClass;
u8 bFunctionProtocol;
u8 iFunction;
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bFirstInterface;
uint8_t bInterfaceCount;
uint8_t bFunctionClass;
uint8_t bFunctionSubClass;
uint8_t bFunctionProtocol;
uint8_t iFunction;
} __packed;
#define USB_DT_INTERFACE_ASSOCIATION_SIZE \
sizeof(struct usb_iface_assoc_descriptor)

18
lib/cm3/nvic.c
View File

@ -53,7 +53,7 @@ Enables a user interrupt.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_enable_irq(u8 irqn)
void nvic_enable_irq(uint8_t irqn)
{
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
@ -66,7 +66,7 @@ Disables a user interrupt.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_disable_irq(u8 irqn)
void nvic_disable_irq(uint8_t irqn)
{
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
@ -80,7 +80,7 @@ True if the interrupt has occurred and is waiting for service.
@return Boolean. Interrupt pending.
*/
u8 nvic_get_pending_irq(u8 irqn)
uint8_t nvic_get_pending_irq(uint8_t irqn)
{
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@ -94,7 +94,7 @@ is already pending.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_set_pending_irq(u8 irqn)
void nvic_set_pending_irq(uint8_t irqn)
{
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
@ -108,7 +108,7 @@ interrupt is actively being serviced.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_clear_pending_irq(u8 irqn)
void nvic_clear_pending_irq(uint8_t irqn)
{
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
@ -122,7 +122,7 @@ Interrupt has occurred and is currently being serviced.
@return Boolean. Interrupt active.
*/
u8 nvic_get_active_irq(u8 irqn)
uint8_t nvic_get_active_irq(uint8_t irqn)
{
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@ -134,7 +134,7 @@ u8 nvic_get_active_irq(u8 irqn)
@return Boolean. Interrupt enabled.
*/
u8 nvic_get_irq_enabled(u8 irqn)
uint8_t nvic_get_irq_enabled(uint8_t irqn)
{
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@ -152,7 +152,7 @@ scb_set_priority_grouping.
@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16)
*/
void nvic_set_priority(u8 irqn, u8 priority)
void nvic_set_priority(uint8_t irqn, uint8_t priority)
{
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
@ -176,7 +176,7 @@ Registers.
@param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
*/
void nvic_generate_software_interrupt(u16 irqn)
void nvic_generate_software_interrupt(uint16_t irqn)
{
if (irqn <= 239) {
NVIC_STIR |= irqn;

2
lib/cm3/scb.c
View File

@ -35,7 +35,7 @@ void scb_reset_system(void)
while (1);
}
void scb_set_priority_grouping(u32 prigroup)
void scb_set_priority_grouping(uint32_t prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
}

10
lib/cm3/sync.c
View File

@ -19,16 +19,16 @@
#include <libopencm3/cm3/sync.h>
u32 __ldrex(volatile u32 *addr)
uint32_t __ldrex(volatile uint32_t *addr)
{
u32 res;
uint32_t res;
__asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr));
return res;
}
u32 __strex(u32 val, volatile u32 *addr)
uint32_t __strex(uint32_t val, volatile uint32_t *addr)
{
u32 res;
uint32_t res;
__asm__ volatile ("strex %0, %2, [%1]"
: "=&r" (res) : "r" (addr), "r" (val));
return res;
@ -41,7 +41,7 @@ void __dmb()
void mutex_lock(mutex_t *m)
{
u32 status = 0;
uint32_t status = 0;
do {
/* Wait until the mutex is unlocked. */

20
lib/cm3/systick.c
View File

@ -46,10 +46,10 @@ LGPL License Terms @ref lgpl_license
The counter is set to the reload value when the counter starts and after it
reaches zero.
@param[in] value u32. 24 bit reload value.
@param[in] value uint32_t. 24 bit reload value.
*/
void systick_set_reload(u32 value)
void systick_set_reload(uint32_t value)
{
STK_LOAD = (value & 0x00FFFFFF);
}
@ -57,10 +57,10 @@ void systick_set_reload(u32 value)
/*---------------------------------------------------------------------------*/
/** @brief SysTick Read the Automatic Reload Value.
@returns 24 bit reload value as u32.
@returns 24 bit reload value as uint32_t.
*/
u32 systick_get_reload(void)
uint32_t systick_get_reload(void)
{
return STK_LOAD & 0x00FFFFFF;
}
@ -68,10 +68,10 @@ u32 systick_get_reload(void)
/*---------------------------------------------------------------------------*/
/** @brief Get the current SysTick counter value.
@returns 24 bit current value as u32.
@returns 24 bit current value as uint32_t.
*/
u32 systick_get_value(void)
uint32_t systick_get_value(void)
{
return STK_VAL & 0x00FFFFFF;
}
@ -81,10 +81,10 @@ u32 systick_get_value(void)
The clock source can be either the AHB clock or the same clock divided by 8.
@param[in] clocksource u8. Clock source from @ref systick_clksource.
@param[in] clocksource uint8_t. Clock source from @ref systick_clksource.
*/
void systick_set_clocksource(u8 clocksource)
void systick_set_clocksource(uint8_t clocksource)
{
if (clocksource < 2) {
STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB);
@ -140,7 +140,7 @@ the flag is read.
@returns Boolean if flag set.
*/
u8 systick_get_countflag(void)
uint8_t systick_get_countflag(void)
{
if (STK_CTRL & STK_CTRL_COUNTFLAG) {
return 1;
@ -154,7 +154,7 @@ u8 systick_get_countflag(void)
@returns Current calibration value
*/
u32 systick_get_calib(void)
uint32_t systick_get_calib(void)
{
return STK_CALIB & 0x00FFFFFF;
}

4
lib/lm3s/gpio.c
View File

@ -37,13 +37,13 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lm3s/gpio.h>
void gpio_set(u32 gpioport, u8 gpios)
void gpio_set(uint32_t gpioport, uint8_t gpios)
{
/* ipaddr[9:2] mask the bits to be set, hence the array index */
GPIO_DATA(gpioport)[gpios] = 0xff;
}
void gpio_clear(u32 gpioport, u8 gpios)
void gpio_clear(uint32_t gpioport, uint8_t gpios)
{
GPIO_DATA(gpioport)[gpios] = 0;
}

26
lib/lm4f/gpio.c
View File

@ -206,8 +206,8 @@ void gpio_enable_ahb_aperture(void)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
u8 gpios)
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
uint8_t gpios)
{
switch (mode) {
case GPIO_MODE_OUTPUT:
@ -267,8 +267,8 @@ void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, u8 gpios)
void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, uint8_t gpios)
{
if (otype == GPIO_OTYPE_OD) {
GPIO_ODR(gpioport) |= gpios;
@ -318,10 +318,10 @@ void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios)
{
u32 pctl32;
u8 pin_mask;
uint32_t pctl32;
uint8_t pin_mask;
int i;
/* Did we mean to disable the alternate function? */
@ -362,7 +362,7 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
void gpio_unlock_commit(u32 gpioport, u8 gpios)
void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios)
{
/* Unlock the GPIO_CR register */
GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE;
@ -438,7 +438,7 @@ void gpio_unlock_commit(u32 gpioport, u8 gpios)
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios Pin identifiers. @ref gpio_pin_id
*/
void gpio_toggle(u32 gpioport, u8 gpios)
void gpio_toggle(uint32_t gpioport, uint8_t gpios)
{
/* The mask makes sure we only toggle the GPIOs we want to */
GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL;
@ -490,7 +490,7 @@ void gpio_toggle(u32 gpioport, u8 gpios)
* @code{.c}
* void gpiof_isr(void)
* {
* u8 serviced_irqs = 0;
* uint8_t serviced_irqs = 0;
*
* // Process individual IRQs
* if (gpio_is_interrupt_source(GPIOF, GPIO0)) {
@ -524,7 +524,7 @@ void gpio_toggle(u32 gpioport, u8 gpios)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_configure_trigger(u32 gpioport, enum gpio_trigger trigger, u8 gpios)
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios)
{
switch (trigger) {
case GPIO_TRIG_LVL_LOW:
@ -568,7 +568,7 @@ void gpio_configure_trigger(u32 gpioport, enum gpio_trigger trigger, u8 gpios)
* combination of pins may be specified by OR'ing them
* together.
*/
void gpio_enable_interrupts(u32 gpioport, u8 gpios)
void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios)
{
GPIO_IM(gpioport) |= gpios;
}
@ -586,7 +586,7 @@ void gpio_enable_interrupts(u32 gpioport, u8 gpios)
* combination of pins may be specified by OR'ing them
* together.
*/
void gpio_disable_interrupts(u32 gpioport, u8 gpios)
void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios)
{
GPIO_IM(gpioport) |= gpios;
}

26
lib/lm4f/rcc.c
View File

@ -100,10 +100,10 @@ Alexandru Gagniuc <mr.nuke.me@gmail.com>
* If write access is desired (i.e. when changing the system clock via the
* fine-grained mechanisms), then include the following line in your code:
* @code
* extern u32 lm4f_rcc_sysclk_freq;
* extern uint32_t lm4f_rcc_sysclk_freq;
* @endcode
*/
u32 lm4f_rcc_sysclk_freq = 16000000;
uint32_t lm4f_rcc_sysclk_freq = 16000000;
/**
@ -118,7 +118,7 @@ u32 lm4f_rcc_sysclk_freq = 16000000;
*/
void rcc_configure_xtal(xtal_t xtal)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC;
reg32 &= ~SYSCTL_RCC_XTAL_MASK;
@ -215,7 +215,7 @@ void rcc_pll_on(void)
*/
void rcc_set_osc_source(osc_src_t src)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC2;
reg32 &= ~SYSCTL_RCC2_OSCSRC2_MASK;
@ -270,9 +270,9 @@ void rcc_pll_bypass_enable(void)
* caller's responsibility to ensure that the divisor will not create
* a system clock that is out of spec.
*/
void rcc_set_pll_divisor(u8 div400)
void rcc_set_pll_divisor(uint8_t div400)
{
u32 reg32;
uint32_t reg32;
SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV;
@ -293,7 +293,7 @@ void rcc_set_pll_divisor(u8 div400)
*/
void rcc_set_pwm_divisor(pwm_clkdiv_t div)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC;
reg32 &= ~SYSCTL_RCC_PWMDIV_MASK;
@ -361,7 +361,7 @@ void rcc_wait_for_pll_ready(void)
*
* @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
*/
void rcc_change_pll_divisor(u8 pll_div400)
void rcc_change_pll_divisor(uint8_t pll_div400)
{
/* Bypass the PLL while its settings are modified */
rcc_pll_bypass_enable();
@ -372,7 +372,7 @@ void rcc_change_pll_divisor(u8 pll_div400)
/* Disable PLL bypass to derive the system clock from the PLL clock */
rcc_pll_bypass_disable();
/* Update the system clock frequency for housekeeping */
lm4f_rcc_sysclk_freq = (u32)400E6 / pll_div400;
lm4f_rcc_sysclk_freq = (uint32_t)400E6 / pll_div400;
}
/**
@ -380,15 +380,15 @@ void rcc_change_pll_divisor(u8 pll_div400)
*
* @return System clock frequency in Hz
*/
u32 rcc_get_system_clock_frequency(void)
uint32_t rcc_get_system_clock_frequency(void)
{
return lm4f_rcc_sysclk_freq;
}
/* Get the clock frequency corresponging to a given XTAL value */
static u32 xtal_to_freq(xtal_t xtal)
static uint32_t xtal_to_freq(xtal_t xtal)
{
const u32 freqs[] = {
const uint32_t freqs[] = {
4000000, /* XTAL_4M */
4096000, /* XTAL_4M_096 */
4915200, /* XTAL_4M_9152 */
@ -440,7 +440,7 @@ static u32 xtal_to_freq(xtal_t xtal)
*
* @return System clock frequency in Hz
*/
void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400)
void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
{
/*
* We could be using the PLL at this point, or we could be running of a

74
lib/lm4f/uart.c
View File

@ -90,7 +90,7 @@
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable(u32 uart)
void uart_enable(uint32_t uart)
{
UART_CTL(uart) |= (UART_CTL_UARTEN | UART_CTL_RXE | UART_CTL_TXE);
}
@ -100,7 +100,7 @@ void uart_enable(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable(u32 uart)
void uart_disable(uint32_t uart)
{
UART_CTL(uart) &= ~UART_CTL_UARTEN;
}
@ -111,9 +111,9 @@ void uart_disable(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] baud Baud rate in bits per second (bps).*
*/
void uart_set_baudrate(u32 uart, u32 baud)
void uart_set_baudrate(uint32_t uart, uint32_t baud)
{
u32 clock;
uint32_t clock;
/* Are we running off the internal clock or system clock? */
if (UART_CC(uart) == UART_CC_CS_PIOSC) {
@ -123,7 +123,7 @@ void uart_set_baudrate(u32 uart, u32 baud)
}
/* Find the baudrate divisor */
u32 div = (((clock * 8) / baud) + 1) / 2;
uint32_t div = (((clock * 8) / baud) + 1) / 2;
/* Set the baudrate divisors */
UART_IBRD(uart) = div / 64;
@ -136,18 +136,18 @@ void uart_set_baudrate(u32 uart, u32 baud)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] databits number of data bits per transmission.
*/
void uart_set_databits(u32 uart, u8 databits)
void uart_set_databits(uint32_t uart, uint8_t databits)
{
u32 reg32, bits32;
uint32_t reg32, bitint32_t;
/* This has the same effect as using UART_LCRH_WLEN_5/6/7/8 directly */
bits32 = (databits - 5) << 5;
bitint32_t = (databits - 5) << 5;
/* TODO: What about 9 data bits? */
reg32 = UART_LCRH(uart);
reg32 &= ~UART_LCRH_WLEN_MASK;
reg32 |= bits32;
reg32 |= bitint32_t;
UART_LCRH(uart) = reg32;
}
@ -157,7 +157,7 @@ void uart_set_databits(u32 uart, u8 databits)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] bits the requested number of stopbits, either 1 or 2.
*/
void uart_set_stopbits(u32 uart, u8 stopbits)
void uart_set_stopbits(uint32_t uart, uint8_t stopbits)
{
if (stopbits == 2) {
UART_LCRH(uart) |= UART_LCRH_STP2;
@ -172,9 +172,9 @@ void uart_set_stopbits(u32 uart, u8 stopbits)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] bits the requested parity scheme.
*/
void uart_set_parity(u32 uart, enum uart_parity parity)
void uart_set_parity(uint32_t uart, enum uart_parity parity)
{
u32 reg32;
uint32_t reg32;
reg32 = UART_LCRH(uart);
reg32 |= UART_LCRH_PEN;
@ -213,9 +213,9 @@ void uart_set_parity(u32 uart, enum uart_parity parity)
* UART_FLOWCTL_CTS -- enable the CTS line \n
* UART_FLOWCTL_RTS_CTS -- enable both RTS and CTS lines
*/
void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow)
{
u32 reg32 = UART_CTL(uart);
uint32_t reg32 = UART_CTL(uart);
reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN);
@ -235,7 +235,7 @@ void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_clock_from_piosc(u32 uart)
void uart_clock_from_piosc(uint32_t uart)
{
UART_CC(uart) = UART_CC_CS_PIOSC;
}
@ -245,7 +245,7 @@ void uart_clock_from_piosc(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_clock_from_sysclk(u32 uart)
void uart_clock_from_sysclk(uint32_t uart)
{
UART_CC(uart) = UART_CC_CS_SYSCLK;
}
@ -272,7 +272,7 @@ void uart_clock_from_sysclk(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] data data to send.
*/
void uart_send(u32 uart, u16 data)
void uart_send(uint32_t uart, uint16_t data)
{
data &= 0xFF;
UART_DR(uart) = data;
@ -284,7 +284,7 @@ void uart_send(u32 uart, u16 data)
* @param[in] uart UART block register address base @ref uart_reg_base
* @return data from the Rx FIFO.
*/
u16 uart_recv(u32 uart)
uint16_t uart_recv(uint32_t uart)
{
return UART_DR(uart) & UART_DR_DATA_MASK;
}
@ -300,7 +300,7 @@ u16 uart_recv(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_wait_send_ready(u32 uart)
void uart_wait_send_ready(uint32_t uart)
{
/* Wait until the Tx FIFO is no longer full */
while (UART_FR(uart) & UART_FR_TXFF);
@ -313,7 +313,7 @@ void uart_wait_send_ready(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_wait_recv_ready(u32 uart)
void uart_wait_recv_ready(uint32_t uart)
{
/* Wait until the Tx FIFO is no longer empty */
while (UART_FR(uart) & UART_FR_RXFE);
@ -327,7 +327,7 @@ void uart_wait_recv_ready(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_send_blocking(u32 uart, u16 data)
void uart_send_blocking(uint32_t uart, uint16_t data)
{
uart_wait_send_ready(uart);
uart_send(uart, data);
@ -341,7 +341,7 @@ void uart_send_blocking(u32 uart, u16 data)
* @param[in] uart UART block register address base @ref uart_reg_base
* @return data from the Rx FIFO.
*/
u16 uart_recv_blocking(u32 uart)
uint16_t uart_recv_blocking(uint32_t uart)
{
uart_wait_recv_ready(uart);
return uart_recv(uart);
@ -395,7 +395,7 @@ u16 uart_recv_blocking(u32 uart)
* @code{.c}
* void uart0_isr(void)
* {
* u32 serviced_irqs = 0;
* uint32_t serviced_irqs = 0;
*
* // Process individual IRQs
* if (uart_is_interrupt_source(UART0, UART_INT_RX)) {
@ -427,7 +427,7 @@ u16 uart_recv_blocking(u32 uart)
* @param[in] ints Interrupts which to enable. Any combination of interrupts may
* be specified by OR'ing then together
*/
void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_IM(uart) |= ints;
}
@ -443,7 +443,7 @@ void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
* @param[in] ints Interrupts which to disable. Any combination of interrupts
* may be specified by OR'ing then together
*/
void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_IM(uart) &= ~ints;
}
@ -456,7 +456,7 @@ void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_rx_interrupt(u32 uart)
void uart_enable_rx_interrupt(uint32_t uart)
{
uart_enable_interrupts(uart, UART_INT_RX);
}
@ -466,7 +466,7 @@ void uart_enable_rx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_rx_interrupt(u32 uart)
void uart_disable_rx_interrupt(uint32_t uart)
{
uart_disable_interrupts(uart, UART_INT_RX);
}
@ -479,7 +479,7 @@ void uart_disable_rx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_tx_interrupt(u32 uart)
void uart_enable_tx_interrupt(uint32_t uart)
{
uart_enable_interrupts(uart, UART_INT_TX);
}
@ -489,7 +489,7 @@ void uart_enable_tx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_tx_interrupt(u32 uart)
void uart_disable_tx_interrupt(uint32_t uart)
{
uart_disable_interrupts(uart, UART_INT_TX);
}
@ -505,7 +505,7 @@ void uart_disable_tx_interrupt(u32 uart)
* @param[in] ints Interrupts which to clear. Any combination of interrupts may
* be specified by OR'ing then together
*/
void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints)
void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_ICR(uart) |= ints;
}
@ -524,7 +524,7 @@ void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_rx_dma(u32 uart)
void uart_enable_rx_dma(uint32_t uart)
{
UART_DMACTL(uart) |= UART_DMACTL_RXDMAE;
}
@ -534,7 +534,7 @@ void uart_enable_rx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_rx_dma(u32 uart)
void uart_disable_rx_dma(uint32_t uart)
{
UART_DMACTL(uart) &= ~UART_DMACTL_RXDMAE;
}
@ -544,7 +544,7 @@ void uart_disable_rx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_tx_dma(u32 uart)
void uart_enable_tx_dma(uint32_t uart)
{
UART_DMACTL(uart) |= UART_DMACTL_TXDMAE;
}
@ -554,7 +554,7 @@ void uart_enable_tx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_tx_dma(u32 uart)
void uart_disable_tx_dma(uint32_t uart)
{
UART_DMACTL(uart) &= ~UART_DMACTL_TXDMAE;
}
@ -591,7 +591,7 @@ void uart_disable_tx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_fifo(u32 uart)
void uart_enable_fifo(uint32_t uart)
{
UART_LCRH(uart) |= UART_LCRH_FEN;
}
@ -601,7 +601,7 @@ void uart_enable_fifo(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_fifo(u32 uart)
void uart_disable_fifo(uint32_t uart)
{
UART_LCRH(uart) &= ~UART_LCRH_FEN;
}
@ -613,7 +613,7 @@ void uart_disable_fifo(u32 uart)
* @param[in] rx_level Trigger level for RX FIFO
* @param[in] tx_level Trigger level for TX FIFO
*/
void uart_set_fifo_trigger_levels(u32 uart,
void uart_set_fifo_trigger_levels(uint32_t uart,
enum uart_fifo_rx_trigger_level rx_level,
enum uart_fifo_tx_trigger_level tx_level)
{

64
lib/lm4f/usb_lm4f.c
View File

@ -176,24 +176,24 @@ static inline void lm4f_usb_soft_connect(void)
USB_POWER |= USB_POWER_SOFTCONN;
}
static void lm4f_set_address(usbd_device *usbd_dev, u8 addr)
static void lm4f_set_address(usbd_device *usbd_dev, uint8_t addr)
{
(void)usbd_dev;
USB_FADDR = addr & USB_FADDR_FUNCADDR_MASK;
}
static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback) (usbd_device *usbd_dev, u8 ep))
static void lm4f_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep))
{
(void)usbd_dev;
(void)type;
u8 reg8;
u16 fifo_size;
uint8_t reg8;
uint16_t fifo_size;
const bool dir_tx = addr & 0x80;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
/*
* We do not mess with the maximum packet size, but we can only allocate
@ -296,11 +296,11 @@ static void lm4f_endpoints_reset(usbd_device *usbd_dev)
usbd_dev->fifo_mem_top = 64;
}
static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
static void lm4f_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
(void)usbd_dev;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
const bool dir_tx = addr & 0x80;
if (ep == 0) {
@ -328,11 +328,11 @@ static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
}
}
static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
static uint8_t lm4f_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
{
(void)usbd_dev;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
const bool dir_tx = addr & 0x80;
if (ep == 0) {
@ -346,7 +346,7 @@ static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
}
}
static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
static void lm4f_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
{
(void)usbd_dev;
(void)addr;
@ -355,11 +355,11 @@ static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
/* NAK's are handled automatically by hardware. Move along. */
}
static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len)
static uint16_t lm4f_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len)
{
const u8 ep = addr & 0xf;
u16 i;
const uint8_t ep = addr & 0xf;
uint16_t i;
(void)usbd_dev;
@ -376,14 +376,14 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* performance, but we don't crash.
*/
for (i = 0; i < (len & ~0x3); i += 4) {
USB_FIFO32(ep) = *((u32 *)(buf + i));
USB_FIFO32(ep) = *((uint32_t *)(buf + i));
}
if (len & 0x2) {
USB_FIFO16(ep) = *((u16 *)(buf + i));
USB_FIFO16(ep) = *((uint16_t *)(buf + i));
i += 2;
}
if (len & 0x1) {
USB_FIFO8(ep) = *((u8 *)(buf + i));
USB_FIFO8(ep) = *((uint8_t *)(buf + i));
}
if (ep == 0) {
@ -405,15 +405,15 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
return i;
}
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len)
static uint16_t lm4f_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf,
uint16_t len)
{
(void)usbd_dev;
u16 rlen;
u8 ep = addr & 0xf;
uint16_t rlen;
uint8_t ep = addr & 0xf;
u16 fifoin = USB_RXCOUNT(ep);
uint16_t fifoin = USB_RXCOUNT(ep);
rlen = (fifoin > len) ? len : fifoin;
@ -423,14 +423,14 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
* performance, but we don't crash.
*/
for (len = 0; len < (rlen & ~0x3); len += 4) {
*((u32 *)(buf + len)) = USB_FIFO32(ep);
*((uint32_t *)(buf + len)) = USB_FIFO32(ep);
}
if (rlen & 0x2) {
*((u16 *)(buf + len)) = USB_FIFO16(ep);
*((uint16_t *)(buf + len)) = USB_FIFO16(ep);
len += 2;
}
if (rlen & 0x1) {
*((u8 *)(buf + len)) = USB_FIFO8(ep);
*((uint8_t *)(buf + len)) = USB_FIFO8(ep);
}
if (ep == 0) {
@ -454,8 +454,8 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
static void lm4f_poll(usbd_device *usbd_dev)
{
void (*tx_cb)(usbd_device *usbd_dev, u8 ea);
void (*rx_cb)(usbd_device *usbd_dev, u8 ea);
void (*tx_cb)(usbd_device *usbd_dev, uint8_t ea);
void (*rx_cb)(usbd_device *usbd_dev, uint8_t ea);
int i;
/*
@ -463,10 +463,10 @@ static void lm4f_poll(usbd_device *usbd_dev)
* interrupt, but we need the initial state in order to decide how to
* handle events.
*/
const u8 usb_is = USB_IS;
const u8 usb_rxis = USB_RXIS;
const u8 usb_txis = USB_TXIS;
const u8 usb_csrl0 = USB_CSRL0;
const uint8_t usb_is = USB_IS;
const uint8_t usb_rxis = USB_RXIS;
const uint8_t usb_txis = USB_TXIS;
const uint8_t usb_csrl0 = USB_CSRL0;
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) {
usbd_dev->user_callback_suspend();

2
lib/lpc13xx/gpio.c
View File

@ -33,7 +33,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc13xx/gpio.h>
void gpio_set(u32 gpioport, u16 gpios)
void gpio_set(uint32_t gpioport, uint16_t gpios)
{
GPIO_DATA(gpioport) = gpios;
}

4
lib/lpc17xx/gpio.c
View File

@ -34,12 +34,12 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc17xx/gpio.h>
void gpio_set(u32 gpioport, u32 gpios)
void gpio_set(uint32_t gpioport, uint32_t gpios)
{
GPIO_SET(gpioport) = gpios;
}
void gpio_clear(u32 gpioport, u32 gpios)
void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
GPIO_CLR(gpioport) = gpios;
}

6
lib/lpc43xx/gpio.c
View File

@ -34,17 +34,17 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc43xx/gpio.h>
void gpio_set(u32 gpioport, u32 gpios)
void gpio_set(uint32_t gpioport, uint32_t gpios)
{
GPIO_SET(gpioport) = gpios;
}
void gpio_clear(u32 gpioport, u32 gpios)
void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
GPIO_CLR(gpioport) = gpios;
}
void gpio_toggle(u32 gpioport, u32 gpios)
void gpio_toggle(uint32_t gpioport, uint32_t gpios)
{
GPIO_NOT(gpioport) = gpios;
}

4
lib/lpc43xx/i2c.c
View File

@ -79,7 +79,7 @@ void i2c0_tx_start(void)
}
/* transmit data byte */
void i2c0_tx_byte(u8 byte)
void i2c0_tx_byte(uint8_t byte)
{
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
@ -90,7 +90,7 @@ void i2c0_tx_byte(u8 byte)
}
/* receive data byte */
u8 i2c0_rx_byte(void)
uint8_t i2c0_rx_byte(void)
{
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;

2
lib/lpc43xx/scu.c
View File

@ -37,7 +37,7 @@ LGPL License Terms @ref lgpl_license
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for
* different I/O pins types
*/
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf)
{
MMIO32(group_pin) = scu_conf;
}

20
lib/lpc43xx/ssp.c
View File

@ -59,7 +59,7 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num);
/* Disable SSP */
void ssp_disable(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@ -77,14 +77,14 @@ void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
u8 clk_prescale,
uint8_t serial_clock_rate,
uint8_t clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option)
{
u32 ssp_port;
u32 clock;
uint32_t ssp_port;
uint32_t clock;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@ -112,9 +112,9 @@ void ssp_init(ssp_num_t ssp_num,
/*
* This Function Wait until Data RX Ready, and return Data Read from SSP.
*/
u16 ssp_read(ssp_num_t ssp_num)
uint16_t ssp_read(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@ -130,7 +130,7 @@ u16 ssp_read(ssp_num_t ssp_num)
void ssp_wait_until_not_busy(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@ -142,9 +142,9 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num)
}
/* This Function Wait Data TX Ready, and Write Data to SSP */
void ssp_write(ssp_num_t ssp_num, u16 data)
void ssp_write(ssp_num_t ssp_num, uint16_t data)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;

6
lib/sam/common/gpio.c
View File

@ -19,7 +19,7 @@
#include <libopencm3/sam/gpio.h>
void gpio_init(u32 port, u32 pins, enum gpio_flags flags)
void gpio_init(uint32_t port, uint32_t pins, enum gpio_flags flags)
{
switch (flags & 3) {
case GPIO_FLAG_GPINPUT:
@ -55,9 +55,9 @@ void gpio_init(u32 port, u32 pins, enum gpio_flags flags)
}
}
void gpio_toggle(u32 gpioport, u32 gpios)
void gpio_toggle(uint32_t gpioport, uint32_t gpios)
{
u32 odsr = PIO_ODSR(gpioport);
uint32_t odsr = PIO_ODSR(gpioport);
PIO_CODR(gpioport) = odsr & gpios;
PIO_SODR(gpioport) = ~odsr & gpios;
}

10
lib/sam/common/pmc.c
View File

@ -21,9 +21,9 @@
#include <libopencm3/sam/eefc.h>
/** Default peripheral clock frequency after reset. */
u32 pmc_mck_frequency = 4000000;
uint32_t pmc_mck_frequency = 4000000;
void pmc_xtal_enable(bool en, u8 startup_time)
void pmc_xtal_enable(bool en, uint8_t startup_time)
{
if (en) {
CKGR_MOR = (CKGR_MOR & ~CKGR_MOR_MOSCXTST_MASK) |
@ -35,14 +35,14 @@ void pmc_xtal_enable(bool en, u8 startup_time)
}
}
void pmc_plla_config(u8 mul, u8 div)
void pmc_plla_config(uint8_t mul, uint8_t div)
{
CKGR_PLLAR = CKGR_PLLAR_ONE | ((mul - 1) << 16) |
CKGR_PLLAR_PLLACOUNT_MASK | div;
while (!(PMC_SR & PMC_SR_LOCKA));
}
void pmc_peripheral_clock_enable(u8 pid)
void pmc_peripheral_clock_enable(uint8_t pid)
{
if (pid < 32) {
PMC_PCER0 = 1 << pid;
@ -51,7 +51,7 @@ void pmc_peripheral_clock_enable(u8 pid)
}
}
void pmc_peripheral_clock_disable(u8 pid)
void pmc_peripheral_clock_disable(uint8_t pid)
{
if (pid < 32) {
PMC_PCDR0 = 1 << pid;

32
lib/sam/common/usart.c
View File

@ -20,29 +20,29 @@
#include <libopencm3/sam/usart.h>
#include <libopencm3/sam/pmc.h>
void usart_set_baudrate(u32 usart, u32 baud)
void usart_set_baudrate(uint32_t usart, uint32_t baud)
{
USART_BRGR(usart) = pmc_mck_frequency / (16 * baud);
}
void usart_set_databits(u32 usart, int bits)
void usart_set_databits(uint32_t usart, int bits)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_CHRL_MASK) |
((bits - 5) << 6);
}
void usart_set_stopbits(u32 usart, enum usart_stopbits sb)
void usart_set_stopbits(uint32_t usart, enum usart_stopbits sb)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_NBSTOP_MASK) |
(sb << 12);
}
void usart_set_parity(u32 usart, enum usart_parity par)
void usart_set_parity(uint32_t usart, enum usart_parity par)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_PAR_MASK) | (par << 9);
}
void usart_set_mode(u32 usart, enum usart_mode mode)
void usart_set_mode(uint32_t usart, enum usart_mode mode)
{
USART_CR(usart) =
(mode & USART_MODE_RX) ? USART_CR_RXEN : USART_CR_RXDIS;
@ -50,59 +50,59 @@ void usart_set_mode(u32 usart, enum usart_mode mode)
: USART_CR_TXDIS;
}
void usart_set_flow_control(u32 usart, enum usart_flowcontrol fc)
void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol fc)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_MODE_MASK) |
(fc ? USART_MR_MODE_HW_HANDSHAKING : 0);
}
void usart_enable(u32 usart)
void usart_enable(uint32_t usart)
{
}
void usart_disable(u32 usart)
void usart_disable(uint32_t usart)
{
}
void usart_send(u32 usart, u16 data)
void usart_send(uint32_t usart, uint16_t data)
{
USART_THR(usart) = data;
}
u16 usart_recv(u32 usart)
uint16_t usart_recv(uint32_t usart)
{
return USART_RHR(usart) & 0x1f;
}
void usart_wait_send_ready(u32 usart)
void usart_wait_send_ready(uint32_t usart)
{
while ((USART_CSR(usart) & USART_CSR_TXRDY) == 0);
}
void usart_wait_recv_ready(u32 usart)
void usart_wait_recv_ready(uint32_t usart)
{
while ((USART_CSR(usart) & USART_CSR_RXRDY) == 0);
}
void usart_send_blocking(u32 usart, u16 data)
void usart_send_blocking(uint32_t usart, uint16_t data)
{
usart_wait_send_ready(usart);
usart_send(usart, data);
}
u16 usart_recv_blocking(u32 usart)
uint16_t usart_recv_blocking(uint32_t usart)
{
usart_wait_recv_ready(usart);
return usart_recv(usart);
}
void usart_enable_rx_interrupt(u32 usart)
void usart_enable_rx_interrupt(uint32_t usart)
{
USART_IER(usart) = USART_CSR_RXRDY;
}
void usart_disable_rx_interrupt(u32 usart)
void usart_disable_rx_interrupt(uint32_t usart)
{
USART_IDR(usart) = USART_CSR_RXRDY;
}

66
lib/stm32/can.c
View File

@ -69,7 +69,7 @@ system.
@param[in] canport Unsigned int32. CAN block register address base @ref
can_reg_base.
*/
void can_reset(u32 canport)
void can_reset(uint32_t canport)
{
if (canport == CAN1) {
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
@ -98,11 +98,11 @@ Initialize the selected CAN peripheral block.
@param[in] brp Unsigned int32. Baud rate prescaler.
@returns int 0 on success, 1 on initialization failure.
*/
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
bool loopback, bool silent)
{
volatile u32 wait_ack;
volatile uint32_t wait_ack;
int ret = 0;
/* Exit from sleep mode. */
@ -206,10 +206,10 @@ Initialize incoming message filter and assign to FIFO.
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
u32 fr1, u32 fr2, u32 fifo, bool enable)
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
{
u32 filter_select_bit = 0x00000001 << nr;
uint32_t filter_select_bit = 0x00000001 << nr;
/* Request initialization "enter". */
CAN_FMR(canport) |= CAN_FMR_FINIT;
@ -266,12 +266,12 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
u16 id2, u16 mask2, u32 fifo, bool enable)
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, false,
((u32)id1 << 16) | (u32)mask1,
((u32)id2 << 16) | (u32)mask2, fifo, enable);
((uint32_t)id1 << 16) | (uint32_t)mask1,
((uint32_t)id2 << 16) | (uint32_t)mask2, fifo, enable);
}
/*---------------------------------------------------------------------------*/
@ -284,8 +284,8 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
u32 fifo, bool enable)
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
@ -302,12 +302,12 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
u16 id3, u16 id4, u32 fifo, bool enable)
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, true,
((u32)id1 << 16) | (u32)id2,
((u32)id3 << 16) | (u32)id4, fifo, enable);
((uint32_t)id1 << 16) | (uint32_t)id2,
((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable);
}
/*---------------------------------------------------------------------------*/
@ -320,8 +320,8 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
u32 fifo, bool enable)
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
}
@ -332,7 +332,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] irq Unsigned int32. IRQ bit(s).
*/
void can_enable_irq(u32 canport, u32 irq)
void can_enable_irq(uint32_t canport, uint32_t irq)
{
CAN_IER(canport) |= irq;
}
@ -343,7 +343,7 @@ void can_enable_irq(u32 canport, u32 irq)
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] irq Unsigned int32. IRQ bit(s).
*/
void can_disable_irq(u32 canport, u32 irq)
void can_disable_irq(uint32_t canport, uint32_t irq)
{
CAN_IER(canport) &= ~irq;
}
@ -360,13 +360,13 @@ void can_disable_irq(u32 canport, u32 irq)
@returns int 0, 1 or 2 on success and depending on which outgoing mailbox got
selected. -1 if no mailbox was available and no transmission got queued.
*/
int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
{
int ret = 0;
u32 mailbox = 0;
uint32_t mailbox = 0;
union {
u8 data8[4];
u32 data32;
uint8_t data8[4];
uint32_t data32;
} tdlxr, tdhxr;
/* Check which transmit mailbox is empty if any. */
@ -451,7 +451,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] fifo Unsigned int8. FIFO id.
*/
void can_fifo_release(u32 canport, u8 fifo)
void can_fifo_release(uint32_t canport, uint8_t fifo)
{
if (fifo == 0) {
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
@ -473,15 +473,15 @@ void can_fifo_release(u32 canport, u8 fifo)
@param[out] length Unsigned int8 pointer. Length of message payload.
@param[out] data Unsigned int8[]. Message payload data.
*/
void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
bool *rtr, u32 *fmi, u8 *length, u8 *data)
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data)
{
u32 fifo_id = 0;
uint32_t fifo_id = 0;
union {
u8 data8[4];
u32 data32;
uint8_t data8[4];
uint32_t data32;
} rdlxr, rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
const uint32_t fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
fifo_id = fifoid_array[fifo];
@ -544,7 +544,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
}
}
bool can_available_mailbox(u32 canport)
bool can_available_mailbox(uint32_t canport)
{
return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2);
}

4
lib/stm32/common/crc_common_all.c
View File

@ -49,7 +49,7 @@ computation is complete.
@returns int32 Computed CRC result
*/
u32 crc_calculate(u32 data)
uint32_t crc_calculate(uint32_t data)
{
CRC_DR = data;
/* Data sheet says this blocks until it's ready.... */
@ -67,7 +67,7 @@ until the computation of each word is complete.
@returns int32 Final computed CRC result
*/
u32 crc_calculate_block(u32 *datap, int size)
uint32_t crc_calculate_block(uint32_t *datap, int size)
{
int i;

24
lib/stm32/common/dac_common_all.c
View File

@ -82,7 +82,7 @@ Both DAC channels are enabled, and both triggers are set to the same timer
dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT);
dma_set_read_from_memory(DMA2,DMA_CHANNEL3);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD);
dma_enable_channel(DMA2,DMA_CHANNEL3);
...
dac_trigger_enable(CHANNEL_D);
@ -320,12 +320,12 @@ void dac_trigger_disable(data_channel dac_channel)
Sets the digital to analog converter trigger source, which can be taken from
various timers, an external trigger or a software trigger.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref
@param[in] dac_trig_src uint32_t. Taken from @ref dac_trig2_sel or @ref
dac_trig1_sel or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_trigger_source(u32 dac_trig_src)
void dac_set_trigger_source(uint32_t dac_trig_src)
{
DAC_CR |= dac_trig_src;
}
@ -339,11 +339,11 @@ existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en
@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_generation(u32 dac_wave_ens)
void dac_set_waveform_generation(uint32_t dac_wave_ens)
{
DAC_CR |= dac_wave_ens;
}
@ -387,11 +387,11 @@ the signal output.
become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
@param[in] dac_mamp uint32_t. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_characteristics(u32 dac_mamp)
void dac_set_waveform_characteristics(uint32_t dac_mamp)
{
DAC_CR |= dac_mamp;
}
@ -405,12 +405,12 @@ data to be converted on a channel. The data can be aligned as follows:
@li right-aligned 12 bit data in bits 0-11
@li left aligned 12 bit data in bits 4-15
@param[in] dac_data u16 with appropriate alignment.
@param[in] dac_data uint16_t with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Alignment and size.
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format,
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel)
{
if (dac_channel == CHANNEL_1) {
@ -448,13 +448,13 @@ Loads the appropriate digital to analog converter dual data register with 12 or
simultaneous or independent analog output. The data in both channels are aligned
identically.
@param[in] dac_data1 u16 for channel 1 with appropriate alignment.
@param[in] dac_data2 u16 for channel 2 with appropriate alignment.
@param[in] dac_data1 uint16_t for channel 1 with appropriate alignment.
@param[in] dac_data2 uint16_t for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or
12 bit.
*/
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2,
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format)
{
switch (dac_data_format) {

58
lib/stm32/common/dma_common_f13.c
View File

@ -49,7 +49,7 @@ The channel is disabled and configuration registers are cleared.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_channel_reset(u32 dma, u8 channel)
void dma_channel_reset(uint32_t dma, uint8_t channel)
{
/* Disable channel and reset config bits. */
DMA_CCR(dma, channel) = 0;
@ -75,10 +75,10 @@ same channel may be cleared by using the logical OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts)
{
/* Get offset to interrupt flag location in channel field */
u32 flags = (interrupts << DMA_FLAG_OFFSET(channel));
uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
DMA_IFCR(dma) = flags;
}
@ -93,10 +93,10 @@ The interrupt flag for the channel is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupt)
{
/* get offset to interrupt flag location in channel field. */
u32 flag = (interrupt << DMA_FLAG_OFFSET(channel));
uint32_t flag = (interrupt << DMA_FLAG_OFFSET(channel));
return ((DMA_ISR(dma) & flag) > 0);
}
@ -111,7 +111,7 @@ intervention.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
@ -128,7 +128,7 @@ hardware priority.
@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
*/
void dma_set_priority(u32 dma, u8 channel, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
DMA_CCR(dma, channel) |= prio;
@ -145,7 +145,7 @@ alignment information if the source and destination widths do not match.
@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
@ -165,7 +165,7 @@ if the peripheral does not support byte or half-word writes.
dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
DMA_CCR(dma, channel) |= peripheral_size;
@ -182,7 +182,7 @@ value held by the base memory address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
@ -194,7 +194,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_memory_increment_mode(u32 dma, u8 channel)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
}
@ -210,7 +210,7 @@ value held by the base peripheral address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
@ -222,7 +222,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
}
@ -241,7 +241,7 @@ disabled here.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_circular_mode(u32 dma, u8 channel)
void dma_enable_circular_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
@ -256,7 +256,7 @@ The data direction is set to read from a peripheral.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_peripheral(u32 dma, u8 channel)
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
@ -270,7 +270,7 @@ The data direction is set to read from memory.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_memory(u32 dma, u8 channel)
void dma_set_read_from_memory(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
@ -282,7 +282,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
@ -294,7 +294,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
@ -306,7 +306,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
@ -318,7 +318,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
@ -330,7 +330,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
@ -342,7 +342,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
@ -354,7 +354,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_channel(u32 dma, u8 channel)
void dma_enable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
@ -369,7 +369,7 @@ disabled.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_channel(u32 dma, u8 channel)
void dma_disable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
@ -388,10 +388,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CPAR(dma, channel) = (u32) address;
DMA_CPAR(dma, channel) = (uint32_t) address;
}
}
@ -406,10 +406,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CMAR(dma, channel) = (u32) address;
DMA_CMAR(dma, channel) = (uint32_t) address;
}
}
@ -425,7 +425,7 @@ count is not changed if the channel is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number)
{
DMA_CNDTR(dma, channel) = number;
}

114
lib/stm32/common/dma_common_f24.c
View File

@ -57,7 +57,7 @@ The specified stream is disabled and configuration registers are cleared.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_stream_reset(u32 dma, u8 stream)
void dma_stream_reset(uint32_t dma, uint8_t stream)
{
/* Disable stream (must be done before register is otherwise changed). */
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
@ -72,7 +72,7 @@ void dma_stream_reset(u32 dma, u8 stream)
/* This is the default setting */
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
uint32_t mask = DMA_ISR_MASK(stream);
if (stream < 4) {
DMA_LIFCR(dma) |= mask;
} else {
@ -92,10 +92,10 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
{
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then
* reset.
*/
@ -117,12 +117,12 @@ The interrupt flag for the stream is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
{
/* get offset to interrupt flag location in stream field. Assumes
* stream and interrupt parameters are integers.
*/
u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream));
/* First four streams are in low register */
if (stream < 4) {
return ((DMA_LISR(dma) & flag) > 0);
@ -145,9 +145,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
*/
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
/* Disable circular and double buffer modes if memory to memory
* transfers are in effect. (Direct Mode is automatically disabled by
* hardware)
@ -173,7 +173,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
*/
void dma_set_priority(u32 dma, u8 stream, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK);
DMA_SCR(dma, stream) |= prio;
@ -192,7 +192,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
DMA_SCR(dma, stream) |= mem_size;
@ -213,7 +213,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
dma_st_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
DMA_SCR(dma, stream) |= peripheral_size;
@ -232,7 +232,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_memory_increment_mode(u32 dma, u8 stream)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
}
@ -246,7 +246,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_memory_increment_mode(u32 dma, u8 stream)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
}
@ -264,9 +264,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
u32 reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
}
@ -279,7 +279,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
}
@ -297,7 +297,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
}
@ -319,7 +319,7 @@ It is enabled automatically if double buffered mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_circular_mode(u32 dma, u8 stream)
void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
}
@ -338,7 +338,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
*/
void dma_channel_select(u32 dma, u8 stream, u32 channel)
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
{
DMA_SCR(dma, stream) |= channel;
}
@ -356,9 +356,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
*/
void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@ -375,9 +375,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
*/
void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@ -394,9 +394,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
*/
void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
if (memory == 1) {
reg32 |= DMA_SxCR_CT;
}
@ -417,7 +417,7 @@ the stream to be disabled and the transfer error flag to be set.
@returns unsigned int8. Memory buffer in use: 0 or 1
*/
u8 dma_get_target(u32 dma, u8 stream)
uint8_t dma_get_target(uint32_t dma, uint8_t stream)
{
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
return 1;
@ -441,7 +441,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_double_buffer_mode(u32 dma, u8 stream)
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
}
@ -453,7 +453,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_double_buffer_mode(u32 dma, u8 stream)
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
}
@ -470,7 +470,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_peripheral_flow_control(u32 dma, u8 stream)
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
}
@ -486,7 +486,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_dma_flow_control(u32 dma, u8 stream)
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
}
@ -498,7 +498,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
@ -511,7 +511,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
}
@ -523,7 +523,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
@ -536,7 +536,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}
@ -548,7 +548,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
@ -561,7 +561,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}
@ -573,7 +573,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_DMEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
@ -586,7 +586,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
}
@ -598,7 +598,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_FEIF);
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
@ -611,7 +611,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
}
@ -624,10 +624,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@returns u32 FIFO Status @ref dma_fifo_status
@returns uint32_t FIFO Status @ref dma_fifo_status
*/
u32 dma_fifo_status(u32 dma, u8 stream)
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
{
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
}
@ -643,7 +643,7 @@ mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode(u32 dma, u8 stream)
void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
}
@ -657,7 +657,7 @@ Data is transferred via a FIFO.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_mode(u32 dma, u8 stream)
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
}
@ -673,9 +673,9 @@ destination.
@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
*/
void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
{
u32 reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
DMA_SFCR(dma, stream) = (reg32 | threshold);
}
@ -686,7 +686,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_stream(u32 dma, u8 stream)
void dma_enable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
@ -700,7 +700,7 @@ void dma_enable_stream(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_stream(u32 dma, u8 stream)
void dma_disable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
}
@ -719,10 +719,10 @@ has no effect if the stream is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
{
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
DMA_SPAR(dma, stream) = (u32 *) address;
DMA_SPAR(dma, stream) = (uint32_t *) address;
}
}
@ -741,12 +741,12 @@ This is the default base memory address used in direct mode.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM0AR(dma, stream) = (u32 *) address;
DMA_SM0AR(dma, stream) = (uint32_t *) address;
}
}
@ -763,12 +763,12 @@ to change this in double buffer mode when the current target is memory area 0
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM1AR(dma, stream) = (u32 *) address;
DMA_SM1AR(dma, stream) = (uint32_t *) address;
}
}
@ -784,7 +784,7 @@ is not changed if the stream is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
{
DMA_SNDTR(dma, stream) = number;
}

24
lib/stm32/common/flash_common_f24.c
View File

@ -20,7 +20,7 @@
#include <libopencm3/stm32/flash.h>
static inline void flash_set_program_size(u32 psize)
static inline void flash_set_program_size(uint32_t psize)
{
FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
FLASH_CR |= psize;
@ -66,9 +66,9 @@ void flash_icache_reset(void)
FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
@ -151,7 +151,7 @@ void flash_wait_for_last_operation(void)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_double_word(u32 address, u64 data)
void flash_program_double_word(uint32_t address, uint64_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@ -170,7 +170,7 @@ void flash_program_double_word(u32 address, u64 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data)
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@ -189,7 +189,7 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X16);
@ -203,7 +203,7 @@ void flash_program_half_word(u32 address, u16 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data)
void flash_program_byte(uint32_t address, uint8_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X8);
@ -217,18 +217,18 @@ void flash_program_byte(u32 address, u8 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program(u32 address, u8 *data, u32 len)
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
{
/* TODO: Use dword and word size program operations where possible for
* turbo speed.
*/
u32 i;
uint32_t i;
for (i = 0; i < len; i++) {
flash_program_byte(address+i, data[i]);
}
}
void flash_erase_sector(u8 sector, u32 program_size)
void flash_erase_sector(uint8_t sector, uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@ -243,7 +243,7 @@ void flash_erase_sector(u8 sector, u32 program_size)
FLASH_CR &= ~(0xF << 3);
}
void flash_erase_all_sectors(u32 program_size)
void flash_erase_all_sectors(uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@ -255,7 +255,7 @@ void flash_erase_all_sectors(u32 program_size)
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
void flash_program_option_bytes(uint32_t data)
{
flash_wait_for_last_operation();

18
lib/stm32/common/gpio_common_all.c
View File

@ -39,7 +39,7 @@ Set one or more pins of the given GPIO port to 1 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_set(u32 gpioport, u16 gpios)
void gpio_set(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
@ -54,7 +54,7 @@ Clear one or more pins of the given GPIO port to 0 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
void gpio_clear(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = (gpios << 16);
}
@ -69,7 +69,7 @@ void gpio_clear(u32 gpioport, u16 gpios)
@return Unsigned int16 value of the pin values. The bit position of the pin
value returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios)
{
return gpio_port_read(gpioport) & gpios;
}
@ -84,7 +84,7 @@ Toggle one or more pins of the given GPIO port. This is not an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
void gpio_toggle(uint32_t gpioport, uint16_t gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
@ -98,9 +98,9 @@ valid pin data.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@return Unsigned int16. The value held in the specified GPIO port.
*/
u16 gpio_port_read(u32 gpioport)
uint16_t gpio_port_read(uint32_t gpioport)
{
return (u16)GPIO_IDR(gpioport);
return (uint16_t)GPIO_IDR(gpioport);
}
/*---------------------------------------------------------------------------*/
@ -111,7 +111,7 @@ Write a value to the given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] data Unsigned int16. The value to be written to the GPIO port.
*/
void gpio_port_write(u32 gpioport, u16 data)
void gpio_port_write(uint32_t gpioport, uint16_t data)
{
GPIO_ODR(gpioport) = data;
}
@ -128,9 +128,9 @@ reset.
If multiple pins are to be locked, use logical OR '|' to separate
them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios)
{
u32 reg32;
uint32_t reg32;
/* Special "Lock Key Writing Sequence", see datasheet. */
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */

18
lib/stm32/common/gpio_common_f24.c
View File

@ -86,10 +86,10 @@ gpio_pup
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios)
{
u16 i;
u32 moder, pupd;
uint16_t i;
uint32_t moder, pupd;
/*
* We want to set the config only for the pins mentioned in gpios,
@ -128,10 +128,10 @@ port.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios)
{
u16 i;
u32 ospeedr;
uint16_t i;
uint32_t ospeedr;
if (otype == 0x1) {
GPIO_OTYPER(gpioport) |= gpios;
@ -173,10 +173,10 @@ gpio_af_num
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios)
{
u16 i;
u32 afrl, afrh;
uint16_t i;
uint32_t afrl, afrh;
afrl = GPIO_AFRL(gpioport);
afrh = GPIO_AFRH(gpioport);

14
lib/stm32/common/hash_common_f24.c
View File

@ -40,7 +40,7 @@ Sets up the specified mode - either HASH or HMAC.
@param[in] mode unsigned int8. Hash processor mode: @ref hash_mode
*/
void hash_set_mode(u8 mode)
void hash_set_mode(uint8_t mode)
{
HASH_CR &= ~HASH_CR_MODE;
HASH_CR |= mode;
@ -54,7 +54,7 @@ Sets up the specified algorithm - either MD5 or SHA1.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_set_algorithm(u8 algorithm)
void hash_set_algorithm(uint8_t algorithm)
{
HASH_CR &= ~HASH_CR_ALGO;
HASH_CR |= algorithm;
@ -68,7 +68,7 @@ Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring.
@param[in] datatype unsigned int8. Hash data type: @ref hash_data_type
*/
void hash_set_data_type(u8 datatype)
void hash_set_data_type(uint8_t datatype)
{
HASH_CR &= ~HASH_CR_DATATYPE;
HASH_CR |= datatype;
@ -82,7 +82,7 @@ Sets up the specified key length: Long, Short.
@param[in] keylength unsigned int8. Hash data type: @ref hash_key_length
*/
void hash_set_key_length(u8 keylength)
void hash_set_key_length(uint8_t keylength)
{
HASH_CR &= ~HASH_CR_LKEY;
HASH_CR |= keylength;
@ -96,7 +96,7 @@ Specifies the number of valid bits in the last word.
@param[in] validbits unsigned int8. Number of valid bits.
*/
void hash_set_last_word_valid_bits(u8 validbits)
void hash_set_last_word_valid_bits(uint8_t validbits)
{
HASH_STR &= ~(HASH_STR_NBW);
HASH_STR |= 32 - validbits;
@ -122,7 +122,7 @@ Puts data into the HASH processor's queue.
@param[in] data unsigned int32. Hash input data.
*/
void hash_add_data(u32 data)
void hash_add_data(uint32_t data)
{
HASH_DIN = data;
}
@ -148,7 +148,7 @@ Makes a copy of the resulting hash.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_get_result(u32 *data)
void hash_get_result(uint32_t *data)
{
data[0] = HASH_HR[0];
data[1] = HASH_HR[1];

64
lib/stm32/common/i2c_common_all.c
View File

@ -49,7 +49,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
*/
void i2c_reset(u32 i2c)
void i2c_reset(uint32_t i2c)
{
switch (i2c) {
case I2C1:
@ -69,7 +69,7 @@ void i2c_reset(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_enable(u32 i2c)
void i2c_peripheral_enable(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_PE;
}
@ -83,7 +83,7 @@ In Slave mode, the peripheral is disabled only after communication has ended.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_disable(u32 i2c)
void i2c_peripheral_disable(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_PE;
}
@ -98,7 +98,7 @@ when the current bus activity is completed.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_start(u32 i2c)
void i2c_send_start(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_START;
}
@ -112,7 +112,7 @@ mode, or simply release the bus if in Slave mode.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_stop(u32 i2c)
void i2c_send_stop(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_STOP;
}
@ -124,7 +124,7 @@ Clear the "Send Stop" flag in the I2C config register
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_stop(u32 i2c)
void i2c_clear_stop(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_STOP;
}
@ -138,9 +138,9 @@ This sets an address for Slave mode operation, in 7 bit form.
@param[in] slave Unsigned int8. Slave address 0...127.
*/
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
{
I2C_OAR1(i2c) = (u16)(slave << 1);
I2C_OAR1(i2c) = (uint16_t)(slave << 1);
I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE;
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
}
@ -156,9 +156,9 @@ This sets an address for Slave mode operation, in 10 bit form.
@param[in] slave Unsigned int16. Slave address 0...1023.
*/
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave)
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
{
I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave);
I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_ADDMODE | slave);
}
/*---------------------------------------------------------------------------*/
@ -170,7 +170,7 @@ clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_fast_mode(u32 i2c)
void i2c_set_fast_mode(uint32_t i2c)
{
I2C_CCR(i2c) |= I2C_CCR_FS;
}
@ -184,7 +184,7 @@ actual clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_standard_mode(u32 i2c)
void i2c_set_standard_mode(uint32_t i2c)
{
I2C_CCR(i2c) &= ~I2C_CCR_FS;
}
@ -201,9 +201,9 @@ i2c_set_ccr
@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
*/
void i2c_set_clock_frequency(u32 i2c, u8 freq)
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */
reg16 |= freq;
I2C_CR2(i2c) = reg16;
@ -224,9 +224,9 @@ of the CCR field. It is a divisor of the peripheral clock frequency
@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095.
*/
void i2c_set_ccr(u32 i2c, u16 freq)
void i2c_set_ccr(uint32_t i2c, uint16_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */
reg16 |= freq;
I2C_CCR(i2c) = reg16;
@ -245,7 +245,7 @@ number.
@param[in] trise Unsigned int16. Rise Time Setting 0...63.
*/
void i2c_set_trise(u32 i2c, u16 trise)
void i2c_set_trise(uint32_t i2c, uint16_t trise)
{
I2C_TRISE(i2c) = trise;
}
@ -259,9 +259,9 @@ void i2c_set_trise(u32 i2c, u16 trise)
send @ref i2c_rw.
*/
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite)
{
I2C_DR(i2c) = (u8)((slave << 1) | readwrite);
I2C_DR(i2c) = (uint8_t)((slave << 1) | readwrite);
}
/*---------------------------------------------------------------------------*/
@ -271,7 +271,7 @@ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
@param[in] data Unsigned int8. Byte to send.
*/
void i2c_send_data(u32 i2c, u8 data)
void i2c_send_data(uint32_t i2c, uint8_t data)
{
I2C_DR(i2c) = data;
}
@ -281,7 +281,7 @@ void i2c_send_data(u32 i2c, u8 data)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
uint8_t i2c_get_data(u32 i2c)
uint8_t i2c_get_data(uint32_t i2c)
{
return I2C_DR(i2c) & 0xff;
}
@ -292,7 +292,7 @@ uint8_t i2c_get_data(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to enable.
*/
void i2c_enable_interrupt(u32 i2c, u32 interrupt)
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) |= interrupt;
}
@ -303,7 +303,7 @@ void i2c_enable_interrupt(u32 i2c, u32 interrupt)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to disable.
*/
void i2c_disable_interrupt(u32 i2c, u32 interrupt)
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) &= ~interrupt;
}
@ -314,7 +314,7 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt)
Enables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_ack(u32 i2c)
void i2c_enable_ack(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_ACK;
}
@ -325,7 +325,7 @@ void i2c_enable_ack(u32 i2c)
Disables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_ack(u32 i2c)
void i2c_disable_ack(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_ACK;
}
@ -336,7 +336,7 @@ void i2c_disable_ack(u32 i2c)
Causes the I2C controller to NACK the reception of the next byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_next(u32 i2c)
void i2c_nack_next(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_POS;
}
@ -348,7 +348,7 @@ Causes the I2C controller to NACK the reception of the current byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_current(u32 i2c)
void i2c_nack_current(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_POS;
}
@ -359,7 +359,7 @@ void i2c_nack_current(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle.
*/
void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle)
{
if (dutycycle == I2C_CCR_DUTY_DIV2) {
I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
@ -373,7 +373,7 @@ void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_dma(u32 i2c)
void i2c_enable_dma(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_DMAEN;
}
@ -383,7 +383,7 @@ void i2c_enable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_dma(u32 i2c)
void i2c_disable_dma(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
}
@ -393,7 +393,7 @@ void i2c_disable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_dma_last_transfer(u32 i2c)
void i2c_set_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_LAST;
}
@ -403,7 +403,7 @@ void i2c_set_dma_last_transfer(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_dma_last_transfer(u32 i2c)
void i2c_clear_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_LAST;
}

6
lib/stm32/common/iwdg_common_all.c
View File

@ -66,13 +66,13 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset
@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset
until a system reset is issued.
*/
void iwdg_set_period_ms(u32 period)
void iwdg_set_period_ms(uint32_t period)
{
u32 count, prescale, reload, exponent;
uint32_t count, prescale, reload, exponent;
/* Set the count to represent ticks of the 32kHz LSI clock */
count = (period << 5);

4
lib/stm32/common/pwr_common_all.c
View File

@ -57,10 +57,10 @@ This provides voltage level threshold detection. The result of detection is
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
or by setting the EXTI16 interrupt (see datasheet for configuration details).
@param[in] pvd_level u32. Taken from @ref pwr_pls.
@param[in] pvd_level uint32_t. Taken from @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(u32 pvd_level)
void pwr_enable_power_voltage_detect(uint32_t pvd_level)
{
PWR_CR &= ~PWR_CR_PLS_MASK;
PWR_CR |= (PWR_CR_PVDE | pvd_level);

4
lib/stm32/common/rtc_common_bcd.c
View File

@ -33,7 +33,7 @@
This sets the RTC synchronous and asynchronous prescalars.
*/
void rtc_set_prescaler(u32 sync, u32 async)
void rtc_set_prescaler(uint32_t sync, uint32_t async)
{
/*
* Even if only one of the two fields needs to be changed,
@ -86,7 +86,7 @@ void rtc_lock(void)
/** @brief Sets the wakeup time auto-reload value
*/
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel)
{
/* FTFM:
* The following sequence is required to configure or change the wakeup

100
lib/stm32/common/spi_common_all.c
View File

@ -79,7 +79,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
spi_reg_base.
*/
void spi_reset(u32 spi_peripheral)
void spi_reset(uint32_t spi_peripheral)
{
switch (spi_peripheral) {
case SPI1:
@ -119,9 +119,9 @@ spi_lsbfirst.
@returns int. Error code.
*/
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst)
{
u32 reg32 = SPI_CR1(spi);
uint32_t reg32 = SPI_CR1(spi);
/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
@ -152,7 +152,7 @@ The SPI peripheral is enabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable(u32 spi)
void spi_enable(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
}
@ -166,9 +166,9 @@ The SPI peripheral is disabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable(u32 spi)
void spi_disable(uint32_t spi)
{
u32 reg32;
uint32_t reg32;
reg32 = SPI_CR1(spi);
reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
@ -186,12 +186,12 @@ prevents the BSY flag from becoming unreliable.
@returns data Unsigned int16. 8 or 16 bit data from final read.
*/
u16 spi_clean_disable(u32 spi)
uint16_t spi_clean_disable(uint32_t spi)
{
/* Wait to receive last data */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
u16 data = SPI_DR(spi);
uint16_t data = SPI_DR(spi);
/* Wait to transmit last data */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@ -213,7 +213,7 @@ Data is written to the SPI interface.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_write(u32 spi, u16 data)
void spi_write(uint32_t spi, uint16_t data)
{
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR(spi) = data;
@ -229,7 +229,7 @@ finished.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_send(u32 spi, u16 data)
void spi_send(uint32_t spi, uint16_t data)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@ -247,7 +247,7 @@ Data is read from the SPI interface after the incoming transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_read(u32 spi)
uint16_t spi_read(uint32_t spi)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
@ -267,7 +267,7 @@ transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_xfer(u32 spi, u16 data)
uint16_t spi_xfer(uint32_t spi, uint16_t data)
{
spi_write(spi, data);
@ -287,7 +287,7 @@ The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_mode(u32 spi)
void spi_set_bidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
}
@ -302,7 +302,7 @@ clock wire and a unidirectional data wire.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_unidirectional_mode(u32 spi)
void spi_set_unidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
}
@ -317,7 +317,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_receive_only_mode(u32 spi)
void spi_set_bidirectional_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
@ -333,7 +333,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_transmit_only_mode(u32 spi)
void spi_set_bidirectional_transmit_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) |= SPI_CR1_BIDIOE;
@ -347,7 +347,7 @@ The SPI peripheral is set to use a CRC field for transmit and receive.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_crc(u32 spi)
void spi_enable_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCEN;
}
@ -358,7 +358,7 @@ void spi_enable_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_crc(u32 spi)
void spi_disable_crc(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
}
@ -373,7 +373,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_buffer(u32 spi)
void spi_set_next_tx_from_buffer(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
}
@ -388,7 +388,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_crc(u32 spi)
void spi_set_next_tx_from_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
@ -399,7 +399,7 @@ void spi_set_next_tx_from_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_8bit(u32 spi)
void spi_set_dff_8bit(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_DFF;
}
@ -410,7 +410,7 @@ void spi_set_dff_8bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_16bit(u32 spi)
void spi_set_dff_16bit(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_DFF;
}
@ -421,7 +421,7 @@ void spi_set_dff_16bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_full_duplex_mode(u32 spi)
void spi_set_full_duplex_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
}
@ -433,7 +433,7 @@ Transfers
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_receive_only_mode(u32 spi)
void spi_set_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_RXONLY;
}
@ -446,7 +446,7 @@ In slave mode the NSS hardware input is used as a select enable for the slave.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_software_slave_management(u32 spi)
void spi_disable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSM;
}
@ -460,7 +460,7 @@ enable/disable of the slave (@ref spi_set_nss_high).
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_software_slave_management(u32 spi)
void spi_enable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSM;
}
@ -477,7 +477,7 @@ otherwise
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_high(u32 spi)
void spi_set_nss_high(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSI;
}
@ -491,7 +491,7 @@ the NSS signal with a slave select disable signal.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_low(u32 spi)
void spi_set_nss_low(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSI;
}
@ -502,7 +502,7 @@ void spi_set_nss_low(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_lsb_first(u32 spi)
void spi_send_lsb_first(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
}
@ -513,7 +513,7 @@ void spi_send_lsb_first(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_msb_first(u32 spi)
void spi_send_msb_first(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
}
@ -528,9 +528,9 @@ values?
@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
*/
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
{
u32 reg32;
uint32_t reg32;
if (baudrate > 7) {
return;
@ -547,7 +547,7 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_master_mode(u32 spi)
void spi_set_master_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_MSTR;
}
@ -558,7 +558,7 @@ void spi_set_master_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_slave_mode(u32 spi)
void spi_set_slave_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_MSTR;
}
@ -569,7 +569,7 @@ void spi_set_slave_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_1(u32 spi)
void spi_set_clock_polarity_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPOL;
}
@ -580,7 +580,7 @@ void spi_set_clock_polarity_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_0(u32 spi)
void spi_set_clock_polarity_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPOL;
}
@ -591,7 +591,7 @@ void spi_set_clock_polarity_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_1(u32 spi)
void spi_set_clock_phase_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPHA;
}
@ -602,7 +602,7 @@ void spi_set_clock_phase_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_0(u32 spi)
void spi_set_clock_phase_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
}
@ -613,7 +613,7 @@ void spi_set_clock_phase_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_buffer_empty_interrupt(u32 spi)
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXEIE;
}
@ -624,7 +624,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_buffer_empty_interrupt(u32 spi)
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
}
@ -635,7 +635,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
}
@ -646,7 +646,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
}
@ -657,7 +657,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_error_interrupt(u32 spi)
void spi_enable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_ERRIE;
}
@ -668,7 +668,7 @@ void spi_enable_error_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_error_interrupt(u32 spi)
void spi_disable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
}
@ -682,7 +682,7 @@ SPI bus into slave mode. Multimaster mode is not possible.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_ss_output(u32 spi)
void spi_enable_ss_output(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_SSOE;
}
@ -697,7 +697,7 @@ becomes a slave enable.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_ss_output(u32 spi)
void spi_disable_ss_output(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
}
@ -712,7 +712,7 @@ SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_dma(u32 spi)
void spi_enable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
}
@ -723,7 +723,7 @@ void spi_enable_tx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_dma(u32 spi)
void spi_disable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
}
@ -738,7 +738,7 @@ for each SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_dma(u32 spi)
void spi_enable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
}
@ -749,7 +749,7 @@ void spi_enable_rx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_dma(u32 spi)
void spi_disable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
}

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