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Merge branch 'generalizations' into efm32

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This commit is contained in:
chrysn 2012-10-18 23:00:25 +02:00
commit 3a2e1c45aa
26 changed files with 88 additions and 900 deletions
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4
examples/lpc43xx/hackrf-jellybean/systick/systickdemo.c
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@ -20,8 +20,8 @@
#include <libopencm3/lpc43xx/gpio.h> #include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h> #include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/cgu.h> #include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/lpc43xx/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/lpc43xx/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/cm3/scs.h> #include <libopencm3/cm3/scs.h>
#include "../jellybean_conf.h" #include "../jellybean_conf.h"

2
examples/stm32/f1/lisa-m-1/can/can.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/stm32/can.h> #include <libopencm3/stm32/can.h>
struct can_tx_msg { struct can_tx_msg {

2
examples/stm32/f1/lisa-m-1/usb_dfu/usbdfu.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>

4
examples/stm32/f1/lisa-m-1/usb_hid/usbhid.c
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@ -21,7 +21,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/stm32/spi.h> #include <libopencm3/stm32/spi.h>
#include <libopencm3/stm32/otg_fs.h> #include <libopencm3/stm32/otg_fs.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
@ -32,7 +32,7 @@
#define INCLUDE_DFU_INTERFACE #define INCLUDE_DFU_INTERFACE
#ifdef INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>
#endif #endif

2
examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h> #include <libopencm3/stm32/usart.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <stdio.h> #include <stdio.h>
#include <errno.h> #include <errno.h>

2
examples/stm32/f1/obldc/can/can.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/stm32/can.h> #include <libopencm3/stm32/can.h>
struct can_tx_msg { struct can_tx_msg {

2
examples/stm32/f1/obldc/systick/systick.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
u32 temp32; u32 temp32;

2
examples/stm32/f1/other/systick/systick.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
u32 temp32; u32 temp32;

2
examples/stm32/f1/other/usb_dfu/usbdfu.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>

4
examples/stm32/f1/other/usb_hid/usbhid.c
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@ -20,7 +20,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/hid.h> #include <libopencm3/usb/hid.h>
@ -28,7 +28,7 @@
#define INCLUDE_DFU_INTERFACE #define INCLUDE_DFU_INTERFACE
#ifdef INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>
#endif #endif

2
examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c
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@ -22,7 +22,7 @@
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/usart.h> #include <libopencm3/stm32/usart.h>
#include <libopencm3/cm3/nvic.h> #include <libopencm3/cm3/nvic.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <stdio.h> #include <stdio.h>
#include <errno.h> #include <errno.h>

2
examples/stm32/f1/stm32-h103/usb_dfu/usbdfu.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>

4
examples/stm32/f1/stm32-h103/usb_hid/usbhid.c
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@ -20,7 +20,7 @@
#include <stdlib.h> #include <stdlib.h>
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/hid.h> #include <libopencm3/usb/hid.h>
@ -28,7 +28,7 @@
#define INCLUDE_DFU_INTERFACE #define INCLUDE_DFU_INTERFACE
#ifdef INCLUDE_DFU_INTERFACE #ifdef INCLUDE_DFU_INTERFACE
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>
#endif #endif

2
examples/stm32/f1/stm32-h103/usb_iap/usbiap.c
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@ -21,7 +21,7 @@
#include <libopencm3/stm32/f1/rcc.h> #include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/gpio.h> #include <libopencm3/stm32/f1/gpio.h>
#include <libopencm3/stm32/f1/flash.h> #include <libopencm3/stm32/f1/flash.h>
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
#include <libopencm3/usb/usbd.h> #include <libopencm3/usb/usbd.h>
#include <libopencm3/usb/dfu.h> #include <libopencm3/usb/dfu.h>

2
include/libopencm3/stm32/f4/scb.h → include/libopencm3/cm3/scb.h
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@ -21,7 +21,7 @@
#ifndef LIBOPENCM3_SCB_H #ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H #define LIBOPENCM3_SCB_H
#include <libopencm3/stm32/memorymap.h> #include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h> #include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */ /* --- SCB: Registers ------------------------------------------------------ */

36
include/libopencm3/stm32/systick.h → include/libopencm3/cm3/systick.h
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@ -1,22 +1,8 @@
/** @defgroup STM32F_systick_defines SysTick Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
* *
* This library is free software: you can redistribute it and/or modify * This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by * it under the terms of the GNU Lesser General Public License as published by
@ -31,13 +17,27 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License * You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
/** @defgroup CM3_systick_defines SysTick Defines
@brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
@ingroup CM3_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
LGPL License Terms @ref lgpl_license
*/
/**@{*/ /**@{*/
#ifndef LIBOPENCM3_SYSTICK_H #ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H #define LIBOPENCM3_SYSTICK_H
#include <libopencm3/stm32/memorymap.h> #include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h> #include <libopencm3/cm3/common.h>
/* --- SYSTICK registers --------------------------------------------------- */ /* --- SYSTICK registers --------------------------------------------------- */
@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license
#define STK_CTRL_CLKSOURCE (1 << 2) #define STK_CTRL_CLKSOURCE (1 << 2)
#define STK_CTRL_CLKSOURCE_LSB 2 #define STK_CTRL_CLKSOURCE_LSB 2
/** @defgroup systick_clksource Clock source selection /** @defgroup systick_clksource Clock source selection
@ingroup STM32F_systick_defines @ingroup CM3_systick_defines
@{*/ @{*/
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 #define STK_CTRL_CLKSOURCE_AHB_DIV8 0
@ -104,6 +104,8 @@ void systick_counter_enable(void);
void systick_counter_disable(void); void systick_counter_disable(void);
u8 systick_get_countflag(void); u8 systick_get_countflag(void);
u32 systick_get_calib(void);
END_DECLS END_DECLS
#endif #endif

88
include/libopencm3/lpc43xx/systick.h
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@ -1,88 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
#include <libopencm3/lpc43xx/memorymap.h>
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SYSTICK registers --------------------------------------------------- */
/* See also libopencm3\cm3\scs.h for details on SysTicks registers */
/* Control and status register (STK_CTRL) */
#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
/* reload value register (STK_LOAD) */
#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
/* current value register (STK_VAL) */
#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
/* calibration value register (STK_CALIB) */
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
/* --- STK_CTRL values ----------------------------------------------------- */
/* Bits [31:17] Reserved, must be kept cleared. */
/* COUNTFLAG: */
#define STK_CTRL_COUNTFLAG (1 << 16)
/* Bits [15:3] Reserved, must be kept cleared. */
/* CLKSOURCE: Clock source selection */
#define STK_CTRL_CLKSOURCE (1 << 2)
/* TICKINT: SysTick exception request enable */
#define STK_CTRL_TICKINT (1 << 1)
/* ENABLE: Counter enable */
#define STK_CTRL_ENABLE (1 << 0)
/* --- STK_LOAD values ----------------------------------------------------- */
/* Bits [31:24] Reserved, must be kept cleared. */
/* RELOAD[23:0]: RELOAD value */
/* --- STK_VAL values ------------------------------------------------------ */
/* Bits [31:24] Reserved, must be kept cleared. */
/* CURRENT[23:0]: Current counter value */
/* --- STK_CALIB values ---------------------------------------------------- */
/* NOREF: NOREF flag */
#define STK_CALIB_NOREF (1 << 31)
/* SKEW: SKEW flag */
#define STK_CALIB_SKEW (1 << 30)
/* Bits [29:24] Reserved, must be kept cleared. */
/* TENMS[23:0]: Calibration value */
/* --- Function Prototypes ------------------------------------------------- */
BEGIN_DECLS
void systick_set_reload(u32 value);
u32 systick_get_value(void);
void systick_set_clocksource(u8 clocksource);
void systick_interrupt_enable(void);
void systick_interrupt_disable(void);
void systick_counter_enable(void);
void systick_counter_disable(void);
u8 systick_get_countflag(void);
u32 systick_get_calib(void);
END_DECLS
#endif

307
include/libopencm3/stm32/f1/scb.h
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@ -1,307 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
/* Implementer[31:24]: Implementer code */
#define SCP_CPUID_IMPLEMENTER_LSB 24
/* Variant[23:20]: Variant number */
#define SCP_CPUID_VARIANT_LSB 20
/* Constant[19:16]: Reads as 0xF */
#define SCP_CPUID_CONSTANT_LSB 16
/* PartNo[15:4]: Part number of the processor */
#define SCP_CPUID_PARTNO_LSB 4
/* Revision[3:0]: Revision number */
#define SCP_CPUID_REVISION_LSB 0
/* --- SCB_ICSR values ----------------------------------------------------- */
/* NMIPENDSET: NMI set-pending bit */
#define SCB_ICSR_NMIPENDSET (1 << 31)
/* Bits [30:29]: reserved - must be kept cleared */
/* PENDSVSET: PendSV set-pending bit */
#define SCB_ICSR_PENDSVSET (1 << 28)
/* PENDSVCLR: PendSV clear-pending bit */
#define SCB_ICSR_PENDSVCLR (1 << 27)
/* PENDSTSET: SysTick exception set-pending bit */
#define SCB_ICSR_PENDSTSET (1 << 26)
/* PENDSTCLR: SysTick exception clear-pending bit */
#define SCB_ICSR_PENDSTCLR (1 << 25)
/* Bit 24: reserved - must be kept cleared */
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
#define SCB_ICSR_ISRPENDING (1 << 22)
/* VECTPENDING[21:12] Pending vector */
#define SCB_ICSR_VECTPENDING_LSB 12
/* RETOBASE: Return to base level */
#define SCB_ICSR_RETOBASE (1 << 11)
/* Bits [10:9]: reserved - must be kept cleared */
/* VECTACTIVE[8:0] Active vector */
#define SCB_ICSR_VECTACTIVE_LSB 0
/* --- SCB_VTOR values ----------------------------------------------------- */
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
/* --- SCB_AIRCR values ---------------------------------------------------- */
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
#define SCB_AIRCR_VECTKEY 0x05FA0000
/* ENDIANESS Data endianness bit */
#define SCB_AIRCR_ENDIANESS (1 << 15)
/* Bits [14:11]: reserved - must be kept cleared */
/* PRIGROUP[10:8]: Interrupt priority grouping field */
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_SHIFT 8
/* Bits [7:3]: reserved - must be kept cleared */
/* SYSRESETREQ System reset request */
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
/* VECTCLRACTIVE */
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
/* VECTRESET */
#define SCB_AIRCR_VECTRESET (1 << 0)
/* --- SCB_SCR values ------------------------------------------------------ */
/* Bits [31:5]: reserved - must be kept cleared */
/* SEVEONPEND Send Event on Pending bit */
#define SCB_SCR_SEVEONPEND (1 << 4)
/* Bit 3: reserved - must be kept cleared */
/* SLEEPDEEP */
#define SCB_SCR_SLEEPDEEP (1 << 2)
/* SLEEPONEXIT */
#define SCB_SCR_SLEEPONEXIT (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_CCR values ------------------------------------------------------ */
/* Bits [31:10]: reserved - must be kept cleared */
/* STKALIGN */
#define SCB_CCR_STKALIGN (1 << 9)
/* BFHFNMIGN */
#define SCB_CCR_BFHFNMIGN (1 << 8)
/* Bits [7:5]: reserved - must be kept cleared */
/* DIV_0_TRP */
#define SCB_CCR_DIV_0_TRP (1 << 4)
/* UNALIGN_TRP */
#define SCB_CCR_UNALIGN_TRP (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* USERSETMPEND */
#define SCB_CCR_USERSETMPEND (1 << 1)
/* NONBASETHRDENA */
#define SCB_CCR_NONBASETHRDENA (1 << 0)
/* --- SCB_SHPR1 values ---------------------------------------------------- */
/* Bits [31:24]: reserved - must be kept cleared */
/* PRI_6[23:16]: Priority of system handler 6, usage fault */
#define SCB_SHPR1_PRI_6_LSB 16
/* PRI_5[15:8]: Priority of system handler 5, bus fault */
#define SCB_SHPR1_PRI_5_LSB 8
/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
#define SCB_SHPR1_PRI_4_LSB 0
/* --- SCB_SHPR2 values ---------------------------------------------------- */
/* PRI_11[31:24]: Priority of system handler 11, SVCall */
#define SCB_SHPR2_PRI_11_LSB 24
/* Bits [23:0]: reserved - must be kept cleared */
/* --- SCB_SHPR3 values ---------------------------------------------------- */
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
#define SCB_SHPR3_PRI_15_LSB 24
/* PRI_14[23:16]: Priority of system handler 14, PendSV */
#define SCB_SHPR3_PRI_14_LSB 16
/* Bits [15:0]: reserved - must be kept cleared */
/* --- SCB_SHCSR values ---------------------------------------------------- */
/* Bits [31:19]: reserved - must be kept cleared */
/* USGFAULTENA: Usage fault enable */
#define SCB_SHCSR_USGFAULTENA (1 << 18)
/* BUSFAULTENA: Bus fault enable */
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
/* MEMFAULTENA: Memory management fault enable */
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
/* SVCALLPENDED: SVC call pending */
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
/* BUSFAULTPENDED: Bus fault exception pending */
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
/* MEMFAULTPENDED: Memory management fault exception pending */
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
/* USGFAULTPENDED: Usage fault exception pending */
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
/* SYSTICKACT: SysTick exception active */
#define SCB_SHCSR_SYSTICKACT (1 << 11)
/* PENDSVACT: PendSV exception active */
#define SCB_SHCSR_PENDSVACT (1 << 10)
/* Bit 9: reserved - must be kept cleared */
/* MONITORACT: Debug monitor active */
#define SCB_SHCSR_MONITORACT (1 << 8)
/* SVCALLACT: SVC call active */
#define SCB_SHCSR_SVCALLACT (1 << 7)
/* Bits [6:4]: reserved - must be kept cleared */
/* USGFAULTACT: Usage fault exception active */
#define SCB_SHCSR_USGFAULTACT (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* BUSFAULTACT: Bus fault exception active */
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
/* MEMFAULTACT: Memory management fault exception active */
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
/* --- SCB_CFSR values ----------------------------------------------------- */
/* Bits [31:26]: reserved - must be kept cleared */
/* DIVBYZERO: Divide by zero usage fault */
#define SCB_CFSR_DIVBYZERO (1 << 25)
/* UNALIGNED: Unaligned access usage fault */
#define SCB_CFSR_UNALIGNED (1 << 24)
/* Bits [23:20]: reserved - must be kept cleared */
/* NOCP: No coprocessor usage fault */
#define SCB_CFSR_NOCP (1 << 19)
/* INVPC: Invalid PC load usage fault */
#define SCB_CFSR_INVPC (1 << 18)
/* INVSTATE: Invalid state usage fault */
#define SCB_CFSR_INVSTATE (1 << 17)
/* UNDEFINSTR: Undefined instruction usage fault */
#define SCB_CFSR_UNDEFINSTR (1 << 16)
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
#define SCB_CFSR_BFARVALID (1 << 15)
/* Bits [14:13]: reserved - must be kept cleared */
/* STKERR: Bus fault on stacking for exception entry */
#define SCB_CFSR_STKERR (1 << 12)
/* UNSTKERR: Bus fault on unstacking for a return from exception */
#define SCB_CFSR_UNSTKERR (1 << 11)
/* IMPRECISERR: Imprecise data bus error */
#define SCB_CFSR_IMPRECISERR (1 << 10)
/* PRECISERR: Precise data bus error */
#define SCB_CFSR_PRECISERR (1 << 9)
/* IBUSERR: Instruction bus error */
#define SCB_CFSR_IBUSERR (1 << 8)
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
#define SCB_CFSR_MMARVALID (1 << 7)
/* Bits [6:5]: reserved - must be kept cleared */
/* MSTKERR: Memory manager fault on stacking for exception entry */
#define SCB_CFSR_MSTKERR (1 << 4)
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
#define SCB_CFSR_MUNSTKERR (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* DACCVIOL: Data access violation flag */
#define SCB_CFSR_DACCVIOL (1 << 1)
/* IACCVIOL: Instruction access violation flag */
#define SCB_CFSR_IACCVIOL (1 << 0)
/* --- SCB_HFSR values ----------------------------------------------------- */
/* DEBUG_VT: reserved for debug use */
#define SCB_HFSR_DEBUG_VT (1 << 31)
/* FORCED: Forced hard fault */
#define SCB_HFSR_FORCED (1 << 30)
/* Bits [29:2]: reserved - must be kept cleared */
/* VECTTBL: Vector table hard fault */
#define SCB_HFSR_VECTTBL (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_MMFAR values ---------------------------------------------------- */
/* MMFAR [31:0]: Memory management fault address */
/* --- SCB_BFAR values ----------------------------------------------------- */
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
END_DECLS
#endif

307
include/libopencm3/stm32/f2/scb.h
View File

@ -1,307 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
/* Implementer[31:24]: Implementer code */
#define SCP_CPUID_IMPLEMENTER_LSB 24
/* Variant[23:20]: Variant number */
#define SCP_CPUID_VARIANT_LSB 20
/* Constant[19:16]: Reads as 0xF */
#define SCP_CPUID_CONSTANT_LSB 16
/* PartNo[15:4]: Part number of the processor */
#define SCP_CPUID_PARTNO_LSB 4
/* Revision[3:0]: Revision number */
#define SCP_CPUID_REVISION_LSB 0
/* --- SCB_ICSR values ----------------------------------------------------- */
/* NMIPENDSET: NMI set-pending bit */
#define SCB_ICSR_NMIPENDSET (1 << 31)
/* Bits [30:29]: reserved - must be kept cleared */
/* PENDSVSET: PendSV set-pending bit */
#define SCB_ICSR_PENDSVSET (1 << 28)
/* PENDSVCLR: PendSV clear-pending bit */
#define SCB_ICSR_PENDSVCLR (1 << 27)
/* PENDSTSET: SysTick exception set-pending bit */
#define SCB_ICSR_PENDSTSET (1 << 26)
/* PENDSTCLR: SysTick exception clear-pending bit */
#define SCB_ICSR_PENDSTCLR (1 << 25)
/* Bit 24: reserved - must be kept cleared */
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
#define SCB_ICSR_ISRPENDING (1 << 22)
/* VECTPENDING[21:12] Pending vector */
#define SCB_ICSR_VECTPENDING_LSB 12
/* RETOBASE: Return to base level */
#define SCB_ICSR_RETOBASE (1 << 11)
/* Bits [10:9]: reserved - must be kept cleared */
/* VECTACTIVE[8:0] Active vector */
#define SCB_ICSR_VECTACTIVE_LSB 0
/* --- SCB_VTOR values ----------------------------------------------------- */
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
/* --- SCB_AIRCR values ---------------------------------------------------- */
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
#define SCB_AIRCR_VECTKEY 0x05FA0000
/* ENDIANESS Data endianness bit */
#define SCB_AIRCR_ENDIANESS (1 << 15)
/* Bits [14:11]: reserved - must be kept cleared */
/* PRIGROUP[10:8]: Interrupt priority grouping field */
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_SHIFT 8
/* Bits [7:3]: reserved - must be kept cleared */
/* SYSRESETREQ System reset request */
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
/* VECTCLRACTIVE */
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
/* VECTRESET */
#define SCB_AIRCR_VECTRESET (1 << 0)
/* --- SCB_SCR values ------------------------------------------------------ */
/* Bits [31:5]: reserved - must be kept cleared */
/* SEVEONPEND Send Event on Pending bit */
#define SCB_SCR_SEVEONPEND (1 << 4)
/* Bit 3: reserved - must be kept cleared */
/* SLEEPDEEP */
#define SCB_SCR_SLEEPDEEP (1 << 2)
/* SLEEPONEXIT */
#define SCB_SCR_SLEEPONEXIT (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_CCR values ------------------------------------------------------ */
/* Bits [31:10]: reserved - must be kept cleared */
/* STKALIGN */
#define SCB_CCR_STKALIGN (1 << 9)
/* BFHFNMIGN */
#define SCB_CCR_BFHFNMIGN (1 << 8)
/* Bits [7:5]: reserved - must be kept cleared */
/* DIV_0_TRP */
#define SCB_CCR_DIV_0_TRP (1 << 4)
/* UNALIGN_TRP */
#define SCB_CCR_UNALIGN_TRP (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* USERSETMPEND */
#define SCB_CCR_USERSETMPEND (1 << 1)
/* NONBASETHRDENA */
#define SCB_CCR_NONBASETHRDENA (1 << 0)
/* --- SCB_SHPR1 values ---------------------------------------------------- */
/* Bits [31:24]: reserved - must be kept cleared */
/* PRI_6[23:16]: Priority of system handler 6, usage fault */
#define SCB_SHPR1_PRI_6_LSB 16
/* PRI_5[15:8]: Priority of system handler 5, bus fault */
#define SCB_SHPR1_PRI_5_LSB 8
/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
#define SCB_SHPR1_PRI_4_LSB 0
/* --- SCB_SHPR2 values ---------------------------------------------------- */
/* PRI_11[31:24]: Priority of system handler 11, SVCall */
#define SCB_SHPR2_PRI_11_LSB 24
/* Bits [23:0]: reserved - must be kept cleared */
/* --- SCB_SHPR3 values ---------------------------------------------------- */
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
#define SCB_SHPR3_PRI_15_LSB 24
/* PRI_14[23:16]: Priority of system handler 14, PendSV */
#define SCB_SHPR3_PRI_14_LSB 16
/* Bits [15:0]: reserved - must be kept cleared */
/* --- SCB_SHCSR values ---------------------------------------------------- */
/* Bits [31:19]: reserved - must be kept cleared */
/* USGFAULTENA: Usage fault enable */
#define SCB_SHCSR_USGFAULTENA (1 << 18)
/* BUSFAULTENA: Bus fault enable */
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
/* MEMFAULTENA: Memory management fault enable */
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
/* SVCALLPENDED: SVC call pending */
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
/* BUSFAULTPENDED: Bus fault exception pending */
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
/* MEMFAULTPENDED: Memory management fault exception pending */
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
/* USGFAULTPENDED: Usage fault exception pending */
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
/* SYSTICKACT: SysTick exception active */
#define SCB_SHCSR_SYSTICKACT (1 << 11)
/* PENDSVACT: PendSV exception active */
#define SCB_SHCSR_PENDSVACT (1 << 10)
/* Bit 9: reserved - must be kept cleared */
/* MONITORACT: Debug monitor active */
#define SCB_SHCSR_MONITORACT (1 << 8)
/* SVCALLACT: SVC call active */
#define SCB_SHCSR_SVCALLACT (1 << 7)
/* Bits [6:4]: reserved - must be kept cleared */
/* USGFAULTACT: Usage fault exception active */
#define SCB_SHCSR_USGFAULTACT (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* BUSFAULTACT: Bus fault exception active */
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
/* MEMFAULTACT: Memory management fault exception active */
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
/* --- SCB_CFSR values ----------------------------------------------------- */
/* Bits [31:26]: reserved - must be kept cleared */
/* DIVBYZERO: Divide by zero usage fault */
#define SCB_CFSR_DIVBYZERO (1 << 25)
/* UNALIGNED: Unaligned access usage fault */
#define SCB_CFSR_UNALIGNED (1 << 24)
/* Bits [23:20]: reserved - must be kept cleared */
/* NOCP: No coprocessor usage fault */
#define SCB_CFSR_NOCP (1 << 19)
/* INVPC: Invalid PC load usage fault */
#define SCB_CFSR_INVPC (1 << 18)
/* INVSTATE: Invalid state usage fault */
#define SCB_CFSR_INVSTATE (1 << 17)
/* UNDEFINSTR: Undefined instruction usage fault */
#define SCB_CFSR_UNDEFINSTR (1 << 16)
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
#define SCB_CFSR_BFARVALID (1 << 15)
/* Bits [14:13]: reserved - must be kept cleared */
/* STKERR: Bus fault on stacking for exception entry */
#define SCB_CFSR_STKERR (1 << 12)
/* UNSTKERR: Bus fault on unstacking for a return from exception */
#define SCB_CFSR_UNSTKERR (1 << 11)
/* IMPRECISERR: Imprecise data bus error */
#define SCB_CFSR_IMPRECISERR (1 << 10)
/* PRECISERR: Precise data bus error */
#define SCB_CFSR_PRECISERR (1 << 9)
/* IBUSERR: Instruction bus error */
#define SCB_CFSR_IBUSERR (1 << 8)
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
#define SCB_CFSR_MMARVALID (1 << 7)
/* Bits [6:5]: reserved - must be kept cleared */
/* MSTKERR: Memory manager fault on stacking for exception entry */
#define SCB_CFSR_MSTKERR (1 << 4)
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
#define SCB_CFSR_MUNSTKERR (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* DACCVIOL: Data access violation flag */
#define SCB_CFSR_DACCVIOL (1 << 1)
/* IACCVIOL: Instruction access violation flag */
#define SCB_CFSR_IACCVIOL (1 << 0)
/* --- SCB_HFSR values ----------------------------------------------------- */
/* DEBUG_VT: reserved for debug use */
#define SCB_HFSR_DEBUG_VT (1 << 31)
/* FORCED: Forced hard fault */
#define SCB_HFSR_FORCED (1 << 30)
/* Bits [29:2]: reserved - must be kept cleared */
/* VECTTBL: Vector table hard fault */
#define SCB_HFSR_VECTTBL (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_MMFAR values ---------------------------------------------------- */
/* MMFAR [31:0]: Memory management fault address */
/* --- SCB_BFAR values ----------------------------------------------------- */
/* BFAR [31:0]: Bus fault address */
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS
void scb_reset_core(void);
void scb_reset_system(void);
void scb_set_priority_grouping(u32 prigroup);
/* TODO: */
END_DECLS
#endif

2
lib/stm32/f1/scb.c → lib/cm3/scb.c
View File

@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <libopencm3/stm32/f1/scb.h> #include <libopencm3/cm3/scb.h>
void scb_reset_core(void) void scb_reset_core(void)
{ {

52
lib/stm32/systick.c → lib/cm3/systick.c
View File

@ -1,27 +1,8 @@
/** @defgroup STM32F_systick_file SysTick
@ingroup STM32F_files
@brief <b>libopencm3 STM32Fxx System Tick Timer</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
This library supports the System Tick timer in the
STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
The System Tick timer is part of the ARM Cortex core. It is a 24 bit
down counter that can be configured with an automatical reload value.
LGPL License Terms @ref lgpl_license
*/
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
* *
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
* *
* This library is free software: you can redistribute it and/or modify * This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by * it under the terms of the GNU Lesser General Public License as published by
@ -36,9 +17,28 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License * You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
/** @defgroup CM3_systick_file SysTick
@ingroup CM3_files
@brief <b>libopencm3 Cortex System Tick Timer</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
This library supports the System Tick timer in ARM Cortex Microcontrollers.
The System Tick timer is part of the ARM Cortex core. It is a 24 bit
down counter that can be configured with an automatical reload value.
LGPL License Terms @ref lgpl_license
*/
/**@{*/ /**@{*/
#include <libopencm3/stm32/systick.h> #include <libopencm3/cm3/systick.h>
/*-----------------------------------------------------------------------------*/ /*-----------------------------------------------------------------------------*/
/** @brief SysTick Set the Automatic Reload Value. /** @brief SysTick Set the Automatic Reload Value.
@ -135,5 +135,15 @@ u8 systick_get_countflag(void)
else else
return 0; return 0;
} }
/*-----------------------------------------------------------------------------*/
/** @brief SysTick Get Calibration Value
@returns Current calibration value
*/
u32 systick_get_calib(void)
{
return (STK_CALIB&0x00FFFFFF);
}
/**@}*/ /**@}*/

69
lib/lpc43xx/systick.c
View File

@ -1,69 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/systick.h>
void systick_set_reload(u32 value)
{
STK_LOAD = (value & 0x00FFFFFF);
}
u32 systick_get_value(void)
{
return STK_VAL;
}
void systick_set_clocksource(u8 clocksource)
{
STK_CTRL |= clocksource;
}
void systick_interrupt_enable(void)
{
STK_CTRL |= STK_CTRL_TICKINT;
}
void systick_interrupt_disable(void)
{
STK_CTRL &= ~STK_CTRL_TICKINT;
}
void systick_counter_enable(void)
{
STK_CTRL |= STK_CTRL_ENABLE;
}
void systick_counter_disable(void)
{
STK_CTRL &= ~STK_CTRL_ENABLE;
}
u8 systick_get_countflag(void)
{
if (STK_CTRL & STK_CTRL_COUNTFLAG)
return 1;
else
return 0;
}
u32 systick_get_calib(void)
{
return (STK_CALIB&0x00FFFFFF);
}

35
lib/stm32/f2/scb.c
View File

@ -1,35 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/f2/scb.h>
void scb_reset_core(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
}
void scb_reset_system(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
}
void scb_set_priority_grouping(u32 prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
}

35
lib/stm32/f4/scb.c
View File

@ -1,35 +0,0 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/f4/scb.h>
void scb_reset_core(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
}
void scb_reset_system(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
}
void scb_set_priority_grouping(u32 prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
}

2
lib/stm32/f4/vector_chipset.c
View File

@ -18,7 +18,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <libopencm3/stm32/f4/scb.h> #include <libopencm3/cm3/scb.h>
static void pre_main(void) static void pre_main(void)
{ {

17
scripts/irq2nvic_h
View File

@ -27,6 +27,8 @@ method to achive the same thing with C preprocessor is known to the author.
(Neither is any non-portable method, for that matter.)""" (Neither is any non-portable method, for that matter.)"""
import sys import sys
import os
import os.path
import yaml import yaml
template_nvic_h = '''\ template_nvic_h = '''\
@ -58,8 +60,12 @@ template_nvic_h = '''\
@{{*/ @{{*/
BEGIN_DECLS
{isrprototypes} {isrprototypes}
END_DECLS
/**@}}*/ /**@}}*/
#endif /* {includeguard} */ #endif /* {includeguard} */
@ -112,12 +118,23 @@ def convert(infile, outfile_nvic, outfile_vectornvic):
outfile_nvic.write(template_nvic_h.format(**data)) outfile_nvic.write(template_nvic_h.format(**data))
outfile_vectornvic.write(template_vector_nvic_c.format(**data)) outfile_vectornvic.write(template_vector_nvic_c.format(**data))
def makeparentdir(filename):
try:
os.makedirs(os.path.dirname(filename))
except OSError:
# where is my 'mkdir -p'?
pass
def main(): def main():
infile = sys.argv[1] infile = sys.argv[1]
if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'):
raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml")
nvic_h = infile.replace('irq.yaml', 'nvic.h') nvic_h = infile.replace('irq.yaml', 'nvic.h')
vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c')
makeparentdir(nvic_h)
makeparentdir(vector_nvic_c)
convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'))
if __name__ == "__main__": if __name__ == "__main__":