Started some cleanup in the ADC headers and convenience code.
This commit is contained in:
Piotr Esden-Tempski
parent
4fbd42148a
commit
451a5e227d
@ -150,77 +150,194 @@
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/* --- ADC_CR1 values ------------------------------------------------------ */
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/* AWDEN: Analog watchdog enable on regular channels */
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#define ADC_CR1_AWDEN (1 << 23)
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/* JAWDEN: Analog watchdog enable on injected channels */
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#define ADC_CR1_JAWDEN (1 << 22)
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#define ADC_CR1_DUALMOD_LSB 16
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#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */
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#define ADC_CR1_DISCNUM_LSB 13
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#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB)
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/* Note: Bits [21:20] are reserved, and must be kept at reset value. */
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/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */
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/* Legend:
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* IND: Independent mode.
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* CRSISM: Combined regular simultaneous + injected simultaneous mode.
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* CRSATM: Combined regular simultaneous + alternate trigger mode.
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* CISFIM: Combined injected simultaneous + fast interleaved mode.
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* CISSIM: Combined injected simultaneous + slow interleaved mode.
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* ISM: Injected simultaneous mode only.
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* RSM: Regular simultaneous mode only.
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* FIM: Fast interleaved mode only.
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* SIM: Slow interleaved mode only.
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* ATM: Alternate trigger mode only.
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*/
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#define ADC_CR1_DUALMOD_IND (0x0 << 16)
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#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
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#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
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#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
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#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
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#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
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#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
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#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
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#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
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#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
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#define ADC_CR1_DUALMOD_MASK (0xF << 16)
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#define ADC_CR1_DUALMOD_SHIFT 16
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/* DISCNUM[2:0]: Discontinous mode channel count. */
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#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
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#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
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#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
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#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
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#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
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#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
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#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
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#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
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#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
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#define ADC_CR1_DISCNUM_SHIFT 13
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/* JDISCEN: Discontinous mode on injected channels. */
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#define ADC_CR1_JDISCEN (1 << 12)
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/* DISCEN: Discontinous mode on regular channels. */
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#define ADC_CR1_DISCEN (1 << 11)
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/* JAUTO: Automatic Injection Group conversion. */
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#define ADC_CR1_JAUTO (1 << 10)
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/* AWDSGL: Enable the watchdog on a single channel in scan mode. */
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#define ADC_CR1_AWDSGL (1 << 9)
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/* SCAN: Scan mode. */
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#define ADC_CR1_SCAN (1 << 8)
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/* JEOCIE: Interrupt enable for injected channels. */
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#define ADC_CR1_JEOCIE (1 << 7)
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/* AWDIE: Analog watchdog interrupt enable. */
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#define ADC_CR1_AWDIE (1 << 6)
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/* EOCIE: Interrupt enable EOC. */
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#define ADC_CR1_EOCIE (1 << 5)
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#define ADC_CR1_AWDCH_LSB 0
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#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB)
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/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
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/* Notes:
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* ADC1: Analog channel 16 and 17 are internally connected to the temperature
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* sensor and V_REFINT, respectively.
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* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
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* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
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*/
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#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
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#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
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#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
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#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
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#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
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#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
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#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
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#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
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#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
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#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
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#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
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#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
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#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
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#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
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#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
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#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
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#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
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#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
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#define ADC_CR1_AWDCH_MASK (0x1F << 0)
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#define ADC_CR1_AWDCH_SHIFT 0
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/* --- ADC_CR2 values ------------------------------------------------------ */
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#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */
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/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */
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#define ADC_CR2_TSVREFE (1 << 23)
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/* SWSTART: Start conversion of regular channels. */
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#define ADC_CR2_SWSTART (1 << 22)
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/* JSWSTART: Start conversion of injected channels. */
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#define ADC_CR2_JSWSTART (1 << 21)
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/* EXTTRIG: External trigger conversion mode for regular channels. */
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#define ADC_CR2_EXTTRIG (1 << 20)
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#define ADC_CR2_EXTSEL_LSB 17
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#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB)
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/* EXTSEL[2:0]: External event select for regular group. */
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/* The following are only valid for ADC1 and ADC2. */
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#define ADC_CR2_EXTSEL_TIM1_CC1 0x0
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#define ADC_CR2_EXTSEL_TIM1_CC2 0x1
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#define ADC_CR2_EXTSEL_TIM1_CC3 0x2
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#define ADC_CR2_EXTSEL_TIM2_CC2 0x3
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#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4
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#define ADC_CR2_EXTSEL_TIM4_CC4 0x5
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#define ADC_CR2_EXTSEL_EXTI11 0x6
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#define ADC_CR2_EXTSEL_SWSTART 0x7
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#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
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#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
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#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
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#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
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#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
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#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
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#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
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#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
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/* The following are only valid for ADC3 */
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#define ADC_CR2_EXTSEL_TIM3_CC1 0x0
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#define ADC_CR2_EXTSEL_TIM2_CC3 0x1
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#define ADC_CR2_EXTSEL_TIM8_CC1 0x3
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#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4
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#define ADC_CR2_EXTSEL_TIM5_CC1 0x5
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#define ADC_CR2_EXTSEL_TIM5_CC3 0x6
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#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
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#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
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#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
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#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
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#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
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#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
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/* Bit 16: reserved, must be kept cleared */
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#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
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#define ADC_CR2_EXTSEL_SHIFT 17
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/* Note: Bit 16 is reserved, must be kept at reset value. */
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/* JEXTTRIG: External trigger conversion mode for injected channels. */
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#define ADC_CR2_JEXTTRIG (1 << 15)
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#define ADC_CR2_JEXTSEL_LSB 12
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#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB)
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/* JEXTSEL[2:0]: External event selection for injected group. */
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/* The following are only valid for ADC1 and ADC2. */
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#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0
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#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1
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#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2
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#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3
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#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4
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#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5
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#define ADC_CR2_JEXTSEL_EXTI15 0x6
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#define ADC_CR2_JEXTSEL_JSWSTART 0x7
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#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
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#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
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#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
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#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
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#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
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#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
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#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
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#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12)
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/* The following are the different meanings for ADC3 only. */
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#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2
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#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3
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#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4
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#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5
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#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6
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#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
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#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
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#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
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#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
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#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
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#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
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#define ADC_CR2_JEXTSEL_SHIFT 12
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/* ALIGN: Data alignement. */
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#define ADC_CR2_ALIGN_RIGHT (0 << 11)
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#define ADC_CR2_ALIGN_LEFT (1 << 11)
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#define ADC_CR2_ALIGN (1 << 11)
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#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */
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/* Bits [7:4] have to be kept 0. */
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/* Note: Bits [10:9] are reserved and must be kept at reset value. */
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/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
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#define ADC_CR2_DMA (1 << 8)
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/* Note: Bits [7:4] are reserved and must be kept at reset value. */
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/* RSTCAL: Reset calibration. */
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#define ADC_CR2_RSTCAL (1 << 3)
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/* CAL: A/D Calibration. */
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#define ADC_CR2_CAL (1 << 2)
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/* CONT: Continous conversion. */
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#define ADC_CR2_CONT (1 << 1)
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#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */
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/* ADON: A/D converter On/Off. */
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/* Note: If any other bit in this register apart from ADON is changed at the
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* same time, then conversion is not triggered. This is to prevent triggering
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* an erroneous conversion.
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* Conclusion: Must be separately written.
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*/
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#define ADC_CR2_ADON (1 << 0)
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/* --- ADC_SMPR1 values ---------------------------------------------------- */
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@ -197,9 +197,9 @@ void adc_enable_external_trigger_regular(u32 adc, u8 trigger)
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{
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u32 reg32;
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reg32 = (ADC_CR2(adc) & 0xfff1ffff); /* Clear bits [19:17]. */
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reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
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if (trigger < 8)
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reg32 |= (trigger << ADC_CR2_EXTSEL_LSB);
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reg32 |= (trigger);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
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}
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@ -213,9 +213,9 @@ void adc_enable_external_trigger_injected(u32 adc, u8 trigger)
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{
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u32 reg32;
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reg32 = (ADC_CR2(adc) & 0xffff8fff); /* Clear bits [12:14]. */
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reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */
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if (trigger < 8)
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reg32 |= (trigger << ADC_CR2_JEXTSEL_LSB);
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reg32 |= (trigger);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
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}
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