stm32/fsmc.h: Document reserved bits.
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@ -90,10 +90,12 @@
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/* --- FSMC_BCRx values ---------------------------------------------------- */
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/* Bits [31:20]: Reserved. */
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/* CBURSTRW: Write burst enable */
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#define FSMC_BCR_CBURSTRW (1 << 19)
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/* Bits 18..16: Reserved. */
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/* Bits [18:16]: Reserved. */
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/* ASYNCWAIT: Wait signal during asynchronous transfers */
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#define FSMC_BCR_ASYNCWAIT (1 << 15)
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@ -138,6 +140,8 @@
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/* --- FSMC_BTRx values ---------------------------------------------------- */
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/* Bits [31:30]: Reserved. */
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/* ACCMOD[29:28]: Access mode */
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#define FSMC_BTR_ACCMOD (1 << 28)
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@ -161,6 +165,8 @@
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/* --- FSMC_BWTRx values --------------------------------------------------- */
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/* Bits [31:30]: Reserved. */
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/* ACCMOD[29:28]: Access mode */
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#define FSMC_BWTR_ACCMOD (1 << 28)
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@ -170,7 +176,7 @@
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/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
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#define FSMC_BWTR_CLKDIV (1 << 20)
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/* Bits 19..16: Reserved. */
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/* Bits [19..16]: Reserved. */
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/* DATAST[15:8]: Data-phase duration */
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#define FSMC_BWTR_DATAST (1 << 8)
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@ -183,6 +189,8 @@
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/* --- FSMC_PCRx values ---------------------------------------------------- */
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/* Bits [31:20]: Reserved. */
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/* ECCPS[19:17]: ECC page size */
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#define FSMC_PCR_ECCPS (1 << 17)
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@ -192,7 +200,7 @@
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/* TCLR[12:9]: CLE to RE delay */
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#define FSMC_PCR_TCLR (1 << 9)
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/* Bits 8..7: Reserved. */
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/* Bits [8..7]: Reserved. */
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/* ECCEN: ECC computation logic enable bit */
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#define FSMC_PCR_ECCEN (1 << 6)
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@ -213,6 +221,8 @@
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/* --- FSMC_SRx values ----------------------------------------------------- */
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/* Bits [31:7]: Reserved. */
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/* FEMPT: FIFO empty */
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#define FSMC_SR_FEMPT (1 << 6)
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