From e99896120be09c6d11efa08ada40373d39d57131 Mon Sep 17 00:00:00 2001 From: Oliver Dille Date: Fri, 7 Sep 2012 22:03:36 +0200 Subject: [PATCH 01/35] Random number generator register definitions. --- include/libopencm3/stm32/f4/rng.h | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 include/libopencm3/stm32/f4/rng.h diff --git a/include/libopencm3/stm32/f4/rng.h b/include/libopencm3/stm32/f4/rng.h new file mode 100644 index 00000000..5f517c8d --- /dev/null +++ b/include/libopencm3/stm32/f4/rng.h @@ -0,0 +1,61 @@ +/* + * This file is part of the libopencm3 project. + * + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RNG_H +#define LIBOPENCM3_RNG_H + +#include +#include + +/* --- Random number generator registers ----------------------------------- */ + +/* Control register */ +#define RNG_CR MMIO32(RNG_BASE + 0x00) + +/* Status register */ +#define RNG_SR MMIO32(RNG_BASE + 0x04) + +/* Data register */ +#define RNG_DR MMIO32(RNG_BASE + 0x08) + +/* --- RNG_CR values ------------------------------------------------------- */ + +/* RNG ENABLE */ +#define RNG_CR_EN (1 << 2) + +/* RNG interupt enable */ +#define RNG_CR_IE (1 << 3) + +/* --- RNG_SR values ------------------------------------------------------- */ + +/* Data ready */ +#define RNG_SR_DRDY (1 << 0) + +/* Clock error current status */ +#define RNG_SR_CECS (1 << 1) + +/* Seed error current status */ +#define RNG_SR_SECS (1 << 2) + +/* Clock error interup status */ +#define RNG_SR_CEIS (1 << 5) + +/* Seed error interup status */ +#define RNG_SR_SEIS (1 << 6) + +#endif From 099a5626dba3a885d4e5b6903a5a5a642c3d6638 Mon Sep 17 00:00:00 2001 From: Oliver Dille Date: Fri, 7 Sep 2012 22:43:10 +0200 Subject: [PATCH 02/35] Random number generator example. --- .../f4/stm32f4-discovery/random/Makefile | 25 ++++++ .../stm32/f4/stm32f4-discovery/random/README | 5 ++ .../f4/stm32f4-discovery/random/random.c | 88 +++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 examples/stm32/f4/stm32f4-discovery/random/Makefile create mode 100644 examples/stm32/f4/stm32f4-discovery/random/README create mode 100644 examples/stm32/f4/stm32f4-discovery/random/random.c diff --git a/examples/stm32/f4/stm32f4-discovery/random/Makefile b/examples/stm32/f4/stm32f4-discovery/random/Makefile new file mode 100644 index 00000000..4f06835c --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/random/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = random + +LDSCRIPT = ../stm32f4-discovery.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f4/stm32f4-discovery/random/README b/examples/stm32/f4/stm32f4-discovery/random/README new file mode 100644 index 00000000..875e6bfe --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/random/README @@ -0,0 +1,5 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example randomly blinks the green LED on the ST STM32F4DISCOVERY eval board. diff --git a/examples/stm32/f4/stm32f4-discovery/random/random.c b/examples/stm32/f4/stm32f4-discovery/random/random.c new file mode 100644 index 00000000..9305be3d --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/random/random.c @@ -0,0 +1,88 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + + +#include +#include +#include +#include + +static void rcc_setup(void) +{ + rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]); + + /* Enable GPIOD clock for onboard leds. */ + rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN); + + /* Enable rng clock */ + rcc_peripheral_enable_clock(&RCC_AHB2ENR, RCC_AHB2ENR_RNGEN); +} + +static void rng_setup(void) +{ + /* Enable interupt */ + /* Set the IE bit in the RNG_CR register. */ + RNG_CR |= RNG_CR_IE; + /* Enable the random number generation by setting the RNGEN bit in the RNG_CR + register. This activates the analog part, the RNG_LFSR and the error detector. + */ + RNG_CR |= RNG_CR_EN; +} + +static void gpio_setup(void) +{ + /* Setup onboard led */ + gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO12 | GPIO13); +} + +/* Tried to folow the guidelines in the stm32f4 user manual.*/ +static u32 random_int(void) +{ + static u32 last_value=0; + static u32 new_value=0; + u32 error_bits = 0; + error_bits = RNG_SR_SEIS | RNG_SR_CEIS; + while (new_value==last_value) { + /* Check for error flags and if data is ready. */ + if ( ((RNG_SR & error_bits) == 0) && ( (RNG_SR & RNG_SR_DRDY) == 1 ) ) + new_value=RNG_DR; + } + last_value=new_value; + return new_value; +} + + +int main(void) +{ + int i,j; + rcc_setup(); + gpio_setup(); + rng_setup(); + while(1){ + u32 rnd; + rnd = random_int(); + for(i=0;i!=32;++i){ + if ( (rnd & (1 << i))!=0 ) + gpio_set(GPIOD, GPIO12); + else + gpio_clear(GPIOD, GPIO12); + /* Delay */ + for(j=0;j!=5000000;++j) + __asm__("nop"); + } + } +} From ff83a1ae1c0764aff11d8cd50f1f0f8a27ea4757 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Sat, 15 Sep 2012 12:51:46 +0930 Subject: [PATCH 03/35] Setup to document entire project using doxygen. New doc directory with config files and generated html, LaTeX/pdf. Makefile provided for autogeneration and explanatory README. The project structure is hostile to doxygen, which can't cope with functions of the same name. Doxygen is run for each family separately, and separately for LaTeX generation. Customized layout files sort of "integrate" HTML, and separate pdfs are generated for each family. Not ideal but seems the best solution until doxygen changes, if at all. --- .gitignore | 5 +- Makefile | 8 +- doc/Doxyfile | 31 +++ Doxyfile => doc/Doxyfile_common | 299 ++++++++++++++------- DoxygenLayout.xml => doc/DoxygenLayout.xml | 23 +- doc/Makefile | 67 +++++ doc/README | 68 +++++ doc/cm3/Doxyfile | 24 ++ doc/cm3/DoxygenLayout_cm3.xml | 192 +++++++++++++ doc/lm3s/Doxyfile | 27 ++ doc/lm3s/Doxyfile_latex | 33 +++ doc/lm3s/DoxygenLayout_lm3s.xml | 193 +++++++++++++ doc/lm3s/header_lm3s.tex | 61 +++++ doc/lpc13xx/Doxyfile | 27 ++ doc/lpc13xx/Doxyfile_latex | 33 +++ doc/lpc13xx/DoxygenLayout_lpc13xx.xml | 193 +++++++++++++ doc/lpc13xx/header_lpc13xx.tex | 61 +++++ doc/lpc17xx/Doxyfile | 27 ++ doc/lpc17xx/Doxyfile_latex | 33 +++ doc/lpc17xx/DoxygenLayout_lpc17xx.xml | 193 +++++++++++++ doc/lpc17xx/header_lpc17xx.tex | 61 +++++ doc/lpc43xx/Doxyfile | 27 ++ doc/lpc43xx/Doxyfile_latex | 33 +++ doc/lpc43xx/DoxygenLayout_lpc43xx.xml | 193 +++++++++++++ doc/lpc43xx/header_lpc43xx.tex | 61 +++++ doc/stm32/Doxyfile | 30 +++ doc/stm32/DoxygenLayout_stm32.xml | 193 +++++++++++++ doc/stm32f1/Doxyfile | 32 +++ doc/stm32f1/Doxyfile_latex | 38 +++ doc/stm32f1/DoxygenLayout_stm32f1.xml | 193 +++++++++++++ doc/stm32f1/header_stm32f1.tex | 61 +++++ doc/stm32f2/Doxyfile | 30 +++ doc/stm32f2/Doxyfile_latex | 36 +++ doc/stm32f2/DoxygenLayout_stm32f2.xml | 193 +++++++++++++ doc/stm32f2/header_stm32f2.tex | 61 +++++ doc/stm32f4/Doxyfile | 30 +++ doc/stm32f4/Doxyfile_latex | 36 +++ doc/stm32f4/DoxygenLayout_stm32f4.xml | 193 +++++++++++++ doc/stm32f4/header_stm32f4.tex | 61 +++++ include/libopencm3/cm3/doc-cm3.h | 22 ++ include/libopencm3/cm3/docmain.h | 70 ----- include/libopencm3/docmain.dox | 21 ++ include/libopencm3/license.dox | 16 ++ include/libopencm3/lm3s/doc-lm3s.h | 32 +++ include/libopencm3/lpc13xx/doc-lpc13xx.h | 32 +++ include/libopencm3/lpc17xx/doc-lpc17xx.h | 32 +++ include/libopencm3/lpc43xx/doc-lpc43xx.h | 32 +++ include/libopencm3/stm32/doc-stm32f.h | 27 +- include/libopencm3/stm32/f1/doc-stm32f1.h | 29 +- include/libopencm3/stm32/f2/doc-stm32f2.h | 33 +++ include/libopencm3/stm32/f4/doc-stm32f4.h | 32 +++ 51 files changed, 3330 insertions(+), 208 deletions(-) create mode 100644 doc/Doxyfile rename Doxyfile => doc/Doxyfile_common (87%) rename DoxygenLayout.xml => doc/DoxygenLayout.xml (84%) create mode 100644 doc/Makefile create mode 100644 doc/README create mode 100644 doc/cm3/Doxyfile create mode 100644 doc/cm3/DoxygenLayout_cm3.xml create mode 100644 doc/lm3s/Doxyfile create mode 100644 doc/lm3s/Doxyfile_latex create mode 100644 doc/lm3s/DoxygenLayout_lm3s.xml create mode 100644 doc/lm3s/header_lm3s.tex create mode 100644 doc/lpc13xx/Doxyfile create mode 100644 doc/lpc13xx/Doxyfile_latex create mode 100644 doc/lpc13xx/DoxygenLayout_lpc13xx.xml create mode 100644 doc/lpc13xx/header_lpc13xx.tex create mode 100644 doc/lpc17xx/Doxyfile create mode 100644 doc/lpc17xx/Doxyfile_latex create mode 100644 doc/lpc17xx/DoxygenLayout_lpc17xx.xml create mode 100644 doc/lpc17xx/header_lpc17xx.tex create mode 100644 doc/lpc43xx/Doxyfile create mode 100644 doc/lpc43xx/Doxyfile_latex create mode 100644 doc/lpc43xx/DoxygenLayout_lpc43xx.xml create mode 100644 doc/lpc43xx/header_lpc43xx.tex create mode 100644 doc/stm32/Doxyfile create mode 100644 doc/stm32/DoxygenLayout_stm32.xml create mode 100644 doc/stm32f1/Doxyfile create mode 100644 doc/stm32f1/Doxyfile_latex create mode 100644 doc/stm32f1/DoxygenLayout_stm32f1.xml create mode 100644 doc/stm32f1/header_stm32f1.tex create mode 100644 doc/stm32f2/Doxyfile create mode 100644 doc/stm32f2/Doxyfile_latex create mode 100644 doc/stm32f2/DoxygenLayout_stm32f2.xml create mode 100644 doc/stm32f2/header_stm32f2.tex create mode 100644 doc/stm32f4/Doxyfile create mode 100644 doc/stm32f4/Doxyfile_latex create mode 100644 doc/stm32f4/DoxygenLayout_stm32f4.xml create mode 100644 doc/stm32f4/header_stm32f4.tex create mode 100644 include/libopencm3/cm3/doc-cm3.h delete mode 100644 include/libopencm3/cm3/docmain.h create mode 100644 include/libopencm3/docmain.dox create mode 100644 include/libopencm3/license.dox create mode 100644 include/libopencm3/lm3s/doc-lm3s.h create mode 100644 include/libopencm3/lpc13xx/doc-lpc13xx.h create mode 100644 include/libopencm3/lpc17xx/doc-lpc17xx.h create mode 100644 include/libopencm3/lpc43xx/doc-lpc43xx.h create mode 100644 include/libopencm3/stm32/f2/doc-stm32f2.h create mode 100644 include/libopencm3/stm32/f4/doc-stm32f4.h diff --git a/.gitignore b/.gitignore index 63b7b481..d5fb0657 100644 --- a/.gitignore +++ b/.gitignore @@ -12,4 +12,7 @@ *~ *.map *.log -doxygen/ +html/ +latex/ +*.pdf + diff --git a/Makefile b/Makefile index d4abe2f3..37c0c404 100644 --- a/Makefile +++ b/Makefile @@ -68,8 +68,8 @@ install: lib @printf " INSTALL scripts\n" $(Q)$(INSTALL) -m 0644 scripts/* $(SHAREDIR) -doxy: - doxygen Doxyfile +doc: + $(Q)$(MAKE) -C doc doc clean: $(Q)for i in $(addprefix lib/,$(TARGETS)) \ @@ -80,7 +80,7 @@ clean: fi; \ done @printf " CLEAN doxygen\n" - $(Q)rm -rf doxygen + $(Q)$(MAKE) -C doc clean -.PHONY: build lib examples install doxy clean +.PHONY: build lib examples install doc clean diff --git a/doc/Doxyfile b/doc/Doxyfile new file mode 100644 index 00000000..75f01f81 --- /dev/null +++ b/doc/Doxyfile @@ -0,0 +1,31 @@ +# Doxygen include file to generate top level entry document + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ./Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +INPUT = ../include/libopencm3/docmain.dox + +LAYOUT_FILE = DoxygenLayout.xml + +GENERATE_LATEX = NO + +TAGFILES = ./cm3/cm3.tag=../cm3/html \ + ./stm32/stm32.tag=../stm32/html \ + ./stm32f1/stm32f1.tag=../stm32f1/html \ + ./stm32f4/stm32f4.tag=../stm32f4/html \ + ./lm3s/lm3s.tag=../lm3s/html \ + ./lpc13xx/lpc13xx.tag=../lpc13xx/html \ + ./lpc17xx/lpc17xx.tag=../lpc17xx/html \ + ./lpc43xx/lpc43xx.tag=../lpc43xx/html + + diff --git a/Doxyfile b/doc/Doxyfile_common similarity index 87% rename from Doxyfile rename to doc/Doxyfile_common index 61e3593e..a0e9bf83 100644 --- a/Doxyfile +++ b/doc/Doxyfile_common @@ -1,4 +1,4 @@ -# Doxyfile 1.7.4 +# Doxyfile 1.8.2 # This file describes the settings to be used by the documentation system # doxygen (www.doxygen.org) for a project. @@ -22,8 +22,9 @@ DOXYFILE_ENCODING = UTF-8 -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. PROJECT_NAME = libopencm3 @@ -51,7 +52,7 @@ PROJECT_LOGO = # If a relative path is entered, it will be relative to the location # where doxygen was started. If left blank the current directory will be used. -OUTPUT_DIRECTORY = doxygen +OUTPUT_DIRECTORY = # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create # 4096 sub-directories (in 2 levels) under the output directory of each output @@ -118,14 +119,16 @@ INLINE_INHERITED_MEMB = NO # path before files name in the file list and in the header files. If set # to NO the shortest path that makes the file name unique will be used. -FULL_PATH_NAMES = YES +FULL_PATH_NAMES = NO # If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag # can be used to strip a user-defined part of the path. Stripping is # only done if one of the specified strings matches the left-hand part of # the path. The tag can be used to show relative paths in the file list. # If left blank the directory from which doxygen is run is used as the -# path to strip. +# path to strip. Note that you specify absolute paths here, but also +# relative paths, which will be relative from the directory where doxygen is +# started. STRIP_FROM_PATH = @@ -194,6 +197,13 @@ TAB_SIZE = 8 ALIASES = +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding +# "class=itcl::class" will allow you to use the command class in the +# itcl::class meaning. + +TCL_SUBST = + # Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C # sources only. Doxygen will then generate output that is more tailored for C. # For instance, some of the names that are used will be different. The list @@ -221,17 +231,34 @@ OPTIMIZE_FOR_FORTRAN = NO OPTIMIZE_OUTPUT_VHDL = NO # Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, +# and language is one of the parsers supported by doxygen: IDL, Java, +# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, +# C++. For instance to make doxygen treat .inc files as Fortran files (default +# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note +# that for custom extensions you also need to set FILE_PATTERNS otherwise the +# files are not read by doxygen. EXTENSION_MAPPING = +# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all +# comments according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you +# can mix doxygen, HTML, and XML commands with Markdown formatting. +# Disable only in case of backward compatibilities issues. + +MARKDOWN_SUPPORT = YES + +# When enabled doxygen tries to link words that correspond to documented classes, +# or namespaces to their corresponding documentation. Such a link can be +# prevented in individual cases by by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. + +AUTOLINK_SUPPORT = YES + # If you use STL classes (i.e. std::string, std::vector, etc.) but do not want # to include (a tag file for) the STL sources as input, then you should # set this tag to YES in order to let doxygen match functions declarations and @@ -252,12 +279,7 @@ CPP_CLI_SUPPORT = NO SIP_SUPPORT = NO -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. +# For Microsoft's IDL there are propget and propput attributes to indicate getter and setter methods for a property. Setting this option to YES (the default) will make doxygen replace the get and set methods by a property in the documentation. This will only work if the methods are indeed getting or setting a simple type. If this is not the case, or you want to show the methods anyway, you should set this option to NO. IDL_PROPERTY_SUPPORT = YES @@ -283,6 +305,15 @@ SUBGROUPING = YES INLINE_GROUPED_CLASSES = NO +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and +# unions with only public data fields will be shown inline in the documentation +# of the scope in which they are defined (i.e. file, namespace, or group +# documentation), provided this scope is documented. If set to NO (the default), +# structs, classes, and unions are shown on a separate page (for HTML and Man +# pages) or section (for LaTeX and RTF). + +INLINE_SIMPLE_STRUCTS = NO + # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum # is documented as struct, union, or enum with the name of the typedef. So # typedef struct TypeS {} TypeT, will appear in the documentation as a struct @@ -305,10 +336,21 @@ TYPEDEF_HIDES_STRUCT = NO # a logarithmic scale so increasing the size by one will roughly double the # memory usage. The cache size is given by this formula: # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols +# corresponding to a cache size of 2^16 = 65536 symbols. SYMBOL_CACHE_SIZE = 0 +# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be +# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given +# their name and scope. Since this can be an expensive process and often the +# same symbol appear multiple times in the code, doxygen keeps a cache of +# pre-resolved symbols. If the cache is too small doxygen will become slower. +# If the cache is too large, memory is wasted. The cache size is given by this +# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols. + +LOOKUP_CACHE_SIZE = 0 + #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- @@ -325,6 +367,11 @@ EXTRACT_ALL = YES EXTRACT_PRIVATE = YES +# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal +# scope will be included in the documentation. + +EXTRACT_PACKAGE = NO + # If the EXTRACT_STATIC tag is set to YES all static members of a file # will be included in the documentation. @@ -471,7 +518,7 @@ STRICT_PROTO_MATCHING = NO # disable (NO) the todo list. This list is created by putting \todo # commands in the documentation. -GENERATE_TODOLIST = YES +GENERATE_TODOLIST = NO # The GENERATE_TESTLIST tag can be used to enable (YES) or # disable (NO) the test list. This list is created by putting \test @@ -512,12 +559,6 @@ MAX_INITIALIZER_LINES = 30 SHOW_USED_FILES = YES -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = YES - # Set the SHOW_FILES tag to NO to disable the generation of the Files page. # This will remove the Files entry from the Quick Index and from the # Folder Tree View (if specified). The default is YES. @@ -543,12 +584,22 @@ FILE_VERSION_FILTER = # The LAYOUT_FILE tag can be used to specify a layout file which will be parsed # by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file +# output files in an output format independent way. To create the layout file # that represents doxygen's defaults, run doxygen with the -l option. # You can optionally specify a file name after the option, if omitted # DoxygenLayout.xml will be used as the name of the layout file. -LAYOUT_FILE = +LAYOUT_FILE = DoxygenLayout.xml + +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this +# feature you need bibtex and perl available in the search path. + +CITE_BIB_FILES = #--------------------------------------------------------------------------- # configuration options related to warning and progress messages @@ -599,7 +650,7 @@ WARN_FORMAT = "$file:$line: $text" # and error messages should be written. If left blank the output is written # to stderr. -WARN_LOGFILE = +WARN_LOGFILE = doxygen.log #--------------------------------------------------------------------------- # configuration options related to the input files @@ -610,7 +661,7 @@ WARN_LOGFILE = # directories like "/usr/src/myproject". Separate the files or directories # with spaces. -INPUT = include lib +INPUT = # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is @@ -634,15 +685,17 @@ FILE_PATTERNS = # should be searched for input files as well. Possible values are YES and NO. # If left blank NO is used. -RECURSIVE = YES +RECURSIVE = NO -# The EXCLUDE tag can be used to specify files and/or directories that should +# The EXCLUDE tag can be used to specify files and/or directories that should be # excluded from the INPUT source files. This way you can easily exclude a # subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to the directory from which doxygen is +# run. -EXCLUDE = +EXCLUDE = -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded # from the input. @@ -744,7 +797,7 @@ INLINE_SOURCES = NO # Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct # doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. +# fragments. Normal C, C++ and Fortran comments will always remain visible. STRIP_CODE_COMMENTS = NO @@ -829,12 +882,13 @@ HTML_FILE_EXTENSION = .html # The HTML_HEADER tag can be used to specify a personal HTML header for # each generated HTML page. If it is left blank doxygen will generate a # standard header. Note that when using a custom header you are responsible -# for the proper inclusion of any scripts and style sheets that doxygen +# for the proper inclusion of any scripts and style sheets that doxygen # needs, which is dependent on the configuration options used. -# It is adviced to generate a default header using "doxygen -w html +# It is advised to generate a default header using "doxygen -w html # header.html footer.html stylesheet.css YourConfigFile" and then modify # that header. Note that the header is subject to change so you typically -# have to redo this when upgrading to a newer version of doxygen or when changing the value of configuration settings such as GENERATE_TREEVIEW! +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! HTML_HEADER = @@ -846,13 +900,23 @@ HTML_FOOTER = # The HTML_STYLESHEET tag can be used to specify a user-defined cascading # style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! +# fine-tune the look of the HTML output. If left blank doxygen will +# generate a default style sheet. Note that it is recommended to use +# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this +# tag will in the future become obsolete. HTML_STYLESHEET = +# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional +# user-defined cascading style sheet that is included after the standard +# style sheets created by doxygen. Using this option one can overrule +# certain style aspects. This is preferred over using HTML_STYLESHEET +# since it does not replace the standard style sheet and is therefor more +# robust against future updates. Doxygen will copy the style sheet file to +# the output directory. + +HTML_EXTRA_STYLESHEET = + # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or # other source files which should be copied to the HTML output directory. Note # that these files will be copied to the base HTML output directory. Use the @@ -863,7 +927,7 @@ HTML_STYLESHEET = HTML_EXTRA_FILES = # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images +# Doxygen will adjust the colors in the style sheet and background images # according to this color. Hue is specified as an angle on a colorwheel, # see http://en.wikipedia.org/wiki/Hue for more information. # For instance the value 0 represents red, 60 is yellow, 120 is green, @@ -893,20 +957,23 @@ HTML_COLORSTYLE_GAMMA = 80 HTML_TIMESTAMP = YES -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - # If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML # documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). +# page has loaded. HTML_DYNAMIC_SECTIONS = NO +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of +# entries shown in the various tree structured indices initially; the user +# can expand and collapse entries dynamically later on. Doxygen will expand +# the tree to such a level that at most the specified number of entries are +# visible (unless a fully collapsed tree already exceeds this amount). +# So setting the number of entries 1 will produce a full collapsed tree by +# default. 0 is a special value representing an infinite number of entries +# and will result in a full expanded tree by default. + +HTML_INDEX_NUM_ENTRIES = 100 + # If the GENERATE_DOCSET tag is set to YES, additional index files # will be generated that can be used as input for Apple's Xcode 3 # integrated development environment, introduced with OSX 10.5 (Leopard). @@ -934,9 +1001,9 @@ DOCSET_FEEDNAME = "Doxygen generated docs" DOCSET_BUNDLE_ID = org.doxygen.Project -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely +# identify the documentation publisher. This should be a reverse domain-name +# style string, e.g. com.mycompany.MyDocSet.documentation. DOCSET_PUBLISHER_ID = org.doxygen.Publisher @@ -1058,19 +1125,14 @@ GENERATE_ECLIPSEHELP = NO ECLIPSE_DOC_ID = org.doxygen.Project -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. +# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) +# at top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. Since the tabs have the same information as the +# navigation tree you can set this option to NO if you already set +# GENERATE_TREEVIEW to YES. DISABLE_INDEX = NO -# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values -# (range [0,1..20]) that doxygen will group on one line in the generated HTML -# documentation. Note that a value of 0 will completely suppress the enum -# values from appearing in the overview section. - -ENUM_VALUES_PER_LINE = 4 - # The GENERATE_TREEVIEW tag is used to specify whether a tree-like index # structure should be generated to display hierarchical information. # If the tag value is set to YES, a side panel will be generated @@ -1078,13 +1140,17 @@ ENUM_VALUES_PER_LINE = 4 # is generated for HTML Help). For this to work a browser that supports # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). # Windows users are probably better off using the HTML help feature. +# Since the tree basically has the same information as the tab index you +# could consider to set DISABLE_INDEX to NO when enabling this option. GENERATE_TREEVIEW = YES -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. -USE_INLINE_TREES = YES +ENUM_VALUES_PER_LINE = 4 # If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be # used to set the initial width (in pixels) of the frame in which the tree @@ -1117,7 +1183,7 @@ FORMULA_TRANSPARENT = YES # (see http://www.mathjax.org) which uses client side Javascript for the # rendering instead of using prerendered bitmaps. Use this if you do not # have LaTeX installed or if you want to formulas look prettier in the HTML -# output. When enabled you also need to install MathJax separately and +# output. When enabled you may also need to install MathJax separately and # configure the path to it using the MATHJAX_RELPATH option. USE_MATHJAX = NO @@ -1126,13 +1192,19 @@ USE_MATHJAX = NO # HTML output directory using the MATHJAX_RELPATH option. The destination # directory should contain the MathJax.js script. For instance, if the mathjax # directory is located at the same level as the HTML output directory, then -# MATHJAX_RELPATH should be ../mathjax. The default value points to the -# mathjax.org site, so you can quickly see the result without installing -# MathJax, but it is strongly recommended to install a local copy of MathJax -# before deployment. +# MATHJAX_RELPATH should be ../mathjax. The default value points to +# the MathJax Content Delivery Network so you can quickly see the result without +# installing MathJax. +# However, it is strongly recommended to install a local +# copy of MathJax from http://www.mathjax.org before deployment. MATHJAX_RELPATH = http://www.mathjax.org/mathjax +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + # When the SEARCHENGINE tag is enabled doxygen will generate a search box # for the HTML output. The underlying search engine uses javascript # and DHTML and should work on any modern browser. Note that when using @@ -1246,6 +1318,12 @@ LATEX_HIDE_INDICES = NO LATEX_SOURCE_CODE = NO +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- @@ -1277,7 +1355,7 @@ COMPACT_RTF = NO RTF_HYPERLINKS = NO -# Load stylesheet definitions from file. Syntax is similar to doxygen's +# Load style sheet definitions from file. Syntax is similar to doxygen's # config file, i.e. a series of assignments. You only have to provide # replacements, missing definitions are set to their default value. @@ -1468,24 +1546,20 @@ SKIP_FUNCTION_MACROS = YES # Configuration::additions related to external references #--------------------------------------------------------------------------- -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: +# The TAGFILES option can be used to specify one or more tagfiles. For each +# tag file the location of the external documentation should be added. The +# format of a tag file without this location is as follows: # # TAGFILES = file1 file2 ... # Adding location for the tag files is done as follows: # # TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. +# where "loc1" and "loc2" can be relative or absolute paths +# or URLs. Note that each tag file must have a unique name (where the name does +# NOT include the path). If a tag file is not located in the directory in which +# doxygen is run, you must also specify the path to the tagfile here. -TAGFILES = +TAGFILES = # When a file name is specified after GENERATE_TAGFILE, doxygen will create # a tag file that is based on the input files it reads. @@ -1502,7 +1576,7 @@ ALLEXTERNALS = NO # in the modules index. If set to NO, only the current project's groups will # be listed. -EXTERNAL_GROUPS = YES +EXTERNAL_GROUPS = NO # The PERL_PATH should be the absolute path and name of the perl script # interpreter (i.e. the result of `which perl'). @@ -1551,13 +1625,12 @@ HAVE_DOT = YES DOT_NUM_THREADS = 0 -# By default doxygen will write a font called Helvetica to the output -# directory and reference it in all dot files that doxygen generates. -# When you want a differently looking font you can specify the font name -# using DOT_FONTNAME. You need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. DOT_FONTNAME = Helvetica @@ -1566,17 +1639,16 @@ DOT_FONTNAME = Helvetica DOT_FONTSIZE = 10 -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. DOT_FONTPATH = # If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen # will generate a graph for each documented class showing the direct and # indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. +# CLASS_DIAGRAMS tag to NO. CLASS_GRAPH = YES @@ -1598,6 +1670,15 @@ GROUP_GRAPHS = YES UML_LOOK = NO +# If the UML_LOOK tag is enabled, the fields and methods are shown inside +# the class node. If there are many fields or methods and many nodes the +# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS +# threshold limits the number of items for each type to make the size more +# managable. Set this to 0 for no limit. Note that the threshold may be +# exceeded by 50% before the limit is enforced. + +UML_LIMIT_NUM_FIELDS = 10 + # If set to YES, the inheritance and collaboration graphs will show the # relations between templates and their instances. @@ -1638,7 +1719,7 @@ CALLER_GRAPH = YES GRAPHICAL_HIERARCHY = YES -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES # then doxygen will show the dependencies a directory has on other directories # in a graphical way. The dependency relations are determined by the #include # relations between the files in the directories. @@ -1647,10 +1728,21 @@ DIRECTORY_GRAPH = YES # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images # generated by dot. Possible values are svg, png, jpg, or gif. -# If left blank png will be used. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). DOT_IMAGE_FORMAT = png +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + # The tag DOT_PATH can be used to specify the path where the dot tool can be # found. If left blank, it is assumed the dot tool can be found in the path. @@ -1714,3 +1806,4 @@ GENERATE_LEGEND = YES # the various graphs. DOT_CLEANUP = YES + diff --git a/DoxygenLayout.xml b/doc/DoxygenLayout.xml similarity index 84% rename from DoxygenLayout.xml rename to doc/DoxygenLayout.xml index 1a3be6ff..b958d14a 100644 --- a/DoxygenLayout.xml +++ b/doc/DoxygenLayout.xml @@ -3,23 +3,20 @@ - + + + + + + + + + + - - - - - - - - - - - - diff --git a/doc/Makefile b/doc/Makefile new file mode 100644 index 00000000..ff366771 --- /dev/null +++ b/doc/Makefile @@ -0,0 +1,67 @@ +# Makefile to build libopencm3 documentation + +# 14 September 2012 +# (C) Ken Sarkies + +doc: html latex + +html: cm3 stm32 stm32f1 stm32f2 stm32f4 lm3s lpc13 lpc17 lpc43 top + +cm3: + cd cm3/; doxygen + +lm3s: + cd lm3s/; doxygen + +lpc13: + cd lpc13xx/; doxygen + +lpc17: + cd lpc17xx/; doxygen + +lpc43: + cd lpc43xx/; doxygen + +stm32: + cd stm32/; doxygen + +stm32f1: + cd stm32f1/; doxygen + +stm32f2: + cd stm32f2/; doxygen + +stm32f4: + cd stm32f4/; doxygen + +top: + doxygen + +latex: stm32f1.pdf stm32f2.pdf stm32f4.pdf lm3s.pdf lpc13.pdf lpc17.pdf lpc43.pdf + +stm32f1.pdf: + cd stm32f1/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f1.pdf + +stm32f2.pdf: + cd stm32f2/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f2.pdf + +stm32f4.pdf: + cd stm32f4/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f4.pdf + +lm3s.pdf: + cd lm3s/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lm3s.pdf + +lpc13.pdf: + cd lpc13xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc13.pdf + +lpc17.pdf: + cd lpc17xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc17.pdf + +lpc43.pdf: + cd lpc43xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc43.pdf + +clean: + @rm -rf html/ */html/ */latex/ *.pdf */*.tag + +.PHONY: doc html cm3 lm3s lpc13 lpc17 lpc43 stm32 stm32f1 stm32f2 stm32f4 top latex + diff --git a/doc/README b/doc/README new file mode 100644 index 00000000..81d82624 --- /dev/null +++ b/doc/README @@ -0,0 +1,68 @@ +libopencm3 Documentation +14 September 2012 (C) K Sarkies +------------------------ + +To generate documentation run 'make doc' in the doc directory. This +runs doxygen for each of the processor families then integrates the whole. + +This requires doxygen v 1.8.2 or later. + +HTML, LaTeX, and pdf output is produced. + +Generation of HTML +------------------ + +To view HTML, point a browser to doc/html/index.html. + +The directory structure is important and should be maintained. +Each of the subdirectories has a configuration file, a layout file and +subdirectories for the documentation. Doxygen is intended to be run inside +these subdirectories. The Makefile will handle this in the appropriate +order. Tag files are generated and used by other doxygen runs to resolve links. + +Tagfiles contain all information about the document, and are used to resolve +references in other documents. The groups defined in these external documents +are not shown when EXTERNAL_GROUPS = NO. The high level tagfiles must be generated +before any others. + +As well as the processor families, a "cm3" subdirectory is used to generate +a tagfile to integrate the CM3 common core defines. + +Doxyfile_common holds global settings. + +OUTPUT_DIRECTORY blank so that the output is placed in the current directory. +RECURSIVE = NO +EXTERNAL_GROUPS = NO + +Each Doxyfile_include for a processor family has: + +@INCLUDE = ../Doxyfile_common +INPUT = specific directories needed, including /include/libopencm3/cm3 + in top directory to set the top level page and GNU license. +LAYOUT_FILE = DoxygenLayout_$processor.xml +WARN_LOGFILE = doxygen_$processor.log +TAGFILES = ../cm3/cm3.tag=../../cm3/html +GENERATE_TAGFILE = $processor.tag + +For the STM32 subfamilies, to include the common files references, add +TAGFILES += ../stm32/stm32.tag=../../stm32/html + +For the top level Doxyfile + +INPUT = ../include/libopencm3/docmain.dox to add in the main page text +LAYOUT_FILE = DoxygenLayout.xml +WARN_LOGFILE = doxygen.log +TAGFILES = cm3/cm3.tag=../cm3/html plus all families to be included. + +Generation of PDF +----------------- + +The pdf is generated via LaTeX. The needs for the documents differ from HTML +so separate Doxyfile_latex are provided. The pdf files are placed in the +doc directory. Each file contains all documentation for the core and common +features. + +@INCLUDE = ../Doxyfile_common +GENERATE_LATEX = YES +GENERATE_HTML = NO + diff --git a/doc/cm3/Doxyfile b/doc/cm3/Doxyfile new file mode 100644 index 00000000..7cf6496c --- /dev/null +++ b/doc/cm3/Doxyfile @@ -0,0 +1,24 @@ +# HTML Documentation for CM3 Core features. + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_cm3.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ + +LAYOUT_FILE = DoxygenLayout_cm3.xml + +GENERATE_TAGFILE = cm3.tag + diff --git a/doc/cm3/DoxygenLayout_cm3.xml b/doc/cm3/DoxygenLayout_cm3.xml new file mode 100644 index 00000000..462a24b5 --- /dev/null +++ b/doc/cm3/DoxygenLayout_cm3.xml @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/lm3s/Doxyfile b/doc/lm3s/Doxyfile new file mode 100644 index 00000000..9f5262c5 --- /dev/null +++ b/doc/lm3s/Doxyfile @@ -0,0 +1,27 @@ +# HTML Documentation for LM3S code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lm3s.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/lm3s \ + ../../lib/lm3s + +LAYOUT_FILE = DoxygenLayout_lm3s.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html + +GENERATE_TAGFILE = lm3s.tag + diff --git a/doc/lm3s/Doxyfile_latex b/doc/lm3s/Doxyfile_latex new file mode 100644 index 00000000..b4ffe3da --- /dev/null +++ b/doc/lm3s/Doxyfile_latex @@ -0,0 +1,33 @@ +# LaTeX Documentation for LM3S code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lm3s_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/lm3s \ + ../../lib/lm3s + +EXCLUDE = ../../include/libopencm3/lm3s/doc-lm3s.h + +LAYOUT_FILE = DoxygenLayout_lm3s.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_lm3s.tex + diff --git a/doc/lm3s/DoxygenLayout_lm3s.xml b/doc/lm3s/DoxygenLayout_lm3s.xml new file mode 100644 index 00000000..186acef7 --- /dev/null +++ b/doc/lm3s/DoxygenLayout_lm3s.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/lm3s/header_lm3s.tex b/doc/lm3s/header_lm3s.tex new file mode 100644 index 00000000..089dce39 --- /dev/null +++ b/doc/lm3s/header_lm3s.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ TI LM3S ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/lpc13xx/Doxyfile b/doc/lpc13xx/Doxyfile new file mode 100644 index 00000000..816c592c --- /dev/null +++ b/doc/lpc13xx/Doxyfile @@ -0,0 +1,27 @@ +# HTML Documentation for LPC13xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc13xx.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/lpc13xx \ + ../../lib/lpc13xx + +LAYOUT_FILE = DoxygenLayout_lpc13xx.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html + +GENERATE_TAGFILE = lpc13xx.tag + diff --git a/doc/lpc13xx/Doxyfile_latex b/doc/lpc13xx/Doxyfile_latex new file mode 100644 index 00000000..0bbcb5a2 --- /dev/null +++ b/doc/lpc13xx/Doxyfile_latex @@ -0,0 +1,33 @@ +# LaTeX Documentation for LPC13xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc13xx_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/lpc13xx/ \ + ../../lib/lpc13xx + +EXCLUDE = ../../include/libopencm3/lpc13xx/doc-lpc13xx.h + +LAYOUT_FILE = DoxygenLayout_lpc13xx.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_lpc13xx.tex + diff --git a/doc/lpc13xx/DoxygenLayout_lpc13xx.xml b/doc/lpc13xx/DoxygenLayout_lpc13xx.xml new file mode 100644 index 00000000..b6aacce5 --- /dev/null +++ b/doc/lpc13xx/DoxygenLayout_lpc13xx.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/lpc13xx/header_lpc13xx.tex b/doc/lpc13xx/header_lpc13xx.tex new file mode 100644 index 00000000..2f50154e --- /dev/null +++ b/doc/lpc13xx/header_lpc13xx.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ NXP LPC13xx ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/lpc17xx/Doxyfile b/doc/lpc17xx/Doxyfile new file mode 100644 index 00000000..f7f0fbbb --- /dev/null +++ b/doc/lpc17xx/Doxyfile @@ -0,0 +1,27 @@ +# HTML Documentation for LPC17xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc17xx.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/lpc17xx \ + ../../lib/lpc17xx + +LAYOUT_FILE = DoxygenLayout_lpc17xx.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html + +GENERATE_TAGFILE = lpc17xx.tag + diff --git a/doc/lpc17xx/Doxyfile_latex b/doc/lpc17xx/Doxyfile_latex new file mode 100644 index 00000000..d1f46508 --- /dev/null +++ b/doc/lpc17xx/Doxyfile_latex @@ -0,0 +1,33 @@ +# LaTeX Documentation for LPC17xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc17xx_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/lpc17xx/ \ + ../../lib/lpc17xx + +EXCLUDE = ../../include/libopencm3/lpc17xx/doc-lpc17xx.h + +LAYOUT_FILE = DoxygenLayout_lpc17xx.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_lpc17xx.tex + diff --git a/doc/lpc17xx/DoxygenLayout_lpc17xx.xml b/doc/lpc17xx/DoxygenLayout_lpc17xx.xml new file mode 100644 index 00000000..809a24c0 --- /dev/null +++ b/doc/lpc17xx/DoxygenLayout_lpc17xx.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/lpc17xx/header_lpc17xx.tex b/doc/lpc17xx/header_lpc17xx.tex new file mode 100644 index 00000000..3f8539da --- /dev/null +++ b/doc/lpc17xx/header_lpc17xx.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ NXP LPC17xx ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/lpc43xx/Doxyfile b/doc/lpc43xx/Doxyfile new file mode 100644 index 00000000..02bf5240 --- /dev/null +++ b/doc/lpc43xx/Doxyfile @@ -0,0 +1,27 @@ +# HTML Documentation for LPC43xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc43xx.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/lpc43xx \ + ../../lib/lpc43xx + +LAYOUT_FILE = DoxygenLayout_lpc43xx.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html + +GENERATE_TAGFILE = lpc43xx.tag + diff --git a/doc/lpc43xx/Doxyfile_latex b/doc/lpc43xx/Doxyfile_latex new file mode 100644 index 00000000..691de351 --- /dev/null +++ b/doc/lpc43xx/Doxyfile_latex @@ -0,0 +1,33 @@ +# LaTeX Documentation for LPC43xx code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_lpc43xx_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/lpc43xx/ \ + ../../lib/lpc43xx + +EXCLUDE = ../../include/libopencm3/lpc43xx/doc-lpc43xx.h + +LAYOUT_FILE = DoxygenLayout_lpc43xx.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_lpc43xx.tex + diff --git a/doc/lpc43xx/DoxygenLayout_lpc43xx.xml b/doc/lpc43xx/DoxygenLayout_lpc43xx.xml new file mode 100644 index 00000000..3cd37f0c --- /dev/null +++ b/doc/lpc43xx/DoxygenLayout_lpc43xx.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/lpc43xx/header_lpc43xx.tex b/doc/lpc43xx/header_lpc43xx.tex new file mode 100644 index 00000000..829e2e7b --- /dev/null +++ b/doc/lpc43xx/header_lpc43xx.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ NXP LPC43xx ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/stm32/Doxyfile b/doc/stm32/Doxyfile new file mode 100644 index 00000000..e39e0986 --- /dev/null +++ b/doc/stm32/Doxyfile @@ -0,0 +1,30 @@ +# HTML Documentation for STM32 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/stm32/ \ + ../../include/libopencm3/stm32/f1/nvic_f1.h \ + ../../include/libopencm3/stm32/f2/nvic_f2.h \ + ../../include/libopencm3/stm32/f4/nvic_f4.h \ + ../../lib/stm32/ + +LAYOUT_FILE = DoxygenLayout_stm32.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html + +GENERATE_TAGFILE = stm32.tag + diff --git a/doc/stm32/DoxygenLayout_stm32.xml b/doc/stm32/DoxygenLayout_stm32.xml new file mode 100644 index 00000000..439d3495 --- /dev/null +++ b/doc/stm32/DoxygenLayout_stm32.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/stm32f1/Doxyfile b/doc/stm32f1/Doxyfile new file mode 100644 index 00000000..f99e9f0b --- /dev/null +++ b/doc/stm32f1/Doxyfile @@ -0,0 +1,32 @@ +# HTML Documentation for STM32F1 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f1.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/stm32/f1 \ + ../../lib/stm32/f1 + +EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \ + ../../include/libopencm3/stm32/f1/usb_desc.h \ + ../../include/libopencm3/stm32/f1/nvic_f1.h + +LAYOUT_FILE = DoxygenLayout_stm32f1.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html \ + ../stm32/stm32.tag=../../stm32/html + +GENERATE_TAGFILE = stm32f1.tag + diff --git a/doc/stm32f1/Doxyfile_latex b/doc/stm32f1/Doxyfile_latex new file mode 100644 index 00000000..83d29693 --- /dev/null +++ b/doc/stm32f1/Doxyfile_latex @@ -0,0 +1,38 @@ +# LaTeX Documentation for STM32F1 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f1_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/stm32/ \ + ../../include/libopencm3/stm32/f1 \ + ../../lib/stm32/ \ + ../../lib/stm32/f1 + +EXCLUDE = ../../include/libopencm3/stm32/f1/doc-stm32f1.h \ + ../../include/libopencm3/stm32/doc-stm32f.h \ + ../../include/libopencm3/stm32/f1/usb.h \ + ../../include/libopencm3/stm32/f1/usb_desc.h \ + +LAYOUT_FILE = DoxygenLayout_stm32f1.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_stm32f1.tex + diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml new file mode 100644 index 00000000..912f2c40 --- /dev/null +++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/stm32f1/header_stm32f1.tex b/doc/stm32f1/header_stm32f1.tex new file mode 100644 index 00000000..19fb8db1 --- /dev/null +++ b/doc/stm32f1/header_stm32f1.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ STM STM32F1 ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/stm32f2/Doxyfile b/doc/stm32f2/Doxyfile new file mode 100644 index 00000000..8378e4fe --- /dev/null +++ b/doc/stm32f2/Doxyfile @@ -0,0 +1,30 @@ +# HTML Documentation for STM32F2 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f2.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/stm32/f2 \ + ../../lib/stm32/f2 + +EXCLUDE = ../../include/libopencm3/stm32/f2/nvic_f2.h + +LAYOUT_FILE = DoxygenLayout_stm32f2.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html \ + ../stm32/stm32.tag=../../stm32/html + +GENERATE_TAGFILE = stm32f2.tag + diff --git a/doc/stm32f2/Doxyfile_latex b/doc/stm32f2/Doxyfile_latex new file mode 100644 index 00000000..42881405 --- /dev/null +++ b/doc/stm32f2/Doxyfile_latex @@ -0,0 +1,36 @@ +# LaTeX Documentation for STM32F2 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f2_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/stm32/ \ + ../../include/libopencm3/stm32/f2 \ + ../../lib/stm32/ \ + ../../lib/stm32/f2 + +EXCLUDE = ../../include/libopencm3/stm32/f2/doc-stm32f2.h \ + ../../include/libopencm3/stm32/doc-stm32f.h + +LAYOUT_FILE = DoxygenLayout_stm32f2.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_stm32f2.tex + diff --git a/doc/stm32f2/DoxygenLayout_stm32f2.xml b/doc/stm32f2/DoxygenLayout_stm32f2.xml new file mode 100644 index 00000000..19bfd0ae --- /dev/null +++ b/doc/stm32f2/DoxygenLayout_stm32f2.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/stm32f2/header_stm32f2.tex b/doc/stm32f2/header_stm32f2.tex new file mode 100644 index 00000000..d65c4f0a --- /dev/null +++ b/doc/stm32f2/header_stm32f2.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ STM STM32F2 ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/doc/stm32f4/Doxyfile b/doc/stm32f4/Doxyfile new file mode 100644 index 00000000..f86895b2 --- /dev/null +++ b/doc/stm32f4/Doxyfile @@ -0,0 +1,30 @@ +# HTML Documentation for STM32F4 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f4.log + +INPUT = ../../include/libopencm3/license.dox \ + ../../include/libopencm3/stm32/f4 \ + ../../lib/stm32/f4 + +EXCLUDE = ../../include/libopencm3/stm32/f4/nvic_f4.h + +LAYOUT_FILE = DoxygenLayout_stm32f4.xml + +TAGFILES = ../cm3/cm3.tag=../../cm3/html \ + ../stm32/stm32.tag=../../stm32/html + +GENERATE_TAGFILE = stm32f4.tag + diff --git a/doc/stm32f4/Doxyfile_latex b/doc/stm32f4/Doxyfile_latex new file mode 100644 index 00000000..3c7da2e1 --- /dev/null +++ b/doc/stm32f4/Doxyfile_latex @@ -0,0 +1,36 @@ +# LaTeX Documentation for STM32F4 code level + +# 14 September 2012 +# (C) Ken Sarkies + +#--------------------------------------------------------------------------- +# Common Include File +#--------------------------------------------------------------------------- + +@INCLUDE = ../Doxyfile_common + +#--------------------------------------------------------------------------- +# Local settings +#--------------------------------------------------------------------------- + +WARN_LOGFILE = doxygen_stm32f4_latex.log + +INPUT = ../../include/libopencm3/docmain.dox \ + ../../include/libopencm3/license.dox \ + ../../include/libopencm3/cm3/ \ + ../../include/libopencm3/stm32/ \ + ../../include/libopencm3/stm32/f4 \ + ../../lib/stm32/ \ + ../../lib/stm32/f4 + +EXCLUDE = ../../include/libopencm3/stm32/f4/doc-stm32f4.h \ + ../../include/libopencm3/stm32/doc-stm32f.h + +LAYOUT_FILE = DoxygenLayout_stm32f4.xml + +GENERATE_HTML = NO + +GENERATE_LATEX = YES + +LATEX_HEADER = header_stm32f4.tex + diff --git a/doc/stm32f4/DoxygenLayout_stm32f4.xml b/doc/stm32f4/DoxygenLayout_stm32f4.xml new file mode 100644 index 00000000..214320a7 --- /dev/null +++ b/doc/stm32f4/DoxygenLayout_stm32f4.xml @@ -0,0 +1,193 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/doc/stm32f4/header_stm32f4.tex b/doc/stm32f4/header_stm32f4.tex new file mode 100644 index 00000000..e634ef2b --- /dev/null +++ b/doc/stm32f4/header_stm32f4.tex @@ -0,0 +1,61 @@ +\documentclass{book} +\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry} +\usepackage{makeidx} +\usepackage{natbib} +\usepackage{graphicx} +\usepackage{multicol} +\usepackage{float} +\usepackage{listings} +\usepackage{color} +\usepackage{ifthen} +\usepackage[table]{xcolor} +\usepackage{textcomp} +\usepackage{alltt} +\usepackage{ifpdf} +\ifpdf +\usepackage[pdftex, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\else +\usepackage[ps2pdf, + pagebackref=true, + colorlinks=true, + linkcolor=blue, + unicode + ]{hyperref} +\usepackage{pspicture} +\fi +\usepackage[utf8]{inputenc} +\usepackage{mathptmx} +\usepackage[scaled=.90]{helvet} +\usepackage{courier} +\usepackage{sectsty} +\usepackage{amssymb} +\usepackage[titles]{tocloft} +\usepackage{doxygen} +\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left } +\makeindex +\setcounter{tocdepth}{3} +\renewcommand{\footrulewidth}{0.4pt} +\renewcommand{\familydefault}{\sfdefault} +\hfuzz=15pt +\setlength{\emergencystretch}{15pt} +\hbadness=750 +\tolerance=750 +\begin{document} +\hypersetup{pageanchor=false,citecolor=blue} +\begin{titlepage} +\vspace*{7cm} +\begin{center} +{\Huge libopencm3: API Reference\\ STM STM32F4 ARM Cortex M3 Series}\\ +\vspace*{1cm} +{\large Generated by Doxygen 1.8.2}\\ +\vspace*{0.5cm} +{\small Thu Sep 13 2012 23:26:45}\\ +\end{center} +\end{titlepage} +\pagenumbering{arabic} +\hypersetup{pageanchor=true,citecolor=blue} diff --git a/include/libopencm3/cm3/doc-cm3.h b/include/libopencm3/cm3/doc-cm3.h new file mode 100644 index 00000000..0f76370f --- /dev/null +++ b/include/libopencm3/cm3/doc-cm3.h @@ -0,0 +1,22 @@ +/** @mainpage libopencm3 Core CM3 + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for Cortex M3 core features. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup CM3_defines CM3 Defines + +@brief Defined Constants and Types for Cortex M3 core features + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/cm3/docmain.h b/include/libopencm3/cm3/docmain.h deleted file mode 100644 index 9407ceb6..00000000 --- a/include/libopencm3/cm3/docmain.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @mainpage libopencm3 Developer Documentation - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net - -@date 18 August 2012 - - * The libopencm3 project (previously known as libopenstm32) aims to create - * a free/libre/open-source (GPL v3, or later) firmware library for various - * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03, - * Atmel SAM3U, NXP LPC1000 and others. - * - * @par "" - * - * See the libopencm3 wiki for - * more information. - -LGPL License Terms @ref lgpl_license - -*/ - -/** @page lgpl_license libopencm3 License - -libopencm3 is free software: you can redistribute it and/or modify -it under the terms of the GNU Lesser General Public License as published by the Free -Software Foundation, either version 3 of the License, or (at your option) any -later version. - -libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. - -You should have received a copy of the GNU Lesser General Public License along with this -program. If not, see . - -*/ - -/** @defgroup LM3S LM3S -Libraries for Texas instruments LM3S series. -*/ - -/** @defgroup LPC13xx LPC13xx -Libraries for NXP Semiconductor LPC13xx series. -*/ - -/** @defgroup LPC17xx LPC17xx -Libraries for NXP Semiconductor LPC17xx series. -*/ - -/** @defgroup STM32F STM32F -Libraries for ST Microelectronics STM32F series. -*/ - -/** @defgroup STM32F1xx STM32F1xx -@ingroup STM32F -Libraries for ST Microelectronics STM32F1xx series. -*/ - -/** @defgroup STM32F2xx STM32F2xx -@ingroup STM32F -Libraries for ST Microelectronics STM32F2xx series. -*/ - -/** @defgroup STM32F4xx STM32F4xx -@ingroup STM32F -Libraries for ST Microelectronics STM32F4xx series. -*/ - diff --git a/include/libopencm3/docmain.dox b/include/libopencm3/docmain.dox new file mode 100644 index 00000000..f85aeb88 --- /dev/null +++ b/include/libopencm3/docmain.dox @@ -0,0 +1,21 @@ +/** @mainpage libopencm3 Developer Documentation + +@version 1.0.0 + +@date 7 September 2012 + + * The libopencm3 project (previously known as libopenstm32) aims to create + * a free/libre/open-source (GPL v3, or later) firmware library for various + * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03, + * Atmel SAM3U, NXP LPC1000 and others. + * + * @par "" + * + * See the libopencm3 wiki for + * more information. + +LGPL License Terms @ref lgpl_license +*/ + + + diff --git a/include/libopencm3/license.dox b/include/libopencm3/license.dox new file mode 100644 index 00000000..3aa9331a --- /dev/null +++ b/include/libopencm3/license.dox @@ -0,0 +1,16 @@ +/** @page lgpl_license libopencm3 License + +libopencm3 is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by the Free +Software Foundation, either version 3 of the License, or (at your option) any +later version. + +libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public License along with this +program. If not, see . + +*/ + diff --git a/include/libopencm3/lm3s/doc-lm3s.h b/include/libopencm3/lm3s/doc-lm3s.h new file mode 100644 index 00000000..2503a7b0 --- /dev/null +++ b/include/libopencm3/lm3s/doc-lm3s.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LM3S + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for TI Stellaris LM3S Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3S LM3S +Libraries for TI Stellaris LM3S series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3S_defines LM3S Defines + +@brief Defined Constants and Types for the LM3S series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/lpc13xx/doc-lpc13xx.h b/include/libopencm3/lpc13xx/doc-lpc13xx.h new file mode 100644 index 00000000..5ed7cae9 --- /dev/null +++ b/include/libopencm3/lpc13xx/doc-lpc13xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC13xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC13xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx LPC13xx +Libraries for NXP Semiconductors LPC13xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx_defines LPC13xx Defines + +@brief Defined Constants and Types for the LPC13xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/lpc17xx/doc-lpc17xx.h b/include/libopencm3/lpc17xx/doc-lpc17xx.h new file mode 100644 index 00000000..5ed7cae9 --- /dev/null +++ b/include/libopencm3/lpc17xx/doc-lpc17xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC13xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC13xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx LPC13xx +Libraries for NXP Semiconductors LPC13xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx_defines LPC13xx Defines + +@brief Defined Constants and Types for the LPC13xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/lpc43xx/doc-lpc43xx.h b/include/libopencm3/lpc43xx/doc-lpc43xx.h new file mode 100644 index 00000000..3c21aaeb --- /dev/null +++ b/include/libopencm3/lpc43xx/doc-lpc43xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC43xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC43xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx LPC43xx +Libraries for NXP Semiconductors LPC43xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx_defines LPC43xx Defines + +@brief Defined Constants and Types for the LPC43xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/stm32/doc-stm32f.h b/include/libopencm3/stm32/doc-stm32f.h index b0532de3..7b0a1a31 100644 --- a/include/libopencm3/stm32/doc-stm32f.h +++ b/include/libopencm3/stm32/doc-stm32f.h @@ -1,24 +1,29 @@ -/** @defgroup STM32F_defines STM32F Top Level Defines - -@brief Defined Constants and Types for the STM32F series - -@ingroup STM32F - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net +/** @mainpage libopencm3 STM32 Common @version 1.0.0 -@date 18 August 2012 +@date 7 September 2012 + +API documentation for common files for ST Microelectronics STM32 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F_defines STM32F Common Defines + +@brief Defined Constants and Types for the STM32F series LGPL License Terms @ref lgpl_license */ -/** @defgroup STM32F_files STM32F Top Level Files +/** @defgroup STM32F_files STM32F Common Files @brief Common Files for ST Microelectronics STM32F series. -@ingroup STM32F +@version 1.0.0 +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license */ - diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h index 04293a66..4e1407e2 100644 --- a/include/libopencm3/stm32/f1/doc-stm32f1.h +++ b/include/libopencm3/stm32/f1/doc-stm32f1.h @@ -1,15 +1,32 @@ +/** @mainpage libopencm3 STM32F1 + +@version 1.0.0 + +@date 7 September 2012 + +API documentation for ST Microelectronics STM32F1 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F1xx STM32F1xx +Libraries for ST Microelectronics STM32F1xx series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + /** @defgroup STM32F1xx_defines STM32F1xx Defines @brief Defined Constants and Types for the STM32F1xx series -@ingroup STM32F1xx - -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net - @version 1.0.0 -@date 18 August 2012 +@date 7 September 2012 LGPL License Terms @ref lgpl_license - */ +*/ diff --git a/include/libopencm3/stm32/f2/doc-stm32f2.h b/include/libopencm3/stm32/f2/doc-stm32f2.h new file mode 100644 index 00000000..faa7f291 --- /dev/null +++ b/include/libopencm3/stm32/f2/doc-stm32f2.h @@ -0,0 +1,33 @@ +/** @mainpage libopencm3 STM32F2 + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for ST Microelectronics STM32F2 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + + +/** @defgroup STM32F2xx STM32F2xx +Libraries for ST Microelectronics STM32F2xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F2xx_defines STM32F2xx Defines + +@brief Defined Constants and Types for the STM32F2xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/stm32/f4/doc-stm32f4.h b/include/libopencm3/stm32/f4/doc-stm32f4.h new file mode 100644 index 00000000..39d70916 --- /dev/null +++ b/include/libopencm3/stm32/f4/doc-stm32f4.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F4 + +@version 1.0.0 + +@date 7 September 2012 + +API documentation for ST Microelectronics STM32F4 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx STM32F4xx +Libraries for ST Microelectronics STM32F4xx series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx_defines STM32F4xx Defines + +@brief Defined Constants and Types for the STM32F4xx series + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + From 7851515c5c749294e82ce20cb23c6d528fb804b5 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Tue, 11 Sep 2012 08:15:11 +0200 Subject: [PATCH 04/35] Fix merge error This line was removed in commit acc276a612d4, but it has been restored in the merge 02ea612142fb. --- include/libopencm3/stm32/f1/adc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index b1396a59..116aeaad 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -679,7 +679,6 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS -/* TODO */ void adc_enable_analog_watchdog_regular(u32 adc); void adc_disable_analog_watchdog_regular(u32 adc); void adc_enable_analog_watchdog_injected(u32 adc); From d6e0e6e976916f7a72abf92318b65ab96b291b78 Mon Sep 17 00:00:00 2001 From: Paul Sokolovsky Date: Tue, 25 Sep 2012 00:31:31 +0300 Subject: [PATCH 05/35] Explicitly link example binaries statically. This allow good share of binaries be linkable (and actually run) with a typical distro-packaged ARM toolchain (Cortex-A and Linux targetted). --- examples/stm32/f1/Makefile.include | 2 +- examples/stm32/f2/Makefile.include | 2 +- examples/stm32/f4/Makefile.include | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/stm32/f1/Makefile.include b/examples/stm32/f1/Makefile.include index b315fac1..60f44e7e 100644 --- a/examples/stm32/f1/Makefile.include +++ b/examples/stm32/f1/Makefile.include @@ -37,7 +37,7 @@ ARCH_FLAGS = -mthumb -mcpu=cortex-m3 -msoft-float CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common $(ARCH_FLAGS) -MD -DSTM32F1 LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ +LDFLAGS += --static -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ -L$(TOOLCHAIN_DIR)/lib \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ $(ARCH_FLAGS) -mfix-cortex-m3-ldrd diff --git a/examples/stm32/f2/Makefile.include b/examples/stm32/f2/Makefile.include index 3e338af5..690f8c4a 100644 --- a/examples/stm32/f2/Makefile.include +++ b/examples/stm32/f2/Makefile.include @@ -37,7 +37,7 @@ endif CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F2 LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ +LDFLAGS += --static -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group \ -L$(TOOLCHAIN_DIR)/lib -L$(TOOLCHAIN_DIR)/lib/stm32/f2 \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ -mthumb -march=armv7 -mfix-cortex-m3-ldrd -msoft-float diff --git a/examples/stm32/f4/Makefile.include b/examples/stm32/f4/Makefile.include index b735aa6e..8fa93917 100644 --- a/examples/stm32/f4/Makefile.include +++ b/examples/stm32/f4/Makefile.include @@ -38,7 +38,7 @@ endif CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common -mcpu=cortex-m4 -mthumb -msoft-float -MD -DSTM32F4 LDSCRIPT ?= $(BINARY).ld -LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \ +LDFLAGS += --static -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \ -L$(TOOLCHAIN_DIR)/lib/stm32/f4 \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ -mthumb -mcpu=cortex-m4 -march=armv7 -mfix-cortex-m3-ldrd -msoft-float From c9ab75878f3f039399cec4cf62604f86c927dff7 Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:07 -0400 Subject: [PATCH 06/35] Add all SCB registers mentioned in ARM DDI 0403D manual. See table B3-4 and B3-5 for the definitions and B3-24 for the bit assignments of SBC_CPACR. --- include/libopencm3/stm32/f4/scb.h | 69 +++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/include/libopencm3/stm32/f4/scb.h b/include/libopencm3/stm32/f4/scb.h index 181aa7a0..7187ca97 100644 --- a/include/libopencm3/stm32/f4/scb.h +++ b/include/libopencm3/stm32/f4/scb.h @@ -72,6 +72,63 @@ /* AFSR: Auxiliary Fault Status Register */ #define SCB_AFSR MMIO32(SCB_BASE + 0x3C) +/* ID_PFR0: Processor Feature Register 0 */ +#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) + +/* ID_PFR1: Processor Feature Register 1 */ +#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) + +/* ID_DFR0: Debug Features Register 0 */ +#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) + +/* ID_AFR0: Auxiliary Features Register 0 */ +#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) + +/* ID_MMFR0: Memory Model Feature Register 0 */ +#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) + +/* ID_MMFR1: Memory Model Feature Register 1 */ +#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) + +/* ID_MMFR2: Memory Model Feature Register 2 */ +#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) + +/* ID_MMFR3: Memory Model Feature Register 3 */ +#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) + +/* ID_ISAR0: Instruction Set Attributes Register 0 */ +#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) + +/* ID_ISAR1: Instruction Set Attributes Register 1 */ +#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) + +/* ID_ISAR2: Instruction Set Attributes Register 2 */ +#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) + +/* ID_ISAR3: Instruction Set Attributes Register 3 */ +#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) + +/* ID_ISAR4: Instruction Set Attributes Register 4 */ +#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) + +/* CPACR: Coprocessor Access Control Register */ +#define SCB_CPACR MMIO32(SCB_BASE + 0x88) + +/* FPCCR: Floating-Point Context Control Register */ +#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) + +/* FPCAR: Floating-Point Context Address Register */ +#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) + +/* FPDSCR: Floating-Point Default Status Control Register */ +#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) + +/* MVFR0: Media and Floating-Point Feature Register 0 */ +#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) + +/* MVFR1: Media and Floating-Point Feature Register 1 */ +#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) + /* --- SCB values ---------------------------------------------------------- */ /* --- SCB_CPUID values ---------------------------------------------------- */ @@ -292,6 +349,18 @@ /* BFAR [31:0]: Bus fault address */ +/* --- SCB_CPACR values ---------------------------------------------------- */ + +/* CPACR CPn: Access privileges values */ +#define SCB_CPACR_NONE 0 /* Access denied */ +#define SCB_CPACR_PRIV 1 /* Privileged access only */ +#define SCB_CPACR_FULL 3 /* Full access */ + +/* CPACR [20:21]: Access privileges for coprocessor 10 */ +#define SCB_CPACR_CP10 (1 << 20) +/* CPACR [22:23]: Access privileges for coprocessor 11 */ +#define SCB_CPACR_CP11 (1 << 22) + /* --- SCB functions ------------------------------------------------------- */ BEGIN_DECLS From 584052c28cdfe5c383f13471deb891ba9438843a Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:09 -0400 Subject: [PATCH 07/35] Compile stm32-f4 library with floating point support. This enables hard-float in the compilation of library and examples for the stm32f40* chips. --- examples/stm32/f4/Makefile.include | 5 +++-- lib/stm32/f4/Makefile | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/examples/stm32/f4/Makefile.include b/examples/stm32/f4/Makefile.include index b735aa6e..9dfe9d0e 100644 --- a/examples/stm32/f4/Makefile.include +++ b/examples/stm32/f4/Makefile.include @@ -36,12 +36,13 @@ endif TOOLCHAIN_DIR := ../../../../.. endif CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ - -fno-common -mcpu=cortex-m4 -mthumb -msoft-float -MD -DSTM32F4 + -fno-common -mcpu=cortex-m4 -mthumb \ + -mfloat-abi=hard -mfpu=fpv4-sp-d16 -MD -DSTM32F4 LDSCRIPT ?= $(BINARY).ld LDFLAGS += -lc -lnosys -L$(TOOLCHAIN_DIR)/lib \ -L$(TOOLCHAIN_DIR)/lib/stm32/f4 \ -T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections \ - -mthumb -mcpu=cortex-m4 -march=armv7 -mfix-cortex-m3-ldrd -msoft-float + -mthumb -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 OBJS += $(BINARY).o OOCD ?= openocd diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 5760d29b..881ef5de 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -24,7 +24,8 @@ PREFIX ?= arm-none-eabi CC = $(PREFIX)-gcc AR = $(PREFIX)-ar CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ - -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ + -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSTM32F4 # ARFLAGS = rcsv ARFLAGS = rcs From e4819d3cd284e76339887a45598269dbe1479da7 Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:08 -0400 Subject: [PATCH 08/35] Enable floating-point coprocessor on reset. Always enable the floating-point coprocessor with full access on reset, allowing usage of hard-fp toolchains. --- lib/stm32/f4/vector.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 3429bfb0..01b5e646 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -18,6 +18,8 @@ * along with this library. If not, see . */ +#include + #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ @@ -224,6 +226,9 @@ void reset_handler(void) __asm__("MSR msp, %0" : : "r"(&_stack)); + /* Enable access to Floating-Point coprocessor. */ + SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) *dest = *src; From aac5909ff133a71dc01037712f86e89f4e7877d7 Mon Sep 17 00:00:00 2001 From: Daniel Serpell Date: Wed, 22 Aug 2012 00:05:10 -0400 Subject: [PATCH 09/35] Add a floating-point example to the stm32f4. This example calculates a mandelbrot fractal using floating point in C. --- .../f4/stm32f4-discovery/mandelbrot/Makefile | 25 ++++ .../f4/stm32f4-discovery/mandelbrot/README | 12 ++ .../f4/stm32f4-discovery/mandelbrot/mandel.c | 127 ++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 examples/stm32/f4/stm32f4-discovery/mandelbrot/Makefile create mode 100644 examples/stm32/f4/stm32f4-discovery/mandelbrot/README create mode 100644 examples/stm32/f4/stm32f4-discovery/mandelbrot/mandel.c diff --git a/examples/stm32/f4/stm32f4-discovery/mandelbrot/Makefile b/examples/stm32/f4/stm32f4-discovery/mandelbrot/Makefile new file mode 100644 index 00000000..3879eca4 --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/mandelbrot/Makefile @@ -0,0 +1,25 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = mandel + +LDSCRIPT = ../stm32f4-discovery.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f4/stm32f4-discovery/mandelbrot/README b/examples/stm32/f4/stm32f4-discovery/mandelbrot/README new file mode 100644 index 00000000..fe4fb13d --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/mandelbrot/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This example program demonstrates the floating point coprocessor usage on +the ST STM32F4DISCOVERY eval board. + +A mandelbrot fractal is calculated and sent as "ascii-art" image through +the USART2. + +The terminal settings for the receiving device/PC are 38400 8n1. + diff --git a/examples/stm32/f4/stm32f4-discovery/mandelbrot/mandel.c b/examples/stm32/f4/stm32f4-discovery/mandelbrot/mandel.c new file mode 100644 index 00000000..5cbdafd3 --- /dev/null +++ b/examples/stm32/f4/stm32f4-discovery/mandelbrot/mandel.c @@ -0,0 +1,127 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2012 Daniel Serpell + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include + +void clock_setup(void) +{ + /* Enable high-speed clock at 120MHz */ + rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]); + + /* Enable GPIOD clock for LED & USARTs. */ + rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN); + rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); + + /* Enable clocks for USART2. */ + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); +} + +void usart_setup(void) +{ + /* Setup USART2 parameters. */ + usart_set_baudrate(USART2, 38400); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) +{ + /* Setup GPIO pin GPIO12 on GPIO port D for LED. */ + gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO12); + + /* Setup GPIO pins for USART2 transmit. */ + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2); + + /* Setup USART2 TX pin as alternate function. */ + gpio_set_af(GPIOA, GPIO_AF7, GPIO2); +} + +/* Maximum number of iterations for the escape-time calculation */ +#define maxIter 32 +/* This array converts the iteration count to a character representation. */ +static char color[maxIter+1] = " .:++xxXXX%%%%%%################"; + +/* Main mandelbrot calculation */ +static int iterate(float px, float py) +{ + int it=0; + float x=0,y=0; + while(it 4 ) + return it; + // Zn+1 = Zn^2 + P + y = 2*x*y + py; + x = nx - ny + px; + it++; + } + return 0; +} + +static void mandel(float cX, float cY, float scale) +{ + int x,y; + for(x=-60;x<60;x++) + { + for(y=-50;y<50;y++) + { + int i = iterate(cX+x*scale, cY+y*scale); + usart_send_blocking(USART2, color[i]); + } + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + } +} + +int main(void) +{ + float scale = 0.25f, centerX = -0.5f, centerY = 0.0f; + + clock_setup(); + gpio_setup(); + usart_setup(); + + while (1) { + /* Blink the LED (PD12) on the board with each fractal drawn. */ + gpio_toggle(GPIOD, GPIO12); /* LED on/off */ + mandel(centerX,centerY,scale); /* draw mandelbrot */ + + /* Change scale and center */ + centerX += 0.175f * scale; + centerY += 0.522f * scale; + scale *= 0.875f; + + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + } + + return 0; +} From fc4047e4b4b38c6c778f2d5f71c7412ecbab3152 Mon Sep 17 00:00:00 2001 From: Tomaz Solc Date: Mon, 24 Sep 2012 12:54:53 +0200 Subject: [PATCH 10/35] Add assert macros to aid in debugging. Adds libopencm3/cm3/assert.h header that provides assertion check macros similar to those provided by the standard C library. Thanks to Nicolas Schodet for help. --- include/libopencm3/cm3/assert.h | 136 ++++++++++++++++++++++++++++++++ lib/cm3/assert.c | 34 ++++++++ lib/lm3s/Makefile | 4 +- lib/lpc13xx/Makefile | 4 +- lib/lpc17xx/Makefile | 4 +- lib/lpc43xx/Makefile | 5 +- lib/stm32/f1/Makefile | 4 +- lib/stm32/f1/rcc.c | 4 +- lib/stm32/f2/Makefile | 4 +- lib/stm32/f2/rcc.c | 4 +- lib/stm32/f4/Makefile | 3 +- lib/stm32/f4/rcc.c | 4 +- 12 files changed, 191 insertions(+), 19 deletions(-) create mode 100644 include/libopencm3/cm3/assert.h create mode 100644 lib/cm3/assert.c diff --git a/include/libopencm3/cm3/assert.h b/include/libopencm3/cm3/assert.h new file mode 100644 index 00000000..0ccb0f72 --- /dev/null +++ b/include/libopencm3/cm3/assert.h @@ -0,0 +1,136 @@ +/** @defgroup debugging Debugging + +@brief Macros and functions to aid in debugging + +@version 1.0.0 + +@date 25 September 2012 + +Two preprocessor defines control the behavior of assertion check macros in +this module. They allow the choice between generated code size and ease of +debugging. + +If NDEBUG is defined, all assertion checks are disabled and macros do not +generate any code. + +If CM3_ASSERT_VERBOSE is defined, information regarding the position of +assertion checks will be stored in the binary, allowing for more +informative error messages, but also significantly increased code size. As +default assertion checks do not use this information it is only useful if +the application linked with libopencm3 defines its own +cm3_assert_failed_verbose() implementation. + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Tomaz Solc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_CM3_ASSERT_H +#define LIBOPENCM3_CM3_ASSERT_H + +#include + +#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1)) + +#ifdef NDEBUG +# define cm3_assert(expr) do { (void)0; } while(0) +# define cm3_assert_not_reached() while(1) +#else +# ifdef CM3_ASSERT_VERBOSE +# define cm3_assert(expr) do { \ + if(CM3_LIKELY(expr)) { (void)0; } else { \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, #expr); \ + } \ + } while(0) +# define cm3_assert_not_reached() do { \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, 0); \ + } while(0) +# else +/** @brief Check if assertion is true. + * + * If NDEBUG macro is defined, this macro generates no code. Otherwise + * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion + * is false. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to check if function + * arguments are within expected ranges and stop execution in case an + * unexpected state is reached. + * + * @param expr expression to check */ +# define cm3_assert(expr) do { \ + if(CM3_LIKELY(expr)) { (void)0; } else { \ + cm3_assert_failed(); \ + } \ + } while(0) +/** @brief Check if unreachable code is reached. + * + * If NDEBUG macro is defined, this macro generates code for an infinite loop. + * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if + * the macro is ever reached. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to stop execution if an + * unreachable portion of code is reached. */ +# define cm3_assert_not_reached() do { \ + cm3_assert_failed(); \ + } while(0) +# endif +#endif + +BEGIN_DECLS + +/** @brief Called on a failed assertion. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. */ +void cm3_assert_failed(void) __attribute__ ((__noreturn__)); + +/** @brief Called on a failed assertion with verbose messages enabled. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. + * + * @param file File name where the failed assertion occurred + * @param line Line number where the failed assertion occurred + * @param func Name of the function where the failed assertion occurred + * @param assert_expr Expression that evaluated to false (can be NULL) */ +void cm3_assert_failed_verbose(const char *file, int line, const char *func, + const char *assert_expr) __attribute__ ((__noreturn__)); + +END_DECLS + +#endif + +/**@}*/ diff --git a/lib/cm3/assert.c b/lib/cm3/assert.c new file mode 100644 index 00000000..d76c578c --- /dev/null +++ b/lib/cm3/assert.c @@ -0,0 +1,34 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Tomaz Solc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void __attribute__((weak)) cm3_assert_failed(void) +{ + while(1); +} + +void __attribute__((weak)) cm3_assert_failed_verbose( + const char *file __attribute__((unused)), + int line __attribute__((unused)), + const char *func __attribute__((unused)), + const char *assert_expr __attribute__((unused))) +{ + cm3_assert_failed(); +} diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index bdad3a47..e471a001 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 158a5bf4..e1e69f7b 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o +OBJS = gpio.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index f688716f..d1da64af 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -28,8 +28,8 @@ CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \ -ffunction-sections -fdata-sections -MD # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o +OBJS = gpio.o vector.o assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/lpc43xx/Makefile b/lib/lpc43xx/Makefile index 67e74d7e..6e08ea0e 100644 --- a/lib/lpc43xx/Makefile +++ b/lib/lpc43xx/Makefile @@ -31,8 +31,9 @@ CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o +OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o \ + assert.o -# VPATH += ../usb +VPATH += ../cm3 include ../Makefile.include diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 3b4252ba..4fdbf434 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,9 +31,9 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o + timer.o usb_f107.o desig.o crc.o assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 5fd9c62f..ab3350b2 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -48,6 +48,7 @@ LGPL License Terms @ref lgpl_license /**@{*/ +#include #include #include @@ -166,8 +167,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } /*-----------------------------------------------------------------------------*/ diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index bd6f2758..c127d61f 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -29,8 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ # ARFLAGS = rcsv ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ - i2c.o systick.o exti.o scb.o timer.o \ + i2c.o systick.o exti.o scb.o timer.o assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index 9461a24c..cc2c9bb7 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -19,6 +19,7 @@ * along with this library. If not, see . */ +#include #include #include @@ -125,8 +126,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } void rcc_css_int_clear(void) diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 5760d29b..85870a7a 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -31,7 +31,8 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \ i2c.o systick.o exti.o scb.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_f107.o \ + assert.o -VPATH += ../../usb:../ +VPATH += ../../usb:../:../../cm3 include ../../Makefile.include diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 6294ff70..f506d4b1 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -19,6 +19,7 @@ * along with this library. If not, see . */ +#include #include #include #include @@ -139,8 +140,7 @@ int rcc_osc_ready_int_flag(osc_t osc) break; } - /* Shouldn't be reached. */ - return -1; + cm3_assert_not_reached(); } void rcc_css_int_clear(void) From a69d83d312396ee604426dce5341a54316c7c9b5 Mon Sep 17 00:00:00 2001 From: chrysn Date: Wed, 3 Oct 2012 18:15:20 +0200 Subject: [PATCH 11/35] unified vector table initialization the cortex generic interrupts get moved to lib/cm3/vector.c, the platorms' individual irq names, initialization and handler prototypes go to platoform specific irq.h files. as the vector.c file heavily depends on platoform specific headers, it can't be built once-and-for-all in lib/cm3/, so there are inclusion stubs in the various architecture dirs; this might be better solved with Makefile / include path handling. one particular file is lib/lpc43xx/vector.c; that platform's initialization code contains an additional section to copy everything from flash to ram (which probably performs better there). that code still resides in the inclusion stub, and gets mashed in using defines. would need a cleaner implementation together with the Makefile solution. this commit contains some files of the upcoming efm32 branch, from which it was cherry-picked. the .bin files produced from before and after this commit only differ in lpc43xx, where the startup sequence was subtly modified. --- include/libopencm3/cm3/vector.h | 65 ++++ include/libopencm3/efm32/tinygecko/irq.h | 130 ++++++++ include/libopencm3/lm3s/irq.h | 33 +++ include/libopencm3/lpc17xx/irq.h | 33 +++ include/libopencm3/lpc43xx/irq.h | 234 +++++++++++++++ include/libopencm3/stm32/f1/irq.h | 306 +++++++++++++++++++ include/libopencm3/stm32/f2/irq.h | 359 +++++++++++++++++++++++ include/libopencm3/stm32/f4/irq.h | 359 +++++++++++++++++++++++ lib/cm3/vector.c | 95 ++++++ lib/efm32/tinygecko/vector.c | 2 + lib/lm3s/vector.c | 98 +------ lib/lpc17xx/vector.c | 97 +----- lib/lpc43xx/vector.c | 224 +------------- lib/stm32/f1/vector.c | 298 +------------------ lib/stm32/f2/vector.c | 338 +-------------------- lib/stm32/f4/vector.c | 338 +-------------------- 16 files changed, 1633 insertions(+), 1376 deletions(-) create mode 100644 include/libopencm3/cm3/vector.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lpc17xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 lib/cm3/vector.c create mode 100644 lib/efm32/tinygecko/vector.c diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h new file mode 100644 index 00000000..198992b0 --- /dev/null +++ b/include/libopencm3/cm3/vector.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include + +// #include "irq.h" /* we'll nede some definitions */ + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; + vector_table_entry_t bus_fault; + vector_table_entry_t usage_fault; + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[IRQ_COUNT]; +} vector_table_t; + +#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h new file mode 100644 index 00000000..f5263aee --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.h @@ -0,0 +1,130 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions of interrupt names on EFM32 Tiny Gecko systems + * + * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. + */ + +#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H + +#define IRQ_DMA 0 +#define IRQ_GPIO_EVEN 1 +#define IRQ_TIMER0 2 +#define IRQ_USART0_RX 3 +#define IRQ_USART0_TX 4 +#define IRQ_ACMP01 5 +#define IRQ_ADC0 6 +#define IRQ_DAC0 7 +#define IRQ_I2C0 8 +#define IRQ_GPIO_ODD 9 +#define IRQ_TIMER1 10 +#define IRQ_USART1_RX 11 +#define IRQ_USART1_TX 12 +#define IRQ_LESENSE 13 +#define IRQ_LEUART0 14 +#define IRQ_LETIMER0 15 +#define IRQ_PCNT0 16 +#define IRQ_RTC 17 +#define IRQ_CMU 18 +#define IRQ_VCMP 19 +#define IRQ_LCD 20 +#define IRQ_MSC 21 +#define IRQ_AES 22 +#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ + +#define WEAK __attribute__ ((weak)) + +void WEAK dma_isr(void); +void WEAK gpio_even_isr(void); +void WEAK timer0_isr(void); +void WEAK usart0_rx_isr(void); +void WEAK usart0_tx_isr(void); +void WEAK acmp01_isr(void); +void WEAK adc0_isr(void); +void WEAK dac0_isr(void); +void WEAK i2c0_isr(void); +void WEAK gpio_odd_isr(void); +void WEAK timer1_isr(void); +void WEAK usart1_rx_isr(void); +void WEAK usart1_tx_isr(void); +void WEAK lesense_isr(void); +void WEAK leuart0_isr(void); +void WEAK letimer0_isr(void); +void WEAK pcnt0_isr(void); +void WEAK rtc_isr(void); +void WEAK cmu_isr(void); +void WEAK vcmp_isr(void); +void WEAK lcd_isr(void); +void WEAK msc_isr(void); +void WEAK aes_isr(void); + +#pragma weak dma_isr = blocking_handler +#pragma weak gpio_even_isr = blocking_handler +#pragma weak timer0_isr = blocking_handler +#pragma weak usart0_rx_isr = blocking_handler +#pragma weak usart0_tx_isr = blocking_handler +#pragma weak acmp01_isr = blocking_handler +#pragma weak adc0_isr = blocking_handler +#pragma weak dac0_isr = blocking_handler +#pragma weak i2c0_isr = blocking_handler +#pragma weak gpio_odd_isr = blocking_handler +#pragma weak timer1_isr = blocking_handler +#pragma weak usart1_rx_isr = blocking_handler +#pragma weak usart1_tx_isr = blocking_handler +#pragma weak lesense_isr = blocking_handler +#pragma weak leuart0_isr = blocking_handler +#pragma weak letimer0_isr = blocking_handler +#pragma weak pcnt0_isr = blocking_handler +#pragma weak rtc_isr = blocking_handler +#pragma weak cmu_isr = blocking_handler +#pragma weak vcmp_isr = blocking_handler +#pragma weak lcd_isr = blocking_handler +#pragma weak msc_isr = blocking_handler +#pragma weak aes_isr = blocking_handler + +#define IRQ_HANDLERS \ + [IRQ_DMA] = dma_isr, \ + [IRQ_GPIO_EVEN] = gpio_even_isr, \ + [IRQ_TIMER0] = timer0_isr, \ + [IRQ_USART0_RX] = usart0_rx_isr, \ + [IRQ_USART0_TX] = usart0_tx_isr, \ + [IRQ_ACMP01] = acmp01_isr, \ + [IRQ_ADC0] = adc0_isr, \ + [IRQ_DAC0] = dac0_isr, \ + [IRQ_I2C0] = i2c0_isr, \ + [IRQ_GPIO_ODD] = gpio_odd_isr, \ + [IRQ_TIMER1] = timer1_isr, \ + [IRQ_USART1_RX] = usart1_rx_isr, \ + [IRQ_USART1_TX] = usart1_tx_isr, \ + [IRQ_LESENSE] = lesense_isr, \ + [IRQ_LEUART0] = leuart0_isr, \ + [IRQ_LETIMER0] = letimer0_isr, \ + [IRQ_PCNT0] = pcnt0_isr, \ + [IRQ_RTC] = rtc_isr, \ + [IRQ_CMU] = cmu_isr, \ + [IRQ_VCMP] = vcmp_isr, \ + [IRQ_LCD] = lcd_isr, \ + [IRQ_MSC] = msc_isr, \ + [IRQ_AES] = aes_isr, + +#endif diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h new file mode 100644 index 00000000..948c563c --- /dev/null +++ b/include/libopencm3/lm3s/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LM3S_IRQ_H +#define LIBOPENCM3_LM3S_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h new file mode 100644 index 00000000..9c31267b --- /dev/null +++ b/include/libopencm3/lpc17xx/irq.h @@ -0,0 +1,33 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC17xx_IRQ_H +#define LIBOPENCM3_LPC17xx_IRQ_H + +/* TODO: Interrupt definitions */ +#define IRQ_COUNT 0 + +/* TODO: Interrupt handler prototypes */ + +/* TODO: Interrupt handler weak aliases */ + +#define IRQ_HANDLERS + +#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h new file mode 100644 index 00000000..a83a8d77 --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.h @@ -0,0 +1,234 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LPC43XX_IRQ_H +#define LIBOPENCM3_LPC43XX_IRQ_H + +#define IRQ_DAC 0 +#define IRQ_M0CORE 1 +#define IRQ_DMA 2 +/* reserved: 3 */ +/* reserved: 4 */ +#define IRQ_ETHERNET 5 +#define IRQ_SDIO 6 +#define IRQ_LCD 7 +#define IRQ_USB0 8 +#define IRQ_USB1 9 +#define IRQ_SCT 10 +#define IRQ_RITIMER 11 +#define IRQ_TIMER0 12 +#define IRQ_TIMER1 13 +#define IRQ_TIMER2 14 +#define IRQ_TIMER3 15 +#define IRQ_MCPWM 16 +#define IRQ_ADC0 17 +#define IRQ_I2C0 18 +#define IRQ_I2C1 19 +#define IRQ_SPI 20 +#define IRQ_ADC1 21 +#define IRQ_SSP0 22 +#define IRQ_SSP1 23 +#define IRQ_USART0 24 +#define IRQ_UART1 25 +#define IRQ_USART2 26 +#define IRQ_USART3 27 +#define IRQ_I2S0 28 +#define IRQ_I2S1 29 +#define IRQ_SPIFI 30 +#define IRQ_SGPIO 31 +#define IRQ_PIN_INT0 32 +#define IRQ_PIN_INT1 33 +#define IRQ_PIN_INT2 34 +#define IRQ_PIN_INT3 35 +#define IRQ_PIN_INT4 36 +#define IRQ_PIN_INT5 37 +#define IRQ_PIN_INT6 38 +#define IRQ_PIN_INT7 39 +#define IRQ_GINT0 40 +#define IRQ_GINT1 41 +#define IRQ_EVENTROUTER 42 +#define IRQ_C_CAN1 43 +/* reserved: 44 */ +/* reserved: 45 */ +#define IRQ_ATIMER 46 +#define IRQ_RTC 47 +/* reserved: 48 */ +#define IRQ_WWDT 49 +/* reserved: 50 */ +#define IRQ_C_CAN0 51 +#define IRQ_QEI 52 + +#define IRQ_COUNT 53 + +#define WEAK __attribute__ ((weak)) + +void WEAK dac_irqhandler(void); +void WEAK m0core_irqhandler(void); +void WEAK dma_irqhandler(void); +void WEAK ethernet_irqhandler(void); +void WEAK sdio_irqhandler(void); +void WEAK lcd_irqhandler(void); +void WEAK usb0_irqhandler(void); +void WEAK usb1_irqhandler(void); +void WEAK sct_irqhandler(void); +void WEAK ritimer_irqhandler(void); +void WEAK timer0_irqhandler(void); +void WEAK timer1_irqhandler(void); +void WEAK timer2_irqhandler(void); +void WEAK timer3_irqhandler(void); +void WEAK mcpwm_irqhandler(void); +void WEAK adc0_irqhandler(void); +void WEAK i2c0_irqhandler(void); +void WEAK i2c1_irqhandler(void); +void WEAK spi_irqhandler(void); +void WEAK adc1_irqhandler(void); +void WEAK ssp0_irqhandler(void); +void WEAK ssp1_irqhandler(void); +void WEAK usart0_irqhandler(void); +void WEAK uart1_irqhandler(void); +void WEAK usart2_irqhandler(void); +void WEAK usart3_irqhandler(void); +void WEAK i2s0_irqhandler(void); +void WEAK i2s1_irqhandler(void); +void WEAK spifi_irqhandler(void); +void WEAK sgpio_irqhandler(void); +void WEAK pin_int0_irqhandler(void); +void WEAK pin_int1_irqhandler(void); +void WEAK pin_int2_irqhandler(void); +void WEAK pin_int3_irqhandler(void); +void WEAK pin_int4_irqhandler(void); +void WEAK pin_int5_irqhandler(void); +void WEAK pin_int6_irqhandler(void); +void WEAK pin_int7_irqhandler(void); +void WEAK gint0_irqhandler(void); +void WEAK gint1_irqhandler(void); +void WEAK eventrouter_irqhandler(void); +void WEAK c_can1_irqhandler(void); +void WEAK atimer_irqhandler(void); +void WEAK rtc_irqhandler(void); +void WEAK wwdt_irqhandler(void); +void WEAK c_can0_irqhandler(void); +void WEAK qei_irqhandler(void); + +#pragma weak dac_irqhandler = null_handler +#pragma weak m0core_irqhandler = null_handler +#pragma weak dma_irqhandler = null_handler +#pragma weak ethernet_irqhandler = null_handler +#pragma weak sdio_irqhandler = null_handler +#pragma weak lcd_irqhandler = null_handler +#pragma weak usb0_irqhandler = null_handler +#pragma weak usb1_irqhandler = null_handler +#pragma weak sct_irqhandler = null_handler +#pragma weak ritimer_irqhandler = null_handler +#pragma weak timer0_irqhandler = null_handler +#pragma weak timer1_irqhandler = null_handler +#pragma weak timer2_irqhandler = null_handler +#pragma weak timer3_irqhandler = null_handler +#pragma weak mcpwm_irqhandler = null_handler +#pragma weak adc0_irqhandler = null_handler +#pragma weak i2c0_irqhandler = null_handler +#pragma weak i2c1_irqhandler = null_handler +#pragma weak spi_irqhandler = null_handler +#pragma weak adc1_irqhandler = null_handler +#pragma weak ssp0_irqhandler = null_handler +#pragma weak ssp1_irqhandler = null_handler +#pragma weak usart0_irqhandler = null_handler +#pragma weak uart1_irqhandler = null_handler +#pragma weak usart2_irqhandler = null_handler +#pragma weak usart3_irqhandler = null_handler +#pragma weak i2s0_irqhandler = null_handler +#pragma weak i2s1_irqhandler = null_handler +#pragma weak spifi_irqhandler = null_handler +#pragma weak sgpio_irqhandler = null_handler +#pragma weak pin_int0_irqhandler = null_handler +#pragma weak pin_int1_irqhandler = null_handler +#pragma weak pin_int2_irqhandler = null_handler +#pragma weak pin_int3_irqhandler = null_handler +#pragma weak pin_int4_irqhandler = null_handler +#pragma weak pin_int5_irqhandler = null_handler +#pragma weak pin_int6_irqhandler = null_handler +#pragma weak pin_int7_irqhandler = null_handler +#pragma weak gint0_irqhandler = null_handler +#pragma weak gint1_irqhandler = null_handler +#pragma weak eventrouter_irqhandler = null_handler +#pragma weak c_can1_irqhandler = null_handler +#pragma weak atimer_irqhandler = null_handler +#pragma weak rtc_irqhandler = null_handler +#pragma weak wwdt_irqhandler = null_handler +#pragma weak c_can0_irqhandler = null_handler +#pragma weak qei_irqhandler = null_handler + +#define IRQ_HANDLERS \ + dac_irqhandler, \ + m0core_irqhandler, \ + dma_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + ethernet_irqhandler, \ + sdio_irqhandler, \ + lcd_irqhandler, \ + usb0_irqhandler, \ + usb1_irqhandler, \ + sct_irqhandler, \ + ritimer_irqhandler, \ + timer0_irqhandler, \ + timer1_irqhandler, \ + timer2_irqhandler, \ + timer3_irqhandler, \ + mcpwm_irqhandler, \ + adc0_irqhandler, \ + i2c0_irqhandler, \ + i2c1_irqhandler, \ + spi_irqhandler, \ + adc1_irqhandler, \ + ssp0_irqhandler, \ + ssp1_irqhandler, \ + usart0_irqhandler, \ + uart1_irqhandler, \ + usart2_irqhandler, \ + usart3_irqhandler, \ + i2s0_irqhandler, \ + i2s1_irqhandler, \ + spifi_irqhandler, \ + sgpio_irqhandler, \ + pin_int0_irqhandler, \ + pin_int1_irqhandler, \ + pin_int2_irqhandler, \ + pin_int3_irqhandler, \ + pin_int4_irqhandler, \ + pin_int5_irqhandler, \ + pin_int6_irqhandler, \ + pin_int7_irqhandler, \ + gint0_irqhandler, \ + gint1_irqhandler, \ + eventrouter_irqhandler, \ + c_can1_irqhandler, \ + 0, /* reserved */ \ + 0, /* reserved */ \ + atimer_irqhandler, \ + rtc_irqhandler, \ + 0, /* reserved */ \ + wwdt_irqhandler, \ + 0, /* reserved */ \ + c_can0_irqhandler, \ + qei_irqhandler, + +#endif diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h new file mode 100644 index 00000000..cfa07f1a --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.h @@ -0,0 +1,306 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F1_IRQ_H +#define LIBOPENCM3_STM32_F1_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMPER 2 +#define IRQ_RTC 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_CHANNEL1 11 +#define IRQ_DMA1_CHANNEL2 12 +#define IRQ_DMA1_CHANNEL3 13 +#define IRQ_DMA1_CHANNEL4 14 +#define IRQ_DMA1_CHANNEL5 15 +#define IRQ_DMA1_CHANNEL6 16 +#define IRQ_DMA1_CHANNEL7 17 +#define IRQ_ADC1_2 18 +#define IRQ_USB_HP_CAN_TX 19 +#define IRQ_USB_LP_CAN_RX0 20 +#define IRQ_CAN_RX1 21 +#define IRQ_CAN_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK 24 +#define IRQ_TIM1_UP 25 +#define IRQ_TIM1_TRG_COM 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_WAKEUP 42 +#define IRQ_TIM8_BRK 43 +#define IRQ_TIM8_UP 44 +#define IRQ_TIM8_TRG_COM 45 +#define IRQ_TIM8_CC 46 +#define IRQ_ADC3 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_CHANNEL1 56 +#define IRQ_DMA2_CHANNEL2 57 +#define IRQ_DMA2_CHANNEL3 58 +#define IRQ_DMA2_CHANNEL4_5 59 +#define IRQ_DMA2_CHANNEL5 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 + +/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ +#define IRQ_COUNT 68 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamper_isr(void); +void WEAK rtc_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_channel1_isr(void); +void WEAK dma1_channel2_isr(void); +void WEAK dma1_channel3_isr(void); +void WEAK dma1_channel4_isr(void); +void WEAK dma1_channel5_isr(void); +void WEAK dma1_channel6_isr(void); +void WEAK dma1_channel7_isr(void); +void WEAK adc1_2_isr(void); +void WEAK usb_hp_can_tx_isr(void); +void WEAK usb_lp_can_rx0_isr(void); +void WEAK can_rx1_isr(void); +void WEAK can_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_isr(void); +void WEAK tim1_up_isr(void); +void WEAK tim1_trg_com_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_wakeup_isr(void); +void WEAK tim8_brk_isr(void); +void WEAK tim8_up_isr(void); +void WEAK tim8_trg_com_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK adc3_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_channel1_isr(void); +void WEAK dma2_channel2_isr(void); +void WEAK dma2_channel3_isr(void); +void WEAK dma2_channel4_5_isr(void); +void WEAK dma2_channel5_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamper_isr = null_handler +#pragma weak rtc_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_channel1_isr = null_handler +#pragma weak dma1_channel2_isr = null_handler +#pragma weak dma1_channel3_isr = null_handler +#pragma weak dma1_channel4_isr = null_handler +#pragma weak dma1_channel5_isr = null_handler +#pragma weak dma1_channel6_isr = null_handler +#pragma weak dma1_channel7_isr = null_handler +#pragma weak adc1_2_isr = null_handler +#pragma weak usb_hp_can_tx_isr = null_handler +#pragma weak usb_lp_can_rx0_isr = null_handler +#pragma weak can_rx1_isr = null_handler +#pragma weak can_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_isr = null_handler +#pragma weak tim1_up_isr = null_handler +#pragma weak tim1_trg_com_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_wakeup_isr = null_handler +#pragma weak tim8_brk_isr = null_handler +#pragma weak tim8_up_isr = null_handler +#pragma weak tim8_trg_com_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak adc3_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_channel1_isr = null_handler +#pragma weak dma2_channel2_isr = null_handler +#pragma weak dma2_channel3_isr = null_handler +#pragma weak dma2_channel4_5_isr = null_handler +#pragma weak dma2_channel5_isr +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamper_isr, \ + rtc_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_channel1_isr, \ + dma1_channel2_isr, \ + dma1_channel3_isr, \ + dma1_channel4_isr, \ + dma1_channel5_isr, \ + dma1_channel6_isr, \ + dma1_channel7_isr, \ + adc1_2_isr, \ + usb_hp_can_tx_isr, \ + usb_lp_can_rx0_isr, \ + can_rx1_isr, \ + can_sce_isr, \ + exti9_5_isr, \ + tim1_brk_isr, \ + tim1_up_isr, \ + tim1_trg_com_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_wakeup_isr, \ + tim8_brk_isr, \ + tim8_up_isr, \ + tim8_trg_com_isr, \ + tim8_cc_isr, \ + adc3_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_isr, \ + tim7_isr, \ + dma2_channel1_isr, \ + dma2_channel2_isr, \ + dma2_channel3_isr, \ + dma2_channel4_5_isr, \ + dma2_channel5_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + +#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h new file mode 100644 index 00000000..7aec1421 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F2_IRQ_H +#define LIBOPENCM3_STM32_F2_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h new file mode 100644 index 00000000..4f4f5e54 --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.h @@ -0,0 +1,359 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_F4_IRQ_H +#define LIBOPENCM3_STM32_F4_IRQ_H + +#define IRQ_WWDG 0 +#define IRQ_PVD 1 +#define IRQ_TAMP_STAMP 2 +#define IRQ_RTC_WKUP 3 +#define IRQ_FLASH 4 +#define IRQ_RCC 5 +#define IRQ_EXTI0 6 +#define IRQ_EXTI1 7 +#define IRQ_EXTI2 8 +#define IRQ_EXTI3 9 +#define IRQ_EXTI4 10 +#define IRQ_DMA1_STREAM0 11 +#define IRQ_DMA1_STREAM1 12 +#define IRQ_DMA1_STREAM2 13 +#define IRQ_DMA1_STREAM3 14 +#define IRQ_DMA1_STREAM4 15 +#define IRQ_DMA1_STREAM5 16 +#define IRQ_DMA1_STREAM6 17 +#define IRQ_ADC 18 +#define IRQ_CAN1_TX 19 +#define IRQ_CAN1_RX0 20 +#define IRQ_CAN1_RX1 21 +#define IRQ_CAN1_SCE 22 +#define IRQ_EXTI9_5 23 +#define IRQ_TIM1_BRK_TIM9 24 +#define IRQ_TIM1_UP_TIM10 25 +#define IRQ_TIM1_TRG_COM_TIM11 26 +#define IRQ_TIM1_CC 27 +#define IRQ_TIM2 28 +#define IRQ_TIM3 29 +#define IRQ_TIM4 30 +#define IRQ_I2C1_EV 31 +#define IRQ_I2C1_ER 32 +#define IRQ_I2C2_EV 33 +#define IRQ_I2C2_ER 34 +#define IRQ_SPI1 35 +#define IRQ_SPI2 36 +#define IRQ_USART1 37 +#define IRQ_USART2 38 +#define IRQ_USART3 39 +#define IRQ_EXTI15_10 40 +#define IRQ_RTC_ALARM 41 +#define IRQ_USB_FS_WKUP 42 +#define IRQ_TIM8_BRK_TIM12 43 +#define IRQ_TIM8_UP_TIM13 44 +#define IRQ_TIM8_TRG_COM_TIM14 45 +#define IRQ_TIM8_CC 46 +#define IRQ_DMA1_STREAM7 47 +#define IRQ_FSMC 48 +#define IRQ_SDIO 49 +#define IRQ_TIM5 50 +#define IRQ_SPI3 51 +#define IRQ_UART4 52 +#define IRQ_UART5 53 +#define IRQ_TIM6_DAC 54 +#define IRQ_TIM7 55 +#define IRQ_DMA2_STREAM0 56 +#define IRQ_DMA2_STREAM1 57 +#define IRQ_DMA2_STREAM2 58 +#define IRQ_DMA2_STREAM3 59 +#define IRQ_DMA2_STREAM4 60 +#define IRQ_ETH 61 +#define IRQ_ETH_WKUP 62 +#define IRQ_CAN2_TX 63 +#define IRQ_CAN2_RX0 64 +#define IRQ_CAN2_RX1 65 +#define IRQ_CAN2_SCE 66 +#define IRQ_OTG_FS 67 +#define IRQ_DMA2_STREAM5 68 +#define IRQ_DMA2_STREAM6 69 +#define IRQ_DMA2_STREAM7 70 +#define IRQ_USART6 71 +#define IRQ_I2C3_EV 72 +#define IRQ_I2C3_ER 73 +#define IRQ_OTG_HS_EP1_OUT 74 +#define IRQ_OTG_HS_EP1_IN 75 +#define IRQ_OTG_HS_WKUP 76 +#define IRQ_OTG_HS 77 +#define IRQ_DCMI 78 +#define IRQ_CRYP 79 +#define IRQ_HASH_RNG 80 + +/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ +#define IRQ_COUNT 81 + +#define WEAK __attribute__ ((weak)) + +void WEAK wwdg_isr(void); +void WEAK pvd_isr(void); +void WEAK tamp_stamp_isr(void); +void WEAK rtc_wkup_isr(void); +void WEAK flash_isr(void); +void WEAK rcc_isr(void); +void WEAK exti0_isr(void); +void WEAK exti1_isr(void); +void WEAK exti2_isr(void); +void WEAK exti3_isr(void); +void WEAK exti4_isr(void); +void WEAK dma1_stream0_isr(void); +void WEAK dma1_stream1_isr(void); +void WEAK dma1_stream2_isr(void); +void WEAK dma1_stream3_isr(void); +void WEAK dma1_stream4_isr(void); +void WEAK dma1_stream5_isr(void); +void WEAK dma1_stream6_isr(void); +void WEAK adc_isr(void); +void WEAK can1_tx_isr(void); +void WEAK can1_rx0_isr(void); +void WEAK can1_rx1_isr(void); +void WEAK can1_sce_isr(void); +void WEAK exti9_5_isr(void); +void WEAK tim1_brk_tim9_isr(void); +void WEAK tim1_up_tim10_isr(void); +void WEAK tim1_trg_com_tim11_isr(void); +void WEAK tim1_cc_isr(void); +void WEAK tim2_isr(void); +void WEAK tim3_isr(void); +void WEAK tim4_isr(void); +void WEAK i2c1_ev_isr(void); +void WEAK i2c1_er_isr(void); +void WEAK i2c2_ev_isr(void); +void WEAK i2c2_er_isr(void); +void WEAK spi1_isr(void); +void WEAK spi2_isr(void); +void WEAK usart1_isr(void); +void WEAK usart2_isr(void); +void WEAK usart3_isr(void); +void WEAK exti15_10_isr(void); +void WEAK rtc_alarm_isr(void); +void WEAK usb_fs_wkup_isr(void); +void WEAK tim8_brk_tim12_isr(void); +void WEAK tim8_up_tim13_isr(void); +void WEAK tim8_trg_com_tim14_isr(void); +void WEAK tim8_cc_isr(void); +void WEAK dma1_stream7_isr(void); +void WEAK fsmc_isr(void); +void WEAK sdio_isr(void); +void WEAK tim5_isr(void); +void WEAK spi3_isr(void); +void WEAK uart4_isr(void); +void WEAK uart5_isr(void); +void WEAK tim6_dac_isr(void); +void WEAK tim7_isr(void); +void WEAK dma2_stream0_isr(void); +void WEAK dma2_stream1_isr(void); +void WEAK dma2_stream2_isr(void); +void WEAK dma2_stream3_isr(void); +void WEAK dma2_stream4_isr(void); +void WEAK eth_isr(void); +void WEAK eth_wkup_isr(void); +void WEAK can2_tx_isr(void); +void WEAK can2_rx0_isr(void); +void WEAK can2_rx1_isr(void); +void WEAK can2_sce_isr(void); +void WEAK otg_fs_isr(void); +void WEAK dma2_stream5_isr(void); +void WEAK dma2_stream6_isr(void); +void WEAK dma2_stream7_isr(void); +void WEAK usart6_isr(void); +void WEAK i2c3_ev_isr(void); +void WEAK i2c3_er_isr(void); +void WEAK otg_hs_ep1_out_isr(void); +void WEAK otg_hs_ep1_in_isr(void); +void WEAK otg_hs_wkup_isr(void); +void WEAK otg_hs_isr(void); +void WEAK dcmi_isr(void); +void WEAK cryp_isr(void); +void WEAK hash_rng_isr(void); + +#pragma weak wwdg_isr = null_handler +#pragma weak pvd_isr = null_handler +#pragma weak tamp_stamp_isr = null_handler +#pragma weak rtc_wkup_isr = null_handler +#pragma weak flash_isr = null_handler +#pragma weak rcc_isr = null_handler +#pragma weak exti0_isr = null_handler +#pragma weak exti1_isr = null_handler +#pragma weak exti2_isr = null_handler +#pragma weak exti3_isr = null_handler +#pragma weak exti4_isr = null_handler +#pragma weak dma1_stream0_isr = null_handler +#pragma weak dma1_stream1_isr = null_handler +#pragma weak dma1_stream2_isr = null_handler +#pragma weak dma1_stream3_isr = null_handler +#pragma weak dma1_stream4_isr = null_handler +#pragma weak dma1_stream5_isr = null_handler +#pragma weak dma1_stream6_isr = null_handler +#pragma weak adc_isr = null_handler +#pragma weak can1_tx_isr = null_handler +#pragma weak can1_rx0_isr = null_handler +#pragma weak can1_rx1_isr = null_handler +#pragma weak can1_sce_isr = null_handler +#pragma weak exti9_5_isr = null_handler +#pragma weak tim1_brk_tim9_isr = null_handler +#pragma weak tim1_up_tim10_isr = null_handler +#pragma weak tim1_trg_com_tim11_isr = null_handler +#pragma weak tim1_cc_isr = null_handler +#pragma weak tim2_isr = null_handler +#pragma weak tim3_isr = null_handler +#pragma weak tim4_isr = null_handler +#pragma weak i2c1_ev_isr = null_handler +#pragma weak i2c1_er_isr = null_handler +#pragma weak i2c2_ev_isr = null_handler +#pragma weak i2c2_er_isr = null_handler +#pragma weak spi1_isr = null_handler +#pragma weak spi2_isr = null_handler +#pragma weak usart1_isr = null_handler +#pragma weak usart2_isr = null_handler +#pragma weak usart3_isr = null_handler +#pragma weak exti15_10_isr = null_handler +#pragma weak rtc_alarm_isr = null_handler +#pragma weak usb_fs_wkup_isr = null_handler +#pragma weak tim8_brk_tim12_isr = null_handler +#pragma weak tim8_up_tim13_isr = null_handler +#pragma weak tim8_trg_com_tim14_isr = null_handler +#pragma weak tim8_cc_isr = null_handler +#pragma weak dma1_stream7_isr = null_handler +#pragma weak fsmc_isr = null_handler +#pragma weak sdio_isr = null_handler +#pragma weak tim5_isr = null_handler +#pragma weak spi3_isr = null_handler +#pragma weak uart4_isr = null_handler +#pragma weak uart5_isr = null_handler +#pragma weak tim6_dac_isr = null_handler +#pragma weak tim7_isr = null_handler +#pragma weak dma2_stream0_isr = null_handler +#pragma weak dma2_stream1_isr = null_handler +#pragma weak dma2_stream2_isr = null_handler +#pragma weak dma2_stream3_isr = null_handler +#pragma weak dma2_stream4_isr = null_handler +#pragma weak eth_isr = null_handler +#pragma weak eth_wkup_isr = null_handler +#pragma weak can2_tx_isr = null_handler +#pragma weak can2_rx0_isr = null_handler +#pragma weak can2_rx1_isr = null_handler +#pragma weak can2_sce_isr = null_handler +#pragma weak otg_fs_isr = null_handler +#pragma weak dma2_stream5_isr = null_handler +#pragma weak dma2_stream6_isr = null_handler +#pragma weak dma2_stream7_isr = null_handler +#pragma weak usart6_isr = null_handler +#pragma weak i2c3_ev_isr = null_handler +#pragma weak i2c3_er_isr = null_handler +#pragma weak otg_hs_ep1_out_isr = null_handler +#pragma weak otg_hs_ep1_in_isr = null_handler +#pragma weak otg_hs_wkup_isr = null_handler +#pragma weak otg_hs_isr = null_handler +#pragma weak dcmi_isr = null_handler +#pragma weak cryp_isr = null_handler +#pragma weak hash_rng_isr = null_handler + +#define IRQ_HANDLERS \ + wwdg_isr, \ + pvd_isr, \ + tamp_stamp_isr, \ + rtc_wkup_isr, \ + flash_isr, \ + rcc_isr, \ + exti0_isr, \ + exti1_isr, \ + exti2_isr, \ + exti3_isr, \ + exti4_isr, \ + dma1_stream0_isr, \ + dma1_stream1_isr, \ + dma1_stream2_isr, \ + dma1_stream3_isr, \ + dma1_stream4_isr, \ + dma1_stream5_isr, \ + dma1_stream6_isr, \ + adc_isr, \ + can1_tx_isr, \ + can1_rx0_isr, \ + can1_rx1_isr, \ + can1_sce_isr, \ + exti9_5_isr, \ + tim1_brk_tim9_isr, \ + tim1_up_tim10_isr, \ + tim1_trg_com_tim11_isr, \ + tim1_cc_isr, \ + tim2_isr, \ + tim3_isr, \ + tim4_isr, \ + i2c1_ev_isr, \ + i2c1_er_isr, \ + i2c2_ev_isr, \ + i2c2_er_isr, \ + spi1_isr, \ + spi2_isr, \ + usart1_isr, \ + usart2_isr, \ + usart3_isr, \ + exti15_10_isr, \ + rtc_alarm_isr, \ + usb_fs_wkup_isr, \ + tim8_brk_tim12_isr, \ + tim8_up_tim13_isr, \ + tim8_trg_com_tim14_isr, \ + tim8_cc_isr, \ + dma1_stream7_isr, \ + fsmc_isr, \ + sdio_isr, \ + tim5_isr, \ + spi3_isr, \ + uart4_isr, \ + uart5_isr, \ + tim6_dac_isr, \ + tim7_isr, \ + dma2_stream0_isr, \ + dma2_stream1_isr, \ + dma2_stream2_isr, \ + dma2_stream3_isr, \ + dma2_stream4_isr, \ + eth_isr, \ + eth_wkup_isr, \ + can2_tx_isr, \ + can2_rx0_isr, \ + can2_rx1_isr, \ + can2_sce_isr, \ + otg_fs_isr, \ + dma2_stream5_isr, \ + dma2_stream6_isr, \ + dma2_stream7_isr, \ + usart6_isr, \ + i2c3_ev_isr, \ + i2c3_er_isr, \ + otg_hs_ep1_out_isr, \ + otg_hs_ep1_in_isr, \ + otg_hs_wkup_isr, \ + otg_hs_isr, \ + dcmi_isr, \ + cryp_isr, \ + hash_rng_isr, + +#endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c new file mode 100644 index 00000000..200e8e58 --- /dev/null +++ b/lib/cm3/vector.c @@ -0,0 +1,95 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski , + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +#define WEAK __attribute__ ((weak)) + +/* Symbols exported by the linker script(s): */ +extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; + +void main(void); +void blocking_handler(void); +void null_handler(void); + +void WEAK reset_handler(void); +void WEAK nmi_handler(void); +void WEAK hard_fault_handler(void); +void WEAK mem_manage_handler(void); +void WEAK bus_fault_handler(void); +void WEAK usage_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK debug_monitor_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); + +__attribute__ ((section(".vectors"))) +vector_table_t vector_table = { + .initial_sp_value = &_stack, + .reset = reset_handler, + .nmi = nmi_handler, + .hard_fault = hard_fault_handler, + .memory_manage_fault = mem_manage_handler, + .bus_fault = bus_fault_handler, + .usage_fault = usage_fault_handler, + .debug_monitor = debug_monitor_handler, + .sv_call = sv_call_handler, + .pend_sv = pend_sv_handler, + .systick = sys_tick_handler, + .irq = { + IRQ_HANDLERS + } +}; + +void WEAK reset_handler(void) +{ + volatile unsigned *src, *dest; + + __asm__("MSR msp, %0" : : "r"(&_stack)); + + for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) + *dest = *src; + + while (dest < &_ebss) + *dest++ = 0; + + /* Call the application's entry point. */ + main(); +} + +void blocking_handler(void) +{ + while (1) ; +} + +void null_handler(void) +{ + /* Do nothing. */ +} + +#pragma weak nmi_handler = null_handler +#pragma weak hard_fault_handler = blocking_handler +#pragma weak mem_manage_handler = blocking_handler +#pragma weak bus_fault_handler = blocking_handler +#pragma weak usage_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak debug_monitor_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c new file mode 100644 index 00000000..d6da5a2b --- /dev/null +++ b/lib/efm32/tinygecko/vector.c @@ -0,0 +1,2 @@ +#include +#include "../../cm3/vector.c" diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 3a1c4d15..e9e7e064 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -1,96 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - - /* TODO: Interrupt handlers */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c index 518f5621..61342f45 100644 --- a/lib/lpc17xx/vector.c +++ b/lib/lpc17xx/vector.c @@ -1,95 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); - -/* TODO: Interrupt handler prototypes */ - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030 */ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ -}; - - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#include +#include "../cm3/vector.c" diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 23008bc9..66e9b639 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -18,156 +18,20 @@ * along with this library. If not, see . */ -#define WEAK __attribute__ ((weak)) +#include +#define reset_handler original_reset_handler +#include "../cm3/vector.c" +#undef reset_handler +#include -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; extern unsigned _etext_ram, _text_ram, _etext_rom; -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - /* Cortex-M4 interrupts */ - (void*)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* reserved */ - pend_sv_handler, - sys_tick_handler, - - /* LPC43xx interrupts */ - dac_irqhandler, - m0core_irqhandler, - dma_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - ethernet_irqhandler, - sdio_irqhandler, - lcd_irqhandler, - usb0_irqhandler, - usb1_irqhandler, - sct_irqhandler, - ritimer_irqhandler, - timer0_irqhandler, - timer1_irqhandler, - timer2_irqhandler, - timer3_irqhandler, - mcpwm_irqhandler, - adc0_irqhandler, - i2c0_irqhandler, - i2c1_irqhandler, - spi_irqhandler, - adc1_irqhandler, - ssp0_irqhandler, - ssp1_irqhandler, - usart0_irqhandler, - uart1_irqhandler, - usart2_irqhandler, - usart3_irqhandler, - i2s0_irqhandler, - i2s1_irqhandler, - spifi_irqhandler, - sgpio_irqhandler, - pin_int0_irqhandler, - pin_int1_irqhandler, - pin_int2_irqhandler, - pin_int3_irqhandler, - pin_int4_irqhandler, - pin_int5_irqhandler, - pin_int6_irqhandler, - pin_int7_irqhandler, - gint0_irqhandler, - gint1_irqhandler, - eventrouter_irqhandler, - c_can1_irqhandler, - 0, /* reserved */ - 0, /* reserved */ - atimer_irqhandler, - rtc_irqhandler, - 0, /* reserved */ - wwdt_irqhandler, - 0, /* reserved */ - c_can0_irqhandler, - qei_irqhandler, -}; - -#define MMIO32(addr) (*(volatile unsigned long*)(addr)) #define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) -void reset_handler(void) +void WEAK reset_handler(void) { volatile unsigned *src, *dest; - __asm__("MSR msp, %0" : : "r"(&_stack)); - /* Copy the code from ROM to Real RAM (if enabled) */ if( (&_etext_ram-&_text_ram) > 0 ) { @@ -186,79 +50,5 @@ void reset_handler(void) /* Continue Execution in RAM */ } - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); + original_reset_handler(); } - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c index f496ae4b..795773b1 100644 --- a/lib/stm32/f1/vector.c +++ b/lib/stm32/f1/vector.c @@ -1,296 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void*)&_stack, /* Addr: 0x0000_0000 */ - reset_handler, /* Addr: 0x0000_0004 */ - nmi_handler, /* Addr: 0x0000_0008 */ - hard_fault_handler, /* Addr: 0x0000_000C */ - mem_manage_handler, /* Addr: 0x0000_0010 */ - bus_fault_handler, /* Addr: 0x0000_0014 */ - usage_fault_handler, /* Addr: 0x0000_0018 */ - 0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */ - sv_call_handler, /* Addr: 0x0000_002C */ - debug_monitor_handler, /* Addr: 0x0000_0030*/ - 0, /* Reserved Addr: 0x0000_00034 */ - pend_sv_handler, /* Addr: 0x0000_0038 */ - sys_tick_handler, /* Addr: 0x0000_003C */ - wwdg_isr, /* Addr: 0x0000_0040 */ - pvd_isr, /* Addr: 0x0000_0044 */ - tamper_isr, /* Addr: 0x0000_0048 */ - rtc_isr, /* Addr: 0x0000_004C */ - flash_isr, /* Addr: 0x0000_0050 */ - rcc_isr, /* Addr: 0x0000_0054 */ - exti0_isr, /* Addr: 0x0000_0058 */ - exti1_isr, /* Addr: 0x0000_005C */ - exti2_isr, /* Addr: 0x0000_0060 */ - exti3_isr, /* Addr: 0x0000_0064 */ - exti4_isr, /* Addr: 0x0000_0068 */ - dma1_channel1_isr, /* Addr: 0x0000_006C */ - dma1_channel2_isr, /* Addr: 0x0000_0070 */ - dma1_channel3_isr, /* Addr: 0x0000_0074 */ - dma1_channel4_isr, /* Addr: 0x0000_0078 */ - dma1_channel5_isr, /* Addr: 0x0000_007C */ - dma1_channel6_isr, /* Addr: 0x0000_0080 */ - dma1_channel7_isr, /* Addr: 0x0000_0084 */ - adc1_2_isr, /* Addr: 0x0000_0088 */ - usb_hp_can_tx_isr, /* Addr: 0x0000_008C */ - usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */ - can_rx1_isr, /* Addr: 0x0000_0094 */ - can_sce_isr, /* Addr: 0x0000_0098 */ - exti9_5_isr, /* Addr: 0x0000_009C */ - tim1_brk_isr, /* Addr: 0x0000_00A0 */ - tim1_up_isr, /* Addr: 0x0000_00A4 */ - tim1_trg_com_isr, /* Addr: 0x0000_00A8 */ - tim1_cc_isr, /* Addr: 0x0000_00AC */ - tim2_isr, /* Addr: 0x0000_00B0 */ - tim3_isr, /* Addr: 0x0000_00B4 */ - tim4_isr, /* Addr: 0x0000_00B8 */ - i2c1_ev_isr, /* Addr: 0x0000_00BC */ - i2c1_er_isr, /* Addr: 0x0000_00C0 */ - i2c2_ev_isr, /* Addr: 0x0000_00C4 */ - i2c2_er_isr, /* Addr: 0x0000_00C8 */ - spi1_isr, /* Addr: 0x0000_00CC */ - spi2_isr, /* Addr: 0x0000_00D0 */ - usart1_isr, /* Addr: 0x0000_00D4 */ - usart2_isr, /* Addr: 0x0000_00D8 */ - usart3_isr, /* Addr: 0x0000_00DC */ - exti15_10_isr, /* Addr: 0x0000_00E0 */ - rtc_alarm_isr, /* Addr: 0x0000_00E4 */ - usb_wakeup_isr, /* Addr: 0x0000_00E8 */ - tim8_brk_isr, /* Addr: 0x0000_00EC */ - tim8_up_isr, /* Addr: 0x0000_00F0 */ - tim8_trg_com_isr, /* Addr: 0x0000_00F4 */ - tim8_cc_isr, /* Addr: 0x0000_00F8 */ - adc3_isr, /* Addr: 0x0000_00FC */ - fsmc_isr, /* Addr: 0x0000_0100 */ - sdio_isr, /* Addr: 0x0000_0104 */ - tim5_isr, /* Addr: 0x0000_0108 */ - spi3_isr, /* Addr: 0x0000_010C */ - uart4_isr, /* Addr: 0x0000_0110 */ - uart5_isr, /* Addr: 0x0000_0114 */ - tim6_isr, /* Addr: 0x0000_0118 */ - tim7_isr, /* Addr: 0x0000_011C */ - dma2_channel1_isr, /* Addr: 0x0000_0120 */ - dma2_channel2_isr, /* Addr: 0x0000_0124 */ - dma2_channel3_isr, /* Addr: 0x0000_0128 */ - dma2_channel4_5_isr, /* Addr: 0x0000_012C */ - dma2_channel5_isr, /* Addr: 0x0000_0130 */ - eth_isr, /* Addr: 0x0000_0134 */ - eth_wkup_isr, /* Addr: 0x0000_0138 */ - can2_tx_isr, /* Addr: 0x0000_013C */ - can2_rx0_isr, /* Addr: 0x0000_0140 */ - can2_rx1_isr, /* Addr: 0x0000_0144 */ - can2_sce_isr, /* Addr: 0x0000_0148 */ - otg_fs_isr, /* Addr: 0x0000_014C */ -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c index 3429bfb0..24d11851 100644 --- a/lib/stm32/f2/vector.c +++ b/lib/stm32/f2/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index 3429bfb0..8d158a6b 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -1,336 +1,2 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#define WEAK __attribute__ ((weak)) - -/* Symbols exported by the linker script(s): */ -extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; - -void main(void); -void reset_handler(void); -void blocking_handler(void); -void null_handler(void); - -void WEAK reset_handler(void); -void WEAK nmi_handler(void); -void WEAK hard_fault_handler(void); -void WEAK mem_manage_handler(void); -void WEAK bus_fault_handler(void); -void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); -void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -__attribute__ ((section(".vectors"))) -void (*const vector_table[]) (void) = { - (void *)&_stack, - reset_handler, - nmi_handler, - hard_fault_handler, - mem_manage_handler, - bus_fault_handler, - usage_fault_handler, - 0, 0, 0, 0, /* Reserved */ - sv_call_handler, - debug_monitor_handler, - 0, /* Reserved */ - pend_sv_handler, - sys_tick_handler, - wwdg_isr, - pvd_isr, - tamp_stamp_isr, - rtc_wkup_isr, - flash_isr, - rcc_isr, - exti0_isr, - exti1_isr, - exti2_isr, - exti3_isr, - exti4_isr, - dma1_stream0_isr, - dma1_stream1_isr, - dma1_stream2_isr, - dma1_stream3_isr, - dma1_stream4_isr, - dma1_stream5_isr, - dma1_stream6_isr, - adc_isr, - can1_tx_isr, - can1_rx0_isr, - can1_rx1_isr, - can1_sce_isr, - exti9_5_isr, - tim1_brk_tim9_isr, - tim1_up_tim10_isr, - tim1_trg_com_tim11_isr, - tim1_cc_isr, - tim2_isr, - tim3_isr, - tim4_isr, - i2c1_ev_isr, - i2c1_er_isr, - i2c2_ev_isr, - i2c2_er_isr, - spi1_isr, - spi2_isr, - usart1_isr, - usart2_isr, - usart3_isr, - exti15_10_isr, - rtc_alarm_isr, - usb_fs_wkup_isr, - tim8_brk_tim12_isr, - tim8_up_tim13_isr, - tim8_trg_com_tim14_isr, - tim8_cc_isr, - dma1_stream7_isr, - fsmc_isr, - sdio_isr, - tim5_isr, - spi3_isr, - uart4_isr, - uart5_isr, - tim6_dac_isr, - tim7_isr, - dma2_stream0_isr, - dma2_stream1_isr, - dma2_stream2_isr, - dma2_stream3_isr, - dma2_stream4_isr, - eth_isr, - eth_wkup_isr, - can2_tx_isr, - can2_rx0_isr, - can2_rx1_isr, - can2_sce_isr, - otg_fs_isr, - dma2_stream5_isr, - dma2_stream6_isr, - dma2_stream7_isr, - usart6_isr, - i2c3_ev_isr, - i2c3_er_isr, - otg_hs_ep1_out_isr, - otg_hs_ep1_in_isr, - otg_hs_wkup_isr, - otg_hs_isr, - dcmi_isr, - cryp_isr, - hash_rng_isr, -}; - -void reset_handler(void) -{ - volatile unsigned *src, *dest; - - __asm__("MSR msp, %0" : : "r"(&_stack)); - - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) - *dest = *src; - - while (dest < &_ebss) - *dest++ = 0; - - /* Call the application's entry point. */ - main(); -} - -void blocking_handler(void) -{ - while (1) ; -} - -void null_handler(void) -{ - /* Do nothing. */ -} - -#pragma weak nmi_handler = null_handler -#pragma weak hard_fault_handler = blocking_handler -#pragma weak mem_manage_handler = blocking_handler -#pragma weak bus_fault_handler = blocking_handler -#pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler -#pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler +#include +#include "../../cm3/vector.c" From 7d0611609bc83abc6c942fe3fd6aeab16376fd7f Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 5 Oct 2012 13:50:42 +0930 Subject: [PATCH 12/35] Code changes to stm32f1 adc.c and adc.h remove rcc_set_adc_clk - use rcc version Added functions: - adc_power_on - adc_start_conversion_direct - adc_set_dual_mode - adc_eoc - adc_eoc_injected - adc_read_regular - adc_read_injected - adc_set_injected_offset Tested dual mode scanned regular, but no tests of injected yet. Changes: "discontinuous" was misspelled. - adc_set_discontinuous_mode_regular - added "length" parameter - adc_disable_discontinuous_mode_regular - name change - adc_enable_discontinuous_mode_injected - name change - adc_enable_automatic_injected_group_conversion - disable triggers - adc_enable_jeoc_interrupt - name change to match common usage in lib - adc_disable_jeoc_interrupt - ditto - adc_enable_external_trigger_regular - remove incorrect test on parameter - adc_enable_external_trigger_injected - ditto - adc_set_sample_time - name change to match function's purpose - adc_set_conversion_time_on_all_channels - ditto - adc_set_injected_sequence - changed order of register loading (ref Barlow's issue) - adc_enable_analog_watchdog_on_all_channels - flipped AWDSGL - adc_enable_analog_watchdog_on_selected_channel - ditto added aliases for expected commonly used functions to avoid sudden user code breakage In adc.h, corrected errors in SQR names added "deprecated" compiler warnings to adc_on and to aliases defined in adc.c --- examples/stm32/f1/lisa-m-2/adc_regular/adc.c | 11 +- .../f1/other/adc_temperature_sensor/adc.c | 10 +- include/libopencm3/stm32/f1/adc.h | 89 ++++---- lib/stm32/f1/adc.c | 208 ++++++++++++++---- 4 files changed, 224 insertions(+), 94 deletions(-) diff --git a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c index 91d029f0..f6442b1a 100644 --- a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c +++ b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c @@ -3,6 +3,7 @@ * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Ken Sarkies * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -71,14 +72,13 @@ void adc_setup(void) /* We configure everything for one single conversion. */ adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_enable_discontinous_mode_regular(ADC1); adc_disable_external_trigger_regular(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -138,10 +138,9 @@ int main(void) /* Continously convert and poll the temperature ADC. */ while (1) { /* - * If the ADC_CR2_ON bit is already set -> setting it another time - * starts the conversion. + * Start the conversion directly (ie without a trigger). */ - adc_on(ADC1); + adc_start_conversion_direct(ADC1); /* Wait for end of conversion. */ while (!(ADC_SR(ADC1) & ADC_SR_EOC)); diff --git a/examples/stm32/f1/other/adc_temperature_sensor/adc.c b/examples/stm32/f1/other/adc_temperature_sensor/adc.c index dea6a7c6..70cc5dac 100644 --- a/examples/stm32/f1/other/adc_temperature_sensor/adc.c +++ b/examples/stm32/f1/other/adc_temperature_sensor/adc.c @@ -69,14 +69,13 @@ void adc_setup(void) /* We configure everything for one single conversion. */ adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_enable_discontinous_mode_regular(ADC1); adc_disable_external_trigger_regular(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -131,10 +130,9 @@ int main(void) adc_set_regular_sequence(ADC1, 1, channel_array); /* - * If the ADC_CR2_ON bit is already set -> setting it another time - * starts the conversion. + * Start the conversion directly (not trigger mode). */ - adc_on(ADC1); + adc_start_conversion_direct(ADC1); /* Wait for end of conversion. */ while (!(ADC_SR(ADC1) & ADC_SR_EOC)); diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 116aeaad..aa54bdf1 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DUALMOD_MASK (0xF << 16) #define ADC_CR1_DUALMOD_SHIFT 16 -/* DISCNUM[2:0]: Discontinous mode channel count. */ +/* DISCNUM[2:0]: Discontinuous mode channel count. */ /****************************************************************************/ /** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. @ingroup STM32F1xx_adc_defines @@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license #define ADC_CR1_DISCNUM_MASK (0x7 << 13) #define ADC_CR1_DISCNUM_SHIFT 13 -/* JDISCEN: */ /** Discontinous mode on injected channels. */ +/* JDISCEN: */ /** Discontinuous mode on injected channels. */ #define ADC_CR1_JDISCEN (1 << 12) -/* DISCEN: */ /** Discontinous mode on regular channels. */ +/* DISCEN: */ /** Discontinuous mode on regular channels. */ #define ADC_CR1_DISCEN (1 << 11) /* JAUTO: */ /** Automatic Injection Group conversion. */ @@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license /* --- ADC_SMPRx generic values -------------------------------------------- */ /****************************************************************************/ /* ADC_SMPRG ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_rg ADC Sample Time Selection Generic +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels @ingroup STM32F1xx_adc_defines @{*/ @@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR1_SQ15_LSB 10 #define ADC_SQR1_SQ14_LSB 5 #define ADC_SQR1_SQ13_LSB 0 -#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB) -/* TODO Fix error #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) #define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) #define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) #define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) #define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) -*/ /* --- ADC_SQR2 values ----------------------------------------------------- */ @@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR2_SQ9_LSB 10 #define ADC_SQR2_SQ8_LSB 5 #define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB) -/* TODO Fix error #define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) #define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) #define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) #define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) #define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) #define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) -*/ /* --- ADC_SQR3 values ----------------------------------------------------- */ @@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR3_SQ3_LSB 10 #define ADC_SQR3_SQ2_LSB 5 #define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB) -/* TODO Fix error #define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) #define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) #define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) #define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) #define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) #define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) -*/ /* --- ADC_JSQR values ----------------------------------------------------- */ #define ADC_JSQR_JL_LSB 20 @@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license #define ADC_JSQR_JSQ3_LSB 10 #define ADC_JSQR_JSQ2_LSB 5 #define ADC_JSQR_JSQ1_LSB 0 -#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB) -#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB) -#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB) -#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB) -#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB) -/* TODO Fix error + +/* JL[2:0]: Discontinous mode channel count injected channels. */ +/****************************************************************************/ +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels. +@ingroup STM32F1xx_adc_defines + +@{*/ +#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) +/**@}*/ +#define ADC_JSQR_JL_SHIFT 13 #define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) #define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) #define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) -*/ /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ @@ -679,22 +662,31 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS +void adc_power_on(u32 adc); +void adc_start_conversion_direct(u32 adc); +void adc_set_single_channel(u32 adc, u8 channel); +void adc_set_dual_mode(u32 mode); +bool adc_eoc(u32 adc); +bool adc_eoc_injected(u32 adc); +u32 adc_read_regular(u32 adc); +u32 adc_read_injected(u32 adc, u8 reg); +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset); void adc_enable_analog_watchdog_regular(u32 adc); void adc_disable_analog_watchdog_regular(u32 adc); void adc_enable_analog_watchdog_injected(u32 adc); void adc_disable_analog_watchdog_injected(u32 adc); -void adc_enable_discontinous_mode_regular(u32 adc); -void adc_disable_discontinous_mode_regular(u32 adc); -void adc_enable_discontinous_mode_injected(u32 adc); -void adc_disable_discontinous_mode_injected(u32 adc); +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length); +void adc_disable_discontinuous_mode_regular(u32 adc); +void adc_enable_discontinuous_mode_injected(u32 adc); +void adc_disable_discontinuous_mode_injected(u32 adc); void adc_enable_automatic_injected_group_conversion(u32 adc); void adc_disable_automatic_injected_group_conversion(u32 adc); void adc_enable_analog_watchdog_on_all_channels(u32 adc); void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel); void adc_enable_scan_mode(u32 adc); void adc_disable_scan_mode(u32 adc); -void adc_enable_jeoc_interrupt(u32 adc); -void adc_disable_jeoc_interrupt(u32 adc); +void adc_enable_eoc_interrupt_injected(u32 adc); +void adc_disable_eoc_interrupt_injected(u32 adc); void adc_enable_awd_interrupt(u32 adc); void adc_disable_awd_interrupt(u32 adc); void adc_enable_eoc_interrupt(u32 adc); @@ -713,17 +705,28 @@ void adc_enable_dma(u32 adc); void adc_disable_dma(u32 adc); void adc_reset_calibration(u32 adc); void adc_calibration(u32 adc); -void adc_set_continous_conversion_mode(u32 adc); +void adc_set_continuous_conversion_mode(u32 adc); void adc_set_single_conversion_mode(u32 adc); +#ifdef __GNUC__ +void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release"))); +#else void adc_on(u32 adc); +#endif void adc_off(u32 adc); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time); +void adc_set_sample_time(u32 adc, u8 channel, u8 time); +void adc_set_sample_time_on_all_channels(u32 adc, u8 time); void adc_set_watchdog_high_threshold(u32 adc, u16 threshold); void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); +#ifdef __GNUC__ +void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode"))); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time"))); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels"))); +void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected"))); +void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected"))); +#endif END_DECLS #endif diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index 433cdd2e..a8bb7460 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -102,38 +102,156 @@ LGPL License Terms @ref lgpl_license #include -void rcc_set_adc_clk(u32 prescaler) +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Power On + +If the ADC is in power-down mode then it is powered up. The application needs +to wait a time of about 3 microseconds for stabilization before using the ADC. +If the ADC is already on this function call has no effect. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_power_on(u32 adc) { - /* TODO */ - - /* FIXME: QUICK HACK to prevent compiler warnings. */ - prescaler = prescaler; -} - -void adc_set_mode(u32 block, /* TODO */ u8 mode) -{ - /* TODO */ - - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - mode = mode; + if (!(ADC_CR2(adc) & ADC_CR2_ADON)) + ADC_CR2(adc) |= ADC_CR2_ADON; } /*-----------------------------------------------------------------------------*/ -/** @brief ADC Read from a Conversion Result Register +/** @brief ADC Start a Conversion Without Trigger + +This initiates a conversion by software without a trigger. The ADC needs to be +powered on before this is called, otherwise this function has no effect. + +Note that this is not available in other STM32F families. To ensure code compatibility, +enable triggering and use a software trigger source @see adc_start_conversion_regular. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +*/ + +void adc_start_conversion_direct(u32 adc) +{ + if (ADC_CR2(adc) & ADC_CR2_ADON) + ADC_CR2(adc) |= ADC_CR2_ADON; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set Dual A/D Mode + +The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting +is applied to ADC1 only. Start of conversion when triggered can cause simultaneous +conversion with ADC2, or alternate conversion. Regular and injected conversions +can be configured, each one being separately simultaneous or alternate. + +@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod +*/ + +void adc_set_dual_mode(u32 mode) +{ + ADC1_CR1 |= mode; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the End-of-Conversion Flag + +This flag is set after all channels of a regular or injected group have been +converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_EOC) != 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion + +This flag is set after all channels of an injected group have been converted. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns bool. End of conversion flag. +*/ + +bool adc_eoc_injected(u32 adc) +{ + return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from the Regular Conversion Result Register + +The result read back is 12 bits, right or left aligned within the first 16 bits. +For ADC1 only, the higher 16 bits will hold the result from ADC2 if +an appropriate dual mode has been set @see adc_set_dual_mode. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@returns Unsigned int32 conversion result. +*/ + +u32 adc_read_regular(u32 adc) +{ + return ADC_DR(adc); +} + +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Read from an Injected Conversion Result Register + +The result read back from the selected injected result register (one of four) is +12 bits, right or left aligned within the first 16 bits. The result can have a +negative value if the injected channel offset has been set @see adc_set_injected_offset. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ -void adc_read(u32 block, u32 channel) +u32 adc_read_injected(u32 adc, u8 reg) { - /* TODO */ + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } + return 0; +} - /* FIXME: QUICK HACK to prevent compiler warnings. */ - block = block; - channel = channel; +/*-----------------------------------------------------------------------------*/ +/** @brief ADC Set the Injected Channel Data Offset + +This value is subtracted from the injected channel results after conversion +is complete, and can result in negative results. A separate value can be specified +for each injected data register. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] reg Unsigned int8. Register number (1 ... 4). +@param[in] offset Unsigned int32. +*/ + +void adc_set_injected_offset(u32 adc, u8 reg, u32 offset) +{ + switch (reg) { + case 1: + ADC_JOFR1(adc) = offset; + break; + case 2: + ADC_JOFR2(adc) = offset; + break; + case 3: + ADC_JOFR3(adc) = offset; + break; + case 4: + ADC_JOFR4(adc) = offset; + break; + } } /*-----------------------------------------------------------------------------*/ @@ -203,9 +321,11 @@ of the subgroup at the beginning of the whole group. @param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum */ -void adc_enable_discontinous_mode_regular(u32 adc) +void adc_enable_discontinuous_mode_regular(u32 adc, u8 length) { - ADC_CR1(adc) |= ADC_CR1_DISCEN; + if ( (length-1) > 7 ) return; + ADC_CR1(adc) |= ADC_CR1_DISCEN; + ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } /*-----------------------------------------------------------------------------*/ @@ -214,7 +334,7 @@ void adc_enable_discontinous_mode_regular(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_discontinous_mode_regular(u32 adc) +void adc_disable_discontinuous_mode_regular(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } @@ -229,7 +349,7 @@ entire group has been converted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_enable_discontinous_mode_injected(u32 adc) +void adc_enable_discontinuous_mode_injected(u32 adc) { ADC_CR1(adc) |= ADC_CR1_JDISCEN; } @@ -240,7 +360,7 @@ void adc_enable_discontinous_mode_injected(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_discontinous_mode_injected(u32 adc) +void adc_disable_discontinuous_mode_injected(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } @@ -257,6 +377,7 @@ channels is disabled as required. void adc_enable_automatic_injected_group_conversion(u32 adc) { + adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } @@ -288,7 +409,7 @@ disabled. void adc_enable_analog_watchdog_on_all_channels(u32 adc) { - ADC_CR1(adc) |= ADC_CR1_AWDSGL; + ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } /*-----------------------------------------------------------------------------*/ @@ -315,7 +436,7 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) if (channel < 18) reg32 |= channel; ADC_CR1(adc) = reg32; - ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; + ADC_CR1(adc) |= ADC_CR1_AWDSGL; } /*-----------------------------------------------------------------------------*/ @@ -350,7 +471,7 @@ void adc_disable_scan_mode(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_enable_jeoc_interrupt(u32 adc) +void adc_enable_eoc_interrupt_injected(u32 adc) { ADC_CR1(adc) |= ADC_CR1_JEOCIE; } @@ -361,7 +482,7 @@ void adc_enable_jeoc_interrupt(u32 adc) @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_disable_jeoc_interrupt(u32 adc) +void adc_disable_eoc_interrupt_injected(u32 adc) { ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } @@ -519,8 +640,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger) u32 reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK)); - if (trigger < 8) - reg32 |= (trigger); + reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_EXTTRIG; } @@ -565,14 +685,12 @@ For ADC3 @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3 */ - void adc_enable_external_trigger_injected(u32 adc, u32 trigger) { u32 reg32; reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */ - if (trigger < 8) - reg32 |= (trigger); + reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; } @@ -681,7 +799,7 @@ group immediately following completion of the previous channel group conversion. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ -void adc_set_continous_conversion_mode(u32 adc) +void adc_set_continuous_conversion_mode(u32 adc) { ADC_CR2(adc) |= ADC_CR2_CONT; } @@ -707,7 +825,7 @@ If the ADC is in power-down mode then it is powered up. The application needs to wait a time of about 3 microseconds for stabilization before using the ADC. If the ADC is already on this function call will initiate a conversion. -@todo fix this. +@deprecated to be removed in a later release @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -740,7 +858,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ -void adc_set_conversion_time(u32 adc, u8 channel, u8 time) +void adc_set_sample_time(u32 adc, u8 channel, u8 time) { u32 reg32; @@ -767,7 +885,7 @@ all channels. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) +void adc_set_sample_time_on_all_channels(u32 adc, u8 time) { u8 i; u32 reg32 = 0; @@ -871,12 +989,24 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) return; for (i = 1; i <= length; i++) - reg32 |= (channel[i - 1] << ((i - 1) * 5)); + reg32 |= (channel[4 - i] << ((4 - i) * 5)); reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } +/*-----------------------------------------------------------------------------*/ + +/* Aliases */ + +#ifdef __GNUC__ +void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode"))); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time"))); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels"))); +void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected"))); +void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected"))); +#endif + /**@}*/ From 4efa64c2785692b422988f7444e737c67931ea5d Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Fri, 5 Oct 2012 14:04:40 +0930 Subject: [PATCH 13/35] Doc changes to go with previous commit --- lib/stm32/f1/adc.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index a8bb7460..0a05aacf 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -44,12 +44,12 @@ conversion, which occurs after all channels have been scanned. @section adc_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set dual mode to independent. +and ADC, reset ADC and set the prescaler divider. Set dual mode to independent +(default). Enable triggering for a software trigger. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); - adc_power_on(ADC1); - adc_calibration(ADC1); + adc_off(ADC1); rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); @@ -58,6 +58,10 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent. adc_set_single_conversion_mode(ADC1); adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); adc_set_single_channel(ADC1, ADC_CHANNEL0); + adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); + adc_power_on(ADC1); + adc_reset_calibration(ADC1); + adc_calibration(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); @@ -144,6 +148,31 @@ is applied to ADC1 only. Start of conversion when triggered can cause simultaneo conversion with ADC2, or alternate conversion. Regular and injected conversions can be configured, each one being separately simultaneous or alternate. +Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock +cycles later. + +Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock +cycles later, followed by ADC1 fourteen cycles later again. This can only be used +on a single channel. + +Alternate trigger mode must occur on an injected channel group, and alternates +between the ADCs on each trigger. + +Note that sampling must not overlap between ADCs on the same channel. + +Dual A/D converter modes possible: + +@li IND: Independent mode. +@li CRSISM: Combined regular simultaneous + injected simultaneous mode. +@li CRSATM: Combined regular simultaneous + alternate trigger mode. +@li CISFIM: Combined injected simultaneous + fast interleaved mode. +@li CISSIM: Combined injected simultaneous + slow interleaved mode. +@li ISM: Injected simultaneous mode only. +@li RSM: Regular simultaneous mode only. +@li FIM: Fast interleaved mode only. +@li SIM: Slow interleaved mode only. +@li ATM: Alternate trigger mode only. + @param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod */ From bece4c30d3b953cd7f469d9db06559ca443df189 Mon Sep 17 00:00:00 2001 From: Stephen Dwyer Date: Fri, 5 Oct 2012 11:40:21 -0600 Subject: [PATCH 14/35] added different ADC sampling examples for the LisaM v2 including: * simple polling of an injected channel * timer triggered sampling of an injected channel * timer triggered sampling and IRQ handling of an injected channel * timer triggered sampling and IRQ handling of 4 injected channels --- examples/stm32/f1/lisa-m-2/adc_injec/Makefile | 27 ++ examples/stm32/f1/lisa-m-2/adc_injec/README | 11 + .../stm32/f1/lisa-m-2/adc_injec/adc_injec.c | 174 +++++++++++++ .../f1/lisa-m-2/adc_injec_timtrig/Makefile | 27 ++ .../f1/lisa-m-2/adc_injec_timtrig/README | 11 + .../adc_injec_timtrig/adc_injec_timtrig.c | 195 +++++++++++++++ .../lisa-m-2/adc_injec_timtrig_irq/Makefile | 27 ++ .../f1/lisa-m-2/adc_injec_timtrig_irq/README | 12 + .../adc_injec_timtrig_irq.c | 211 ++++++++++++++++ .../adc_injec_timtrig_irq_4ch/Makefile | 27 ++ .../lisa-m-2/adc_injec_timtrig_irq_4ch/README | 12 + .../adc_injec_timtrig_irq_4ch.c | 230 ++++++++++++++++++ 12 files changed, 964 insertions(+) create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec/Makefile create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec/README create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig/README create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/README create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/README create mode 100644 examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c diff --git a/examples/stm32/f1/lisa-m-2/adc_injec/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec/Makefile new file mode 100644 index 00000000..20355ceb --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec/Makefile @@ -0,0 +1,27 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = adc +# Comment the following line if you _don't_ have luftboot flashed! +LDFLAGS += -Wl,-Ttext=0x8002000 +CFLAGS += -std=c99 +LDSCRIPT = ../lisa-m.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec/README b/examples/stm32/f1/lisa-m-2/adc_injec/README new file mode 100644 index 00000000..f0c7d624 --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a simple polling example that sends the value read out from the +temperature sensor ADC channel of the STM32 to the USART2. + +This example polls injected channels. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c b/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c new file mode 100644 index 00000000..cba90f65 --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c @@ -0,0 +1,174 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Stephen Dwyer + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART2, 115200); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX_RX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) +{ + /* Enable GPIO clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Setup the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); +} + +void adc_setup(void) +{ + int i; + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + + /* Make sure the ADC doesn't run during config. */ + adc_off(ADC1); + + /* We configure everything for one single injected conversion. */ + adc_disable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + /* We can only use discontinuous mode on either the regular OR injected channels, not both */ + adc_disable_discontinous_mode_regular(ADC1); + adc_enable_discontinous_mode_injected(ADC1); + /* We want to start the injected conversion in software */ + adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_JSWSTART); + adc_set_right_aligned(ADC1); + /* We want to read the temperature sensor, so we have to enable it. */ + adc_enable_temperature_sensor(ADC1); + adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + + adc_on(ADC1); + + /* Wait for ADC starting up. */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + + adc_reset_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_RSTCAL) != 0); //added this check + adc_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_CAL) != 0); //added this check +} + +void my_usart_print_int(u32 usart, int value) +{ + s8 i; + u8 nr_digits = 0; + char buffer[25]; + + if (value < 0) { + usart_send_blocking(usart, '-'); + value = value * -1; + } + + while (value > 0) { + buffer[nr_digits++] = "0123456789"[value % 10]; + value /= 10; + } + + for (i = (nr_digits - 1); i >= 0; i--) { + usart_send_blocking(usart, buffer[i]); + } + + usart_send_blocking(usart, '\r'); +} + +int main(void) +{ + u8 channel_array[16]; + u16 temperature = 0; + + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + adc_setup(); + + gpio_set(GPIOA, GPIO8); /* LED1 on */ + gpio_set(GPIOC, GPIO15); /* LED2 on */ + + /* Send a message on USART1. */ + usart_send_blocking(USART2, 's'); + usart_send_blocking(USART2, 't'); + usart_send_blocking(USART2, 'm'); + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + + /* Select the channel we want to convert. 16=temperature_sensor. */ + channel_array[0] = 16; + /* Set the injected sequence here, with number of channels */ + adc_set_injected_sequence(ADC1, 1, channel_array); + + /* Continously convert and poll the temperature ADC. */ + while (1) { + /* + * If the ADC_CR2_ON bit is already set -> setting it another time + * starts a regular conversion. Injected conversion is started + * explicitly with the JSWSTART bit as an external trigger. It may + * also work by setting no regular channels and setting JAUTO to + * automatically convert the injected channels after the regular + * channels (of which there would be none). (Not tested.) + */ + adc_start_conversion_injected(ADC1); + + /* Wait for end of conversion. */ + while (!(ADC_SR(ADC1) & ADC_SR_JEOC)); + ADC_SR(ADC2) &= ~ADC_SR_JEOC; //clear injected end of conversion + + temperature = ADC_JDR1(ADC1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) + + /* + * That's actually not the real temperature - you have to compute it + * as described in the datasheet. + */ + my_usart_print_int(USART2, temperature); + + gpio_toggle(GPIOA, GPIO8); /* LED2 on */ + + } + + return 0; +} diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile new file mode 100644 index 00000000..20355ceb --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile @@ -0,0 +1,27 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = adc +# Comment the following line if you _don't_ have luftboot flashed! +LDFLAGS += -Wl,-Ttext=0x8002000 +CFLAGS += -std=c99 +LDSCRIPT = ../lisa-m.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/README b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/README new file mode 100644 index 00000000..d690f8a7 --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/README @@ -0,0 +1,11 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a simple example that sends the value read out from the +temperature sensor ADC channel of the STM32 to the USART2. + +This example uses a timer trigger to automatically sample the adc channel. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c new file mode 100644 index 00000000..cb9f15d0 --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c @@ -0,0 +1,195 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Stephen Dwyer + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART2, 115200); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX_RX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) +{ + /* Enable GPIO clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Setup the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); +} + +void timer_setup(void) +{ + /* Set up the timer TIM2 for injected sampling */ + uint32_t timer; + volatile uint32_t *rcc_apbenr; + uint32_t rcc_apb; + + timer = TIM2; + rcc_apbenr = &RCC_APB1ENR; + rcc_apb = RCC_APB1ENR_TIM2EN; + + rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb); + + /* Time Base configuration */ + timer_reset(timer); + timer_set_mode(timer, TIM_CR1_CKD_CK_INT, + TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + timer_set_period(timer, 0xFF); + timer_set_prescaler(timer, 0x8); + timer_set_clock_division(timer, 0x0); + /* Generate TRGO on every update. */ + timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); + timer_enable_counter(timer); +} + +void adc_setup(void) +{ + int i; + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + + /* Make sure the ADC doesn't run during config. */ + adc_off(ADC1); + + /* We configure everything for one single timer triggered injected conversion. */ + adc_disable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + /* We can only use discontinuous mode on either the regular OR injected channels, not both */ + adc_disable_discontinous_mode_regular(ADC1); + adc_enable_discontinous_mode_injected(ADC1); + /* We want to start the injected conversion with the TIM2 TRGO */ + adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); + adc_set_right_aligned(ADC1); + /* We want to read the temperature sensor, so we have to enable it. */ + adc_enable_temperature_sensor(ADC1); + adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + + adc_on(ADC1); + + /* Wait for ADC starting up. */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + + adc_reset_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_RSTCAL) != 0); + adc_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_CAL) != 0); +} + +void my_usart_print_int(u32 usart, int value) +{ + s8 i; + u8 nr_digits = 0; + char buffer[25]; + + if (value < 0) { + usart_send_blocking(usart, '-'); + value = value * -1; + } + + while (value > 0) { + buffer[nr_digits++] = "0123456789"[value % 10]; + value /= 10; + } + + for (i = (nr_digits - 1); i >= 0; i--) { + usart_send_blocking(usart, buffer[i]); + } + + usart_send_blocking(usart, '\r'); +} + +int main(void) +{ + u8 channel_array[16]; + u16 temperature = 0; + + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + timer_setup(); + adc_setup(); + + gpio_set(GPIOA, GPIO8); /* LED1 on */ + gpio_set(GPIOC, GPIO15); /* LED2 on */ + + /* Send a message on USART1. */ + usart_send_blocking(USART2, 's'); + usart_send_blocking(USART2, 't'); + usart_send_blocking(USART2, 'm'); + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + + /* Select the channel we want to convert. 16=temperature_sensor. */ + channel_array[0] = 16; + /* Set the injected sequence here, with number of channels */ + adc_set_injected_sequence(ADC1, 1, channel_array); + + /* Continously convert and poll the temperature ADC. */ + while (1) { + /* + * Since the injected sampling is triggered by the timer, it gets + * updated automatically, we just need to periodically read out the value. + * It would be better to check if the JEOC bit is set, and clear it following + * so that you do not read the same value twice, especially for a slower + * sampling rate. + */ + + temperature = ADC_JDR1(ADC1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) + + /* + * That's actually not the real temperature - you have to compute it + * as described in the datasheet. + */ + my_usart_print_int(USART2, temperature); + + gpio_toggle(GPIOA, GPIO8); /* LED2 on */ + + } + + return 0; +} diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile new file mode 100644 index 00000000..20355ceb --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile @@ -0,0 +1,27 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = adc +# Comment the following line if you _don't_ have luftboot flashed! +LDFLAGS += -Wl,-Ttext=0x8002000 +CFLAGS += -std=c99 +LDSCRIPT = ../lisa-m.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/README b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/README new file mode 100644 index 00000000..175edcea --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a simple example that sends the value read out from the +temperature sensor ADC channel of the STM32 to the USART2. + +This example uses a timer trigger to sample an injected adc channel and +then uses an interrupt routine to retrieve the sample from the data register. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c new file mode 100644 index 00000000..73814d83 --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c @@ -0,0 +1,211 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Stephen Dwyer + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +volatile u16 temperature = 0; + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART2, 115200); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX_RX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) +{ + /* Enable GPIO clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Setup the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); +} + +void timer_setup(void) +{ + /* Set up the timer TIM2 for injected sampling */ + uint32_t timer; + volatile uint32_t *rcc_apbenr; + uint32_t rcc_apb; + + timer = TIM2; + rcc_apbenr = &RCC_APB1ENR; + rcc_apb = RCC_APB1ENR_TIM2EN; + + rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb); + + /* Time Base configuration */ + timer_reset(timer); + timer_set_mode(timer, TIM_CR1_CKD_CK_INT, + TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + timer_set_period(timer, 0xFF); + timer_set_prescaler(timer, 0x8); + timer_set_clock_division(timer, 0x0); + /* Generate TRGO on every update. */ + timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); + timer_enable_counter(timer); +} + +void irq_setup(void) +{ + /* Enable the adc1_2_isr() routine */ + nvic_set_priority(NVIC_ADC1_2_IRQ, 0); + nvic_enable_irq(NVIC_ADC1_2_IRQ); +} + +void adc_setup(void) +{ + int i; + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + + /* Make sure the ADC doesn't run during config. */ + adc_off(ADC1); + + /* We configure everything for one single timer triggered injected conversion with interrupt generation. */ + /* While not needed for a single channel, try out scan mode which does all channels in one sweep and + * generates the interrupt/EOC/JEOC flags set at the end of all channels, not each one. + */ + adc_enable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + /* We want to start the injected conversion with the TIM2 TRGO */ + adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); + /* Generate the ADC1_2_IRQ */ + adc_enable_jeoc_interrupt(ADC1); + adc_set_right_aligned(ADC1); + /* We want to read the temperature sensor, so we have to enable it. */ + adc_enable_temperature_sensor(ADC1); + adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + + adc_on(ADC1); + + /* Wait for ADC starting up. */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + + adc_reset_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_RSTCAL) != 0); + adc_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_CAL) != 0); +} + +void my_usart_print_int(u32 usart, int value) +{ + s8 i; + u8 nr_digits = 0; + char buffer[25]; + + if (value < 0) { + usart_send_blocking(usart, '-'); + value = value * -1; + } + + while (value > 0) { + buffer[nr_digits++] = "0123456789"[value % 10]; + value /= 10; + } + + for (i = (nr_digits - 1); i >= 0; i--) { + usart_send_blocking(usart, buffer[i]); + } + + usart_send_blocking(usart, '\r'); +} + +int main(void) +{ + u8 channel_array[16]; + + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + timer_setup(); + irq_setup(); + adc_setup(); + + gpio_set(GPIOA, GPIO8); /* LED1 on */ + gpio_set(GPIOC, GPIO15); /* LED2 on */ + + /* Send a message on USART1. */ + usart_send_blocking(USART2, 's'); + usart_send_blocking(USART2, 't'); + usart_send_blocking(USART2, 'm'); + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + + /* Select the channel we want to convert. 16=temperature_sensor. */ + channel_array[0] = 16; + /* Set the injected sequence here, with number of channels */ + adc_set_injected_sequence(ADC1, 1, channel_array); + + /* Continously convert and poll the temperature ADC. */ + while (1) { + /* + * Since sampling is triggered by the timer and copying the value + * out of the data register is handled by the interrupt routine, + * we just need to print the value and toggle the LED. It may be useful + * to buffer the adc values in some cases. + */ + + /* + * That's actually not the real temperature - you have to compute it + * as described in the datasheet. + */ + my_usart_print_int(USART2, temperature); + + gpio_toggle(GPIOA, GPIO8); /* LED2 on */ + + } + + return 0; +} + +void adc1_2_isr(void) +{ + /* Clear Injected End Of Conversion (JEOC) */ + ADC_SR(ADC1) &= ~ADC_SR_JEOC; + temperature = ADC_JDR1(ADC1); +} diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile new file mode 100644 index 00000000..20355ceb --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile @@ -0,0 +1,27 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +BINARY = adc +# Comment the following line if you _don't_ have luftboot flashed! +LDFLAGS += -Wl,-Ttext=0x8002000 +CFLAGS += -std=c99 +LDSCRIPT = ../lisa-m.ld + +include ../../Makefile.include + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/README b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/README new file mode 100644 index 00000000..0339a11d --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/README @@ -0,0 +1,12 @@ +------------------------------------------------------------------------------ +README +------------------------------------------------------------------------------ + +This is a simple example that sends the values read out from four ADC +channels of the STM32 to the USART2. + +This example uses a timer trigger to sample the injected adc channels and +then uses an interrupt routine to retrieve the samples from the data registers. + +The terminal settings for the receiving device/PC are 115200 8n1. + diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c new file mode 100644 index 00000000..9331bb9f --- /dev/null +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c @@ -0,0 +1,230 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Stephen Dwyer + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +volatile u16 temperature = 0; +volatile u16 v_refint = 0; +volatile u16 lisam_adc1 = 0; +volatile u16 lisam_adc2 = 0; +u8 channel_array[4]; /* for injected sampling, 4 channels max, for regular, 16 max */ + +void usart_setup(void) +{ + /* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN); + + /* Setup GPIO pin GPIO_USART1_TX/GPIO9 on GPIO port A for transmit. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, + GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); + + /* Setup UART parameters. */ + usart_set_baudrate(USART2, 115200); + usart_set_databits(USART2, 8); + usart_set_stopbits(USART2, USART_STOPBITS_1); + usart_set_mode(USART2, USART_MODE_TX_RX); + usart_set_parity(USART2, USART_PARITY_NONE); + usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); + + /* Finally enable the USART. */ + usart_enable(USART2); +} + +void gpio_setup(void) +{ + /* Enable GPIO clocks. */ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPCEN); + + /* Setup the LEDs. */ + gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO8); + gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, GPIO15); + + /* Setup Lisa/M v2 ADC1,2 on ANALOG1 connector */ + gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, \ + GPIO3 | GPIO0 ); +} + +void timer_setup(void) +{ + /* Set up the timer TIM2 for injected sampling */ + uint32_t timer; + volatile uint32_t *rcc_apbenr; + uint32_t rcc_apb; + + timer = TIM2; + rcc_apbenr = &RCC_APB1ENR; + rcc_apb = RCC_APB1ENR_TIM2EN; + + rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb); + + /* Time Base configuration */ + timer_reset(timer); + timer_set_mode(timer, TIM_CR1_CKD_CK_INT, + TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + timer_set_period(timer, 0xFF); + timer_set_prescaler(timer, 0x8); + timer_set_clock_division(timer, 0x0); + /* Generate TRGO on every update. */ + timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); + timer_enable_counter(timer); +} + +void irq_setup(void) +{ + /* Enable the adc1_2_isr() routine */ + nvic_set_priority(NVIC_ADC1_2_IRQ, 0); + nvic_enable_irq(NVIC_ADC1_2_IRQ); +} + +void adc_setup(void) +{ + int i; + + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + + /* Make sure the ADC doesn't run during config. */ + adc_off(ADC1); + + /* We configure everything for one single timer triggered injected conversion with interrupt generation. */ + /* While not needed for a single channel, try out scan mode which does all channels in one sweep and + * generates the interrupt/EOC/JEOC flags set at the end of all channels, not each one. + */ + adc_enable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + /* We want to start the injected conversion with the TIM2 TRGO */ + adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); + /* Generate the ADC1_2_IRQ */ + adc_enable_jeoc_interrupt(ADC1); + adc_set_right_aligned(ADC1); + /* We want to read the temperature sensor, so we have to enable it. */ + adc_enable_temperature_sensor(ADC1); + adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + + /* Select the channels we want to convert. + * 16=temperature_sensor, 17=Vrefint, 13=ADC1, 10=ADC2 + */ + channel_array[0] = 16; + channel_array[1] = 17; + channel_array[2] = 13; + channel_array[3] = 10; + adc_set_injected_sequence(ADC1, 4, channel_array); + + adc_on(ADC1); + + /* Wait for ADC starting up. */ + for (i = 0; i < 800000; i++) /* Wait a bit. */ + __asm__("nop"); + + adc_reset_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_RSTCAL) != 0); //added this check + adc_calibration(ADC1); + while ((ADC_CR2(ADC1) & ADC_CR2_CAL) != 0); //added this check +} + +void my_usart_print_int(u32 usart, int value) +{ + s8 i; + u8 nr_digits = 0; + char buffer[25]; + + if (value < 0) { + usart_send_blocking(usart, '-'); + value = value * -1; + } + + while (value > 0) { + buffer[nr_digits++] = "0123456789"[value % 10]; + value /= 10; + } + + for (i = (nr_digits - 1); i >= 0; i--) { + usart_send_blocking(usart, buffer[i]); + } + + //usart_send_blocking(usart, '\r'); +} + +int main(void) +{ + + rcc_clock_setup_in_hse_12mhz_out_72mhz(); + gpio_setup(); + usart_setup(); + timer_setup(); + irq_setup(); + adc_setup(); + + gpio_set(GPIOA, GPIO8); /* LED1 off */ + gpio_set(GPIOC, GPIO15); /* LED5 off */ + + /* Send a message on USART1. */ + usart_send_blocking(USART2, 's'); + usart_send_blocking(USART2, 't'); + usart_send_blocking(USART2, 'm'); + usart_send_blocking(USART2, '\r'); + usart_send_blocking(USART2, '\n'); + + /* Moved the channel selection and sequence init to adc_setup() */ + + /* Continously convert and poll the temperature ADC. */ + while (1) { + /* + * Since sampling is triggered by the timer and copying the values + * out of the data registers is handled by the interrupt routine, + * we just need to print the values and toggle the LED. It may be useful + * to buffer the adc values in some cases. + */ + + my_usart_print_int(USART2, temperature); + usart_send_blocking(USART2, ' '); + my_usart_print_int(USART2, v_refint); + usart_send_blocking(USART2, ' '); + my_usart_print_int(USART2, lisam_adc1); + usart_send_blocking(USART2, ' '); + my_usart_print_int(USART2, lisam_adc2); + usart_send_blocking(USART2, '\r'); + + gpio_toggle(GPIOA, GPIO8); /* LED2 on */ + + } + + return 0; +} + +void adc1_2_isr(void) +{ + /* Clear Injected End Of Conversion (JEOC) */ + ADC_SR(ADC1) &= ~ADC_SR_JEOC; + temperature = ADC_JDR1(ADC1); + v_refint = ADC_JDR2(ADC1); + lisam_adc1 = ADC_JDR3(ADC1); + lisam_adc2 = ADC_JDR4(ADC1); +} From 794f3fbeda3ec1dc7de1b9023eef44e4169a7ea1 Mon Sep 17 00:00:00 2001 From: Stephen Dwyer Date: Fri, 5 Oct 2012 11:47:33 -0600 Subject: [PATCH 15/35] oops, had to update bin names in makefiles for adc examples --- examples/stm32/f1/lisa-m-2/adc_injec/Makefile | 2 +- examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile | 2 +- examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile | 2 +- examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/examples/stm32/f1/lisa-m-2/adc_injec/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec/Makefile index 20355ceb..e50737bf 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec/Makefile +++ b/examples/stm32/f1/lisa-m-2/adc_injec/Makefile @@ -17,7 +17,7 @@ ## along with this library. If not, see . ## -BINARY = adc +BINARY = adc_injec # Comment the following line if you _don't_ have luftboot flashed! LDFLAGS += -Wl,-Ttext=0x8002000 CFLAGS += -std=c99 diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile index 20355ceb..af2e9e65 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/Makefile @@ -17,7 +17,7 @@ ## along with this library. If not, see . ## -BINARY = adc +BINARY = adc_injec_timtrig # Comment the following line if you _don't_ have luftboot flashed! LDFLAGS += -Wl,-Ttext=0x8002000 CFLAGS += -std=c99 diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile index 20355ceb..c88152e2 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/Makefile @@ -17,7 +17,7 @@ ## along with this library. If not, see . ## -BINARY = adc +BINARY = adc_injec_timtrig_irq # Comment the following line if you _don't_ have luftboot flashed! LDFLAGS += -Wl,-Ttext=0x8002000 CFLAGS += -std=c99 diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile index 20355ceb..d9a74a28 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/Makefile @@ -17,7 +17,7 @@ ## along with this library. If not, see . ## -BINARY = adc +BINARY = adc_injec_timtrig_irq_4ch # Comment the following line if you _don't_ have luftboot flashed! LDFLAGS += -Wl,-Ttext=0x8002000 CFLAGS += -std=c99 From 2b8fbfc433fe75efaa323d0b085e6d54a1221975 Mon Sep 17 00:00:00 2001 From: Stephen Dwyer Date: Sun, 7 Oct 2012 17:53:09 -0600 Subject: [PATCH 16/35] updated the lisa_m_2 (STM32 F1) ADC examples for recent code changes to stm32f1 adc.c and adc.h --- examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c | 12 ++++++------ .../lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c | 10 +++++----- .../adc_injec_timtrig_irq/adc_injec_timtrig_irq.c | 8 ++++---- .../adc_injec_timtrig_irq_4ch.c | 14 +++++++------- examples/stm32/f1/lisa-m-2/adc_regular/adc.c | 4 ++-- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c b/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c index cba90f65..eab78875 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec/adc_injec.c @@ -73,16 +73,16 @@ void adc_setup(void) adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); /* We can only use discontinuous mode on either the regular OR injected channels, not both */ - adc_disable_discontinous_mode_regular(ADC1); - adc_enable_discontinous_mode_injected(ADC1); + adc_disable_discontinuous_mode_regular(ADC1); + adc_enable_discontinuous_mode_injected(ADC1); /* We want to start the injected conversion in software */ adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_JSWSTART); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -155,10 +155,10 @@ int main(void) adc_start_conversion_injected(ADC1); /* Wait for end of conversion. */ - while (!(ADC_SR(ADC1) & ADC_SR_JEOC)); + while (!(adc_eoc_injected(ADC1))); ADC_SR(ADC2) &= ~ADC_SR_JEOC; //clear injected end of conversion - temperature = ADC_JDR1(ADC1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) + temperature = adc_read_injected(ADC1,1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) /* * That's actually not the real temperature - you have to compute it diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c index cb9f15d0..d675723e 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c @@ -99,16 +99,16 @@ void adc_setup(void) adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); /* We can only use discontinuous mode on either the regular OR injected channels, not both */ - adc_disable_discontinous_mode_regular(ADC1); - adc_enable_discontinous_mode_injected(ADC1); + adc_disable_discontinuous_mode_regular(ADC1); + adc_enable_discontinuous_mode_injected(ADC1); /* We want to start the injected conversion with the TIM2 TRGO */ adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -179,7 +179,7 @@ int main(void) * sampling rate. */ - temperature = ADC_JDR1(ADC1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) + temperature = adc_read_injected(ADC1,1); //get the result from ADC_JDR1 on ADC1 (only bottom 16bits) /* * That's actually not the real temperature - you have to compute it diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c index 73814d83..bda1d9dc 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c @@ -114,13 +114,13 @@ void adc_setup(void) /* We want to start the injected conversion with the TIM2 TRGO */ adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); /* Generate the ADC1_2_IRQ */ - adc_enable_jeoc_interrupt(ADC1); + adc_enable_eoc_interrupt_injected(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -207,5 +207,5 @@ void adc1_2_isr(void) { /* Clear Injected End Of Conversion (JEOC) */ ADC_SR(ADC1) &= ~ADC_SR_JEOC; - temperature = ADC_JDR1(ADC1); + temperature = adc_read_injected(ADC1,1); } diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c index 9331bb9f..13341841 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c @@ -122,11 +122,11 @@ void adc_setup(void) /* We want to start the injected conversion with the TIM2 TRGO */ adc_enable_external_trigger_injected(ADC1,ADC_CR2_JEXTSEL_TIM2_TRGO); /* Generate the ADC1_2_IRQ */ - adc_enable_jeoc_interrupt(ADC1); + adc_enable_eoc_interrupt_injected(ADC1); adc_set_right_aligned(ADC1); /* We want to read the temperature sensor, so we have to enable it. */ adc_enable_temperature_sensor(ADC1); - adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); + adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC); /* Select the channels we want to convert. * 16=temperature_sensor, 17=Vrefint, 13=ADC1, 10=ADC2 @@ -137,7 +137,7 @@ void adc_setup(void) channel_array[3] = 10; adc_set_injected_sequence(ADC1, 4, channel_array); - adc_on(ADC1); + adc_power_on(ADC1); /* Wait for ADC starting up. */ for (i = 0; i < 800000; i++) /* Wait a bit. */ @@ -223,8 +223,8 @@ void adc1_2_isr(void) { /* Clear Injected End Of Conversion (JEOC) */ ADC_SR(ADC1) &= ~ADC_SR_JEOC; - temperature = ADC_JDR1(ADC1); - v_refint = ADC_JDR2(ADC1); - lisam_adc1 = ADC_JDR3(ADC1); - lisam_adc2 = ADC_JDR4(ADC1); + temperature = adc_read_injected(ADC1,1); + v_refint = adc_read_injected(ADC1,2); + lisam_adc1 = adc_read_injected(ADC1,3); + lisam_adc2 = adc_read_injected(ADC1,4); } diff --git a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c index f6442b1a..9bbbe032 100644 --- a/examples/stm32/f1/lisa-m-2/adc_regular/adc.c +++ b/examples/stm32/f1/lisa-m-2/adc_regular/adc.c @@ -143,9 +143,9 @@ int main(void) adc_start_conversion_direct(ADC1); /* Wait for end of conversion. */ - while (!(ADC_SR(ADC1) & ADC_SR_EOC)); + while (!(adc_eoc(ADC1))); - temperature = ADC_DR(ADC1); + temperature = adc_read_regular(ADC1); /* * That's actually not the real temperature - you have to compute it From 8f9f2bdc005648c19fbe62426210b3b560662776 Mon Sep 17 00:00:00 2001 From: "Thomas W. Barr" Date: Mon, 8 Oct 2012 16:40:36 -0500 Subject: [PATCH 17/35] complete peripheral handlers in vector table --- lib/lm3s/vector.c | 364 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 361 insertions(+), 3 deletions(-) diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c index 3a1c4d15..b7c92aef 100644 --- a/lib/lm3s/vector.c +++ b/lib/lm3s/vector.c @@ -37,7 +37,117 @@ void WEAK debug_monitor_handler(void); void WEAK pend_sv_handler(void); void WEAK sys_tick_handler(void); -/* TODO: Interrupt handler prototypes */ +void WEAK gpioa_handler(void); +void WEAK gpiob_handler(void); +void WEAK gpioc_handler(void); +void WEAK gpiod_handler(void); +void WEAK gpioe_handler(void); +void WEAK uart0_handler(void); +void WEAK uart1_handler(void); +void WEAK ssi0_handler(void); +void WEAK i2c0_handler(void); +void WEAK pwm0_fault_handler(void); +void WEAK pwm0_0_handler(void); +void WEAK pwm0_1_handler(void); +void WEAK pwm0_2_handler(void); +void WEAK qei0_handler(void); +void WEAK adc0ss0_handler(void); +void WEAK adc0ss1_handler(void); +void WEAK adc0ss2_handler(void); +void WEAK adc0ss3_handler(void); +void WEAK watchdog_handler(void); +void WEAK timer0a_handler(void); +void WEAK timer0b_handler(void); +void WEAK timer1a_handler(void); +void WEAK timer1b_handler(void); +void WEAK timer2a_handler(void); +void WEAK timer2b_handler(void); +void WEAK comp0_handler(void); +void WEAK comp1_handler(void); +void WEAK comp2_handler(void); +void WEAK sysctl_handler(void); +void WEAK flash_handler(void); +void WEAK gpiof_handler(void); +void WEAK gpiog_handler(void); +void WEAK gpioh_handler(void); +void WEAK uart2_handler(void); +void WEAK ssi1_handler(void); +void WEAK timer3a_handler(void); +void WEAK timer3b_handler(void); +void WEAK i2c1_handler(void); +void WEAK qei1_handler(void); +void WEAK can0_handler(void); +void WEAK can1_handler(void); +void WEAK can2_handler(void); +void WEAK eth_handler(void); +void WEAK hibernate_handler(void); +void WEAK usb0_handler(void); +void WEAK pwm0_3_handler(void); +void WEAK udma_handler(void); +void WEAK udmaerr_handler(void); +void WEAK adc1ss0_handler(void); +void WEAK adc1ss1_handler(void); +void WEAK adc1ss2_handler(void); +void WEAK adc1ss3_handler(void); +void WEAK i2s0_handler(void); +void WEAK epi0_handler(void); +void WEAK gpioj_handler(void); +void WEAK gpiok_handler(void); +void WEAK gpiol_handler(void); +void WEAK ssi2_handler(void); +void WEAK ssi3_handler(void); +void WEAK uart3_handler(void); +void WEAK uart4_handler(void); +void WEAK uart5_handler(void); +void WEAK uart6_handler(void); +void WEAK uart7_handler(void); +void WEAK i2c2_handler(void); +void WEAK i2c3_handler(void); +void WEAK timer4a_handler(void); +void WEAK timer4b_handler(void); +void WEAK timer5a_handler(void); +void WEAK timer5b_handler(void); +void WEAK wtimer0a_handler(void); +void WEAK wtimer0b_handler(void); +void WEAK wtimer1a_handler(void); +void WEAK wtimer1b_handler(void); +void WEAK wtimer2a_handler(void); +void WEAK wtimer2b_handler(void); +void WEAK wtimer3a_handler(void); +void WEAK wtimer3b_handler(void); +void WEAK wtimer4a_handler(void); +void WEAK wtimer4b_handler(void); +void WEAK wtimer5a_handler(void); +void WEAK wtimer5b_handler(void); +void WEAK sysexc_handler(void); +void WEAK peci0_handler(void); +void WEAK lpc0_handler(void); +void WEAK i2c4_handler(void); +void WEAK i2c5_handler(void); +void WEAK gpiom_handler(void); +void WEAK gpion_handler(void); +void WEAK fan0_handler(void); +void WEAK gpiop0_handler(void); +void WEAK gpiop1_handler(void); +void WEAK gpiop2_handler(void); +void WEAK gpiop3_handler(void); +void WEAK gpiop4_handler(void); +void WEAK gpiop5_handler(void); +void WEAK gpiop6_handler(void); +void WEAK gpiop7_handler(void); +void WEAK gpioq0_handler(void); +void WEAK gpioq1_handler(void); +void WEAK gpioq2_handler(void); +void WEAK gpioq3_handler(void); +void WEAK gpioq4_handler(void); +void WEAK gpioq5_handler(void); +void WEAK gpioq6_handler(void); +void WEAK gpioq7_handler(void); +void WEAK pwm1_0_handler(void); +void WEAK pwm1_1_handler(void); +void WEAK pwm1_2_handler(void); +void WEAK pwm1_3_handler(void); +void WEAK pwm1_fault_handler(void); __attribute__ ((section(".vectors"))) void (*const vector_table[]) (void) = { @@ -55,7 +165,145 @@ void (*const vector_table[]) (void) = { pend_sv_handler, sys_tick_handler, - /* TODO: Interrupt handlers */ + gpioa_handler, /* 16 */ + gpiob_handler, /* 17 */ + gpioc_handler, /* 18 */ + gpiod_handler, /* 19 */ + gpioe_handler, /* 20 */ + uart0_handler, /* 21 */ + uart1_handler, /* 22 */ + ssi0_handler, /* 23 */ + i2c0_handler, /* 24 */ + pwm0_fault_handler, /* 25 */ + pwm0_0_handler, /* 26 */ + pwm0_1_handler, /* 27 */ + pwm0_2_handler, /* 28 */ + qei0_handler, /* 29 */ + adc0ss0_handler, /* 30 */ + adc0ss1_handler, /* 31 */ + adc0ss2_handler, /* 32 */ + adc0ss3_handler, /* 33 */ + watchdog_handler, /* 34 */ + timer0a_handler, /* 35 */ + timer0b_handler, /* 36 */ + timer1a_handler, /* 37 */ + timer1b_handler, /* 38 */ + timer2a_handler, /* 39 */ + timer2b_handler, /* 40 */ + comp0_handler, /* 41 */ + comp1_handler, /* 42 */ + comp2_handler, /* 43 */ + sysctl_handler, /* 44 */ + flash_handler, /* 45 */ + gpiof_handler, /* 46 */ + gpiog_handler, /* 47 */ + gpioh_handler, /* 48 */ + uart2_handler, /* 49 */ + ssi1_handler, /* 50 */ + timer3a_handler, /* 51 */ + timer3b_handler, /* 52 */ + i2c1_handler, /* 53 */ + qei1_handler, /* 54 */ + can0_handler, /* 55 */ + can1_handler, /* 56 */ + can2_handler, /* 57 */ + eth_handler, /* 58 */ + hibernate_handler, /* 59 */ + usb0_handler, /* 60 */ + pwm0_3_handler, /* 61 */ + udma_handler, /* 62 */ + udmaerr_handler, /* 63 */ + adc1ss0_handler, /* 64 */ + adc1ss1_handler, /* 65 */ + adc1ss2_handler, /* 66 */ + adc1ss3_handler, /* 67 */ + i2s0_handler, /* 68 */ + epi0_handler, /* 69 */ + gpioj_handler, /* 70 */ + gpiok_handler, /* 71 */ + gpiol_handler, /* 72 */ + ssi2_handler, /* 73 */ + ssi3_handler, /* 74 */ + uart3_handler, /* 75 */ + uart4_handler, /* 76 */ + uart5_handler, /* 77 */ + uart6_handler, /* 78 */ + uart7_handler, /* 79 */ + 0, /* 80 */ + 0, /* 81 */ + 0, /* 82 */ + 0, /* 83 */ + i2c2_handler, /* 84 */ + i2c3_handler, /* 85 */ + timer4a_handler, /* 86 */ + timer4b_handler, /* 87 */ + 0, /* 88 */ + 0, /* 89 */ + 0, /* 90 */ + 0, /* 91 */ + 0, /* 92 */ + 0, /* 93 */ + 0, /* 94 */ + 0, /* 95 */ + 0, /* 96 */ + 0, /* 97 */ + 0, /* 98 */ + 0, /* 99 */ + 0, /* 100 */ + 0, /* 101 */ + 0, /* 102 */ + 0, /* 103 */ + 0, /* 104 */ + 0, /* 105 */ + 0, /* 106 */ + 0, /* 107 */ + timer5a_handler, /* 108 */ + timer5b_handler, /* 109 */ + wtimer0a_handler, /* 110 */ + wtimer0b_handler, /* 111 */ + wtimer1a_handler, /* 112 */ + wtimer1b_handler, /* 113 */ + wtimer2a_handler, /* 114 */ + wtimer2b_handler, /* 115 */ + wtimer3a_handler, /* 116 */ + wtimer3b_handler, /* 117 */ + wtimer4a_handler, /* 118 */ + wtimer4b_handler, /* 119 */ + wtimer5a_handler, /* 120 */ + wtimer5b_handler, /* 121 */ + sysexc_handler, /* 122 */ + peci0_handler, /* 123 */ + lpc0_handler, /* 124 */ + i2c4_handler, /* 125 */ + i2c5_handler, /* 126 */ + gpiom_handler, /* 127 */ + gpion_handler, /* 128 */ + 0, /* 129 */ + fan0_handler, /* 130 */ + 0, /* 131 */ + gpiop0_handler, /* 132 */ + gpiop1_handler, /* 133 */ + gpiop2_handler, /* 134 */ + gpiop3_handler, /* 135 */ + gpiop4_handler, /* 136 */ + gpiop5_handler, /* 137 */ + gpiop6_handler, /* 138 */ + gpiop7_handler, /* 139 */ + gpioq0_handler, /* 140 */ + gpioq1_handler, /* 141 */ + gpioq2_handler, /* 142 */ + gpioq3_handler, /* 143 */ + gpioq4_handler, /* 144 */ + gpioq5_handler, /* 145 */ + gpioq6_handler, /* 146 */ + gpioq7_handler, /* 147 */ + 0, /* 148 */ + 0, /* 149 */ + pwm1_0_handler, /* 150 */ + pwm1_1_handler, /* 151 */ + pwm1_2_handler, /* 152 */ + pwm1_3_handler, /* 153 */ + pwm1_fault_handler, /* 154 */ }; void reset_handler(void) @@ -93,4 +341,114 @@ void null_handler(void) #pragma weak debug_monitor_handler = null_handler #pragma weak pend_sv_handler = null_handler #pragma weak sys_tick_handler = null_handler -/* TODO: Interrupt handler weak aliases */ +#pragma weak gpioa_handler = null_handler +#pragma weak gpiob_handler = null_handler +#pragma weak gpioc_handler = null_handler +#pragma weak gpiod_handler = null_handler +#pragma weak gpioe_handler = null_handler +#pragma weak uart0_handler = null_handler +#pragma weak uart1_handler = null_handler +#pragma weak ssi0_handler = null_handler +#pragma weak i2c0_handler = null_handler +#pragma weak pwm0_fault_handler = null_handler +#pragma weak pwm0_0_handler = null_handler +#pragma weak pwm0_1_handler = null_handler +#pragma weak pwm0_2_handler = null_handler +#pragma weak qei0_handler = null_handler +#pragma weak adc0ss0_handler = null_handler +#pragma weak adc0ss1_handler = null_handler +#pragma weak adc0ss2_handler = null_handler +#pragma weak adc0ss3_handler = null_handler +#pragma weak watchdog_handler = null_handler +#pragma weak timer0a_handler = null_handler +#pragma weak timer0b_handler = null_handler +#pragma weak timer1a_handler = null_handler +#pragma weak timer1b_handler = null_handler +#pragma weak timer2a_handler = null_handler +#pragma weak timer2b_handler = null_handler +#pragma weak comp0_handler = null_handler +#pragma weak comp1_handler = null_handler +#pragma weak comp2_handler = null_handler +#pragma weak sysctl_handler = null_handler +#pragma weak flash_handler = null_handler +#pragma weak gpiof_handler = null_handler +#pragma weak gpiog_handler = null_handler +#pragma weak gpioh_handler = null_handler +#pragma weak uart2_handler = null_handler +#pragma weak ssi1_handler = null_handler +#pragma weak timer3a_handler = null_handler +#pragma weak timer3b_handler = null_handler +#pragma weak i2c1_handler = null_handler +#pragma weak qei1_handler = null_handler +#pragma weak can0_handler = null_handler +#pragma weak can1_handler = null_handler +#pragma weak can2_handler = null_handler +#pragma weak eth_handler = null_handler +#pragma weak hibernate_handler = null_handler +#pragma weak usb0_handler = null_handler +#pragma weak pwm0_3_handler = null_handler +#pragma weak udma_handler = null_handler +#pragma weak udmaerr_handler = null_handler +#pragma weak adc1ss0_handler = null_handler +#pragma weak adc1ss1_handler = null_handler +#pragma weak adc1ss2_handler = null_handler +#pragma weak adc1ss3_handler = null_handler +#pragma weak i2s0_handler = null_handler +#pragma weak epi0_handler = null_handler +#pragma weak gpioj_handler = null_handler +#pragma weak gpiok_handler = null_handler +#pragma weak gpiol_handler = null_handler +#pragma weak ssi2_handler = null_handler +#pragma weak ssi3_handler = null_handler +#pragma weak uart3_handler = null_handler +#pragma weak uart4_handler = null_handler +#pragma weak uart5_handler = null_handler +#pragma weak uart6_handler = null_handler +#pragma weak uart7_handler = null_handler +#pragma weak i2c2_handler = null_handler +#pragma weak i2c3_handler = null_handler +#pragma weak timer4a_handler = null_handler +#pragma weak timer4b_handler = null_handler +#pragma weak timer5a_handler = null_handler +#pragma weak timer5b_handler = null_handler +#pragma weak wtimer0a_handler = null_handler +#pragma weak wtimer0b_handler = null_handler +#pragma weak wtimer1a_handler = null_handler +#pragma weak wtimer1b_handler = null_handler +#pragma weak wtimer2a_handler = null_handler +#pragma weak wtimer2b_handler = null_handler +#pragma weak wtimer3a_handler = null_handler +#pragma weak wtimer3b_handler = null_handler +#pragma weak wtimer4a_handler = null_handler +#pragma weak wtimer4b_handler = null_handler +#pragma weak wtimer5a_handler = null_handler +#pragma weak wtimer5b_handler = null_handler +#pragma weak sysexc_handler = null_handler +#pragma weak peci0_handler = null_handler +#pragma weak lpc0_handler = null_handler +#pragma weak i2c4_handler = null_handler +#pragma weak i2c5_handler = null_handler +#pragma weak gpiom_handler = null_handler +#pragma weak gpion_handler = null_handler +#pragma weak fan0_handler = null_handler +#pragma weak gpiop0_handler = null_handler +#pragma weak gpiop1_handler = null_handler +#pragma weak gpiop2_handler = null_handler +#pragma weak gpiop3_handler = null_handler +#pragma weak gpiop4_handler = null_handler +#pragma weak gpiop5_handler = null_handler +#pragma weak gpiop6_handler = null_handler +#pragma weak gpiop7_handler = null_handler +#pragma weak gpioq0_handler = null_handler +#pragma weak gpioq1_handler = null_handler +#pragma weak gpioq2_handler = null_handler +#pragma weak gpioq3_handler = null_handler +#pragma weak gpioq4_handler = null_handler +#pragma weak gpioq5_handler = null_handler +#pragma weak gpioq6_handler = null_handler +#pragma weak gpioq7_handler = null_handler +#pragma weak pwm1_0_handler = null_handler +#pragma weak pwm1_1_handler = null_handler +#pragma weak pwm1_2_handler = null_handler +#pragma weak pwm1_3_handler = null_handler +#pragma weak pwm1_fault_handler = null_handler From f94d71efee4afd49e475f056707fa34b0820e664 Mon Sep 17 00:00:00 2001 From: "Thomas W. Barr" Date: Mon, 8 Oct 2012 16:42:47 -0500 Subject: [PATCH 18/35] add _end and __end symbols for compatibility with code written against CodeSourcery linkers --- lib/lm3s/libopencm3_lm3s.ld | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/lm3s/libopencm3_lm3s.ld b/lib/lm3s/libopencm3_lm3s.ld index ceb391ac..4aaf4d92 100644 --- a/lib/lm3s/libopencm3_lm3s.ld +++ b/lib/lm3s/libopencm3_lm3s.ld @@ -77,6 +77,8 @@ SECTIONS . = ALIGN(4); end = .; + _end = .; + __end = .; } PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); From 0834f41383df854c30f4db973c3632439d7d9cca Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Tue, 9 Oct 2012 11:50:57 +1030 Subject: [PATCH 19/35] stm32f1: Add object files to Makefile to include new modules into lib. Correct typo in pwr.c Add two new functions to timer.c to preset the counter (for use with deadman style timeouts) and to identify an interrupt source. Also noticed lib/makefile.include didn't clean lib/stm32, which isn't a target. Added a fix. --- include/libopencm3/stm32/timer.h | 2 ++ lib/Makefile.include | 2 +- lib/stm32/f1/Makefile | 2 +- lib/stm32/f1/pwr.c | 10 ++++---- lib/stm32/f1/timer.c | 39 ++++++++++++++++++++++++++++++++ 5 files changed, 48 insertions(+), 7 deletions(-) diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index b6f89497..61d40e91 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1028,6 +1028,7 @@ BEGIN_DECLS void timer_reset(u32 timer_peripheral); void timer_enable_irq(u32 timer_peripheral, u32 irq); void timer_disable_irq(u32 timer_peripheral, u32 irq); +bool timer_return_interrupt_source(u32 timer_peripheral, u32 flag); bool timer_get_flag(u32 timer_peripheral, u32 flag); void timer_clear_flag(u32 timer_peripheral, u32 flag); void timer_set_mode(u32 timer_peripheral, u32 clock_div, @@ -1090,6 +1091,7 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock); void timer_set_deadtime(u32 timer_peripheral, u32 deadtime); void timer_generate_event(u32 timer_peripheral, u32 event); u32 timer_get_counter(u32 timer_peripheral); +void timer_set_counter(u32 timer_peripheral, u32 count); void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt); void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc); diff --git a/lib/Makefile.include b/lib/Makefile.include index f2f1f7b2..9fbea244 100644 --- a/lib/Makefile.include +++ b/lib/Makefile.include @@ -40,7 +40,7 @@ $(SRCLIBDIR)/$(LIBNAME).ld: $(LIBNAME).ld clean: @printf " CLEAN lib/stm32/f1\n" - $(Q)rm -f *.o *.d + $(Q)rm -f *.o *.d ../*.o ../*.d $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).a $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME).ld $(Q)rm -f $(SRCLIBDIR)/$(LIBNAME)_rom_to_ram.ld diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 4fdbf434..a2f7bf28 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \ rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o crc.o assert.o + timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o VPATH += ../../usb:../:../../cm3 diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c index 83c3dba5..451ed1cf 100644 --- a/lib/stm32/f1/pwr.c +++ b/lib/stm32/f1/pwr.c @@ -157,7 +157,7 @@ The wakeup pin is used for waking the processor from standby mode. void pwr_enable_wakeup_pin(void) { - PWR_CSR |= PWR_CR_EWUP; + PWR_CSR |= PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ @@ -168,7 +168,7 @@ The wakeup pin is used for general purpose I/O. void pwr_disable_wakeup_pin(void) { - PWR_CSR &= ~PWR_CR_EWUP; + PWR_CSR &= ~PWR_CSR_EWUP; } /*---------------------------------------------------------------------------*/ @@ -183,7 +183,7 @@ threshold. bool pwr_voltage_high(void) { - return (PWR_CSR & PWR_CR_PVDO); + return (PWR_CSR & PWR_CSR_PVDO); } /*---------------------------------------------------------------------------*/ @@ -197,7 +197,7 @@ cleared by software (see @ref pwr_clear_standby_flag). bool pwr_get_standby_flag(void) { - return (PWR_CSR & PWR_CR_SBF); + return (PWR_CSR & PWR_CSR_SBF); } /*---------------------------------------------------------------------------*/ @@ -211,7 +211,7 @@ cleared by software (see @ref pwr_clear_wakeup_flag). bool pwr_get_wakeup_flag(void) { - return (PWR_CSR & PWR_CR_WUF); + return (PWR_CSR & PWR_CSR_WUF); } /**@}*/ diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index c5ea921f..384eaaf0 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -198,6 +198,31 @@ void timer_disable_irq(u32 timer_peripheral, u32 irq) TIM_DIER(timer_peripheral) &= ~irq; } +/*---------------------------------------------------------------------------*/ +/** @brief Return Interrupt Source. + +Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF +for advanced timers) was set and the interrupt was enabled. If the specified flag +is not an interrupt flag, the function returns false. + +@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here. + +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. +@returns boolean: flag set. +*/ + +bool timer_interrupt_source(u32 timer_peripheral, u32 flag) +{ +/* flag not set or interrupt disabled or not an interrupt source */ + if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) || + (flag > TIM_SR_BIF)) return false; +/* Only an interrupt source for advanced timers */ + if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF)) + return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)); + return true; +} + /*---------------------------------------------------------------------------*/ /** @brief Read a Status Flag. @@ -1671,6 +1696,20 @@ u32 timer_get_counter(u32 timer_peripheral) return TIM_CNT(timer_peripheral); } +/*---------------------------------------------------------------------------*/ +/** @brief Set Counter + +Set the value of a timer's counter register contents. + +@param[in] timer_peripheral Unsigned int32. Timer register address base +@param[in] Unsigned int32. Counter value. +*/ + +void timer_set_counter(u32 timer_peripheral, u32 count) +{ + TIM_CNT(timer_peripheral) = count; +} + /*---------------------------------------------------------------------------*/ /** @brief Set Input Capture Filter Parameters From 6ee8e44bd7743806eeb1ba0983fd1113c519f71c Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:31:31 +1030 Subject: [PATCH 20/35] Initial documentation for stm32/usart.c, usart.h Some minor documentation corrections to timer.h --- doc/stm32f1/DoxygenLayout_stm32f1.xml | 2 +- include/libopencm3/stm32/timer.h | 26 ++-- include/libopencm3/stm32/usart.h | 77 +++++++++-- lib/stm32/usart.c | 187 ++++++++++++++++++++++++++ 4 files changed, 267 insertions(+), 25 deletions(-) diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml index 912f2c40..6ed9bbad 100644 --- a/doc/stm32f1/DoxygenLayout_stm32f1.xml +++ b/doc/stm32f1/DoxygenLayout_stm32f1.xml @@ -6,7 +6,7 @@ - + diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 61d40e91..4977674d 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -1,6 +1,6 @@ /** @defgroup STM32F_tim_defines Timers Defines -@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers +@brief libopencm3 Defined Constants and Types for the STM32 Timers @ingroup STM32F_defines @@ -44,7 +44,7 @@ LGPL License Terms @ref lgpl_license /* Timer register base adresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM1 TIM1_BASE @@ -251,7 +251,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* CKD[1:0]: Clock division */ @@ -267,7 +267,7 @@ LGPL License Terms @ref lgpl_license /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) @@ -280,7 +280,7 @@ LGPL License Terms @ref lgpl_license /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR1_DIR_UP (0 << 4) @@ -303,7 +303,7 @@ LGPL License Terms @ref lgpl_license /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ @@ -335,7 +335,7 @@ LGPL License Terms @ref lgpl_license /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) @@ -397,7 +397,7 @@ LGPL License Terms @ref lgpl_license /* TS[2:0]: Trigger selection */ /** @defgroup tim_ts TS Trigger selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Internal Trigger 0 (ITR0) */ @@ -421,7 +421,7 @@ LGPL License Terms @ref lgpl_license /* SMS[2:0]: Slave mode selection */ /** @defgroup tim_sms SMS Slave mode selection -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /** Slave mode disabled */ @@ -451,7 +451,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ /* TDE:*//** Trigger DMA request enable */ @@ -503,7 +503,7 @@ and generates an update of the registers. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -548,7 +548,7 @@ and generates an update of the registers. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ @@ -908,7 +908,7 @@ and generates an update of the registers. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup STM32F1xx_tim_defines +@ingroup STM32F_tim_defines @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 9ec6c3db..911781b3 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -1,3 +1,18 @@ +/** @defgroup STM32F_usart_defines USART Defines + +@brief libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 1 September 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -17,6 +32,8 @@ * along with this library. If not, see . */ +/**@{*/ + #ifndef LIBOPENCM3_USART_H #define LIBOPENCM3_USART_H @@ -25,9 +42,15 @@ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE +/**@}*/ #define UART4 UART4_BASE #define UART5 UART5_BASE @@ -90,37 +113,43 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines -/* CTS: CTS flag */ -/* Note: N/A on UART4/5 */ +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ #define USART_SR_CTS (1 << 9) -/* LBD: LIN break detection flag */ +/** LBD: LIN break detection flag */ #define USART_SR_LBD (1 << 8) -/* TXE: Transmit data buffer empty */ +/** TXE: Transmit data buffer empty */ #define USART_SR_TXE (1 << 7) -/* TC: Transmission complete */ +/** TC: Transmission complete */ #define USART_SR_TC (1 << 6) -/* RXNE: Read data register not empty */ +/** RXNE: Read data register not empty */ #define USART_SR_RXNE (1 << 5) -/* IDLE: Idle line detected */ +/** IDLE: Idle line detected */ #define USART_SR_IDLE (1 << 4) -/* ORE: Overrun error */ +/** ORE: Overrun error */ #define USART_SR_ORE (1 << 3) -/* NE: Noise error flag */ +/** NE: Noise error flag */ #define USART_SR_NE (1 << 2) -/* FE: Framing error */ +/** FE: Framing error */ #define USART_SR_FE (1 << 1) -/* PE: Parity error */ +/** PE: Parity error */ #define USART_SR_PE (1 << 0) +/**@}*/ /* --- USART_DR values ----------------------------------------------------- */ @@ -269,27 +298,51 @@ /* --- Convenience defines ------------------------------------------------- */ /* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_PARITY_NONE 0x00 #define USART_PARITY_EVEN USART_CR1_PCE #define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ #define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) /* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_MODE_RX USART_CR1_RE #define USART_MODE_TX USART_CR1_TE #define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ #define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ #define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ #define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +/**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ #define USART_FLOWCONTROL_NONE 0x00 #define USART_FLOWCONTROL_RTS USART_CR3_RTSE #define USART_FLOWCONTROL_CTS USART_CR3_CTSE #define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ #define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) /* --- Function prototypes ------------------------------------------------- */ @@ -318,3 +371,5 @@ void usart_disable_tx_dma(u32 usart); END_DECLS #endif +/**@}*/ + diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 1d0ea9bb..2958d7c7 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -1,3 +1,22 @@ +/** @defgroup STM32F1xx_usart_file USART + +@ingroup STM32F_files + +@brief libopencm3 STM32F USART + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 30 August 2012 + +This library supports the USART/UART in the STM32F series +of ARM Cortex Microcontrollers by ST Microelectronics. + +Devices can have up to 3 USARTs and 2 UARTs. + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,6 +36,8 @@ * along with this library. If not, see . */ +/**@{*/ + #include #if defined(STM32F1) @@ -29,6 +50,20 @@ # error "stm32 family not defined." #endif +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Baudrate. + +The baud rate is computed from the APB high-speed prescaler clock (for USART1) +or the APB low-speed prescaler clock (for other USARTs). These values must +be correctly set before calling this function (refer to the rcc_clock_setup-* +functions in RCC). + +@todo Add support for USART6 and oversampling in F2/F4 + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] baud unsigned 32 bit. Baud rate specified in Hz. +*/ + void usart_set_baudrate(u32 usart, u32 baud) { u32 clock = rcc_ppre1_frequency; @@ -59,6 +94,16 @@ void usart_set_baudrate(u32 usart, u32 baud) USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Word Length. + +The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit +if parity is enabled, in which case the data length will be 7 or 8 bits respectively. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] bits unsigned 32 bit. Word length in bits 8 or 9. +*/ + void usart_set_databits(u32 usart, u32 bits) { if (bits == 8) @@ -67,6 +112,15 @@ void usart_set_databits(u32 usart, u32 bits) USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Stop Bit(s). + +The stop bits are specified as 0.5, 1, 1.5 or 2. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. +*/ + void usart_set_stopbits(u32 usart, u32 stopbits) { u32 reg32; @@ -76,6 +130,15 @@ void usart_set_stopbits(u32 usart, u32 stopbits) USART_CR2(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Parity. + +The parity bit can be selected as none, even or odd. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. +*/ + void usart_set_parity(u32 usart, u32 parity) { u32 reg32; @@ -85,6 +148,15 @@ void usart_set_parity(u32 usart, u32 parity) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Rx/Tx Mode. + +The mode can be selected as Rx only, Tx only or Rx+Tx. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. +*/ + void usart_set_mode(u32 usart, u32 mode) { u32 reg32; @@ -94,6 +166,15 @@ void usart_set_mode(u32 usart, u32 mode) USART_CR1(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Set Hardware Flow Control. + +The flow control bit can be selected as none, RTS, CTS or RTS+CTS. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. +*/ + void usart_set_flow_control(u32 usart, u32 flowcontrol) { u32 reg32; @@ -103,46 +184,112 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol) USART_CR3(usart) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable(u32 usart) { USART_CR1(usart) |= USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Disable. + +At the end of the current frame, the USART is disabled to reduce power. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable(u32 usart) { USART_CR1(usart) &= ~USART_CR1_UE; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send a Data Word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send(u32 usart, u16 data) { /* Send data. */ USART_DR(usart) = (data & USART_DR_MASK); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word. + +If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv(u32 usart) { /* Receive data. */ return USART_DR(usart) & USART_DR_MASK; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Transmit Data Buffer Empty + +Blocks until the transmit data buffer becomes empty and is ready to accept the +next data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_send_ready(u32 usart) { /* Wait until the data has been transferred into the shift register. */ while ((USART_SR(usart) & USART_SR_TXE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Wait for Received Data Available + +Blocks until the receive data buffer holds a valid received data word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_wait_recv_ready(u32 usart) { /* Wait until the data is ready to be received. */ while ((USART_SR(usart) & USART_SR_RXNE) == 0); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Send Data Word with Blocking + +Blocks until the transmit data buffer becomes empty then writes the next data word +for transmission. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] data unsigned 16 bit. +*/ + void usart_send_blocking(u32 usart, u16 data) { usart_wait_send_ready(usart); usart_send(usart, data); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Read a Received Data Word with Blocking. + +Wait until a data word has been received then return the word. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@returns unsigned 16 bit data word. +*/ + u16 usart_recv_blocking(u32 usart) { usart_wait_recv_ready(usart); @@ -150,22 +297,62 @@ u16 usart_recv_blocking(u32 usart) return usart_recv(usart); } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Enable. + +DMA is available on: +@li USART1 Rx DMA1 channel 5. +@li USART2 Rx DMA1 channel 6. +@li USART3 Rx DMA1 channel 3. +@li UART4 Rx DMA2 channel 3. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_rx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_rx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAR; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Enable. + +DMA is available on: +@li USART1 Tx DMA1 channel 4. +@li USART2 Tx DMA1 channel 7. +@li USART3 Tx DMA1 channel 2. +@li UART4 Tx DMA2 channel 5. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_enable_tx_dma(u32 usart) { USART_CR3(usart) |= USART_CR3_DMAT; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter DMA Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + void usart_disable_tx_dma(u32 usart) { USART_CR3(usart) &= ~USART_CR3_DMAT; } + + +/**@}*/ + From c4b7e2a76a52a53e0ba6ccd1a6f9d699036bea48 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Wed, 10 Oct 2012 21:37:39 +1030 Subject: [PATCH 21/35] Additional stm32/usart.c functions to enable/disable Rx/Tx interrupts, return a status flag and check for interrupt source. --- include/libopencm3/stm32/usart.h | 6 +++ lib/stm32/usart.c | 86 ++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 911781b3..088e67b3 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -367,6 +367,12 @@ void usart_enable_rx_dma(u32 usart); void usart_disable_rx_dma(u32 usart); void usart_enable_tx_dma(u32 usart); void usart_disable_tx_dma(u32 usart); +void usart_enable_rx_interrupt(u32 usart); +void usart_disable_rx_interrupt(u32 usart); +void usart_enable_tx_interrupt(u32 usart); +void usart_disable_tx_interrupt(u32 usart); +bool usart_get_flag(u32 usart, u32 flag); +bool usart_get_interrupt_source(u32 usart, u32 flag); END_DECLS diff --git a/lib/stm32/usart.c b/lib/stm32/usart.c index 2958d7c7..5cf861b5 100644 --- a/lib/stm32/usart.c +++ b/lib/stm32/usart.c @@ -353,6 +353,92 @@ void usart_disable_tx_dma(u32 usart) USART_CR3(usart) &= ~USART_CR3_DMAT; } +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_RXNEIE; +} + + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Receiver Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_rx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_RXNEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Enable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_enable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) |= USART_CR1_TXEIE; +} + +/*-----------------------------------------------------------------------------*/ +/** @brief USART Transmitter Interrupt Disable. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +*/ + +void usart_disable_tx_interrupt(u32 usart) +{ + USART_CR1(usart) &= ~USART_CR1_TXEIE; +} + + +/*---------------------------------------------------------------------------*/ +/** @brief USART Read a Status Flag. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag set. +*/ + +bool usart_get_flag(u32 usart, u32 flag) +{ + return ((USART_SR(usart) & flag) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief USART Return Interrupt Source. + +Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was +set and the interrupt was enabled. If the specified flag is not an interrupt +flag, the function returns false. + +@todo These are the most important interrupts likely to be used. Others +relating to LIN break, and error conditions in multibuffer communication, need +to be added for completeness. + +@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. +@returns boolean: flag and interrupt enable both set. +*/ + +bool usart_get_interrupt_source(u32 usart, u32 flag) +{ +u32 flag_set = (USART_SR(usart) & flag); +/* IDLE, RXNE, TC, TXE interrupts */ + if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) + return ((flag_set & USART_CR1(usart)) != 0); +/* Overrun error */ + else if (flag == USART_SR_ORE) + return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); + return (false); +} /**@}*/ From 0c779512d6db7fd513c8982059b869df0be29210 Mon Sep 17 00:00:00 2001 From: Ken Sarkies Date: Mon, 15 Oct 2012 14:34:33 +1030 Subject: [PATCH 22/35] Initial documentation for SPI, I2C and CRC (no code changes) --- include/libopencm3/stm32/crc.h | 14 ++ include/libopencm3/stm32/i2c.h | 38 +++ include/libopencm3/stm32/spi.h | 62 +++++ lib/stm32/crc.c | 46 +++- lib/stm32/i2c.c | 165 +++++++++++++ lib/stm32/spi.c | 408 ++++++++++++++++++++++++++++++++- 6 files changed, 730 insertions(+), 3 deletions(-) diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h index 3848191f..aa301824 100644 --- a/include/libopencm3/stm32/crc.h +++ b/include/libopencm3/stm32/crc.h @@ -1,3 +1,17 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F CRC Generator + +@ingroup STM32F_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 13257eba..a59c4202 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -1,3 +1,19 @@ +/** @defgroup i2c_defines I2C Defines + +@ingroup STM32F_defines + +@brief libopencm3 Defined Constants and Types for the STM32 I2C + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -23,11 +39,19 @@ #include #include +/**@{*/ + /* --- Convenience macros -------------------------------------------------- */ /* I2C register base adresses (for convenience) */ +/****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address +@ingroup i2c_defines + +@{*/ #define I2C1 I2C1_BASE #define I2C2 I2C2_BASE +/**@}*/ /* --- I2C registers ------------------------------------------------------- */ @@ -146,6 +170,11 @@ /* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ /* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */ +/****************************************************************************/ +/** @defgroup i2c_clock I2C clock frequency settings +@ingroup i2c_defines + +@{*/ #define I2C_CR2_FREQ_2MHZ 0x02 #define I2C_CR2_FREQ_3MHZ 0x03 #define I2C_CR2_FREQ_4MHZ 0x04 @@ -181,6 +210,7 @@ #define I2C_CR2_FREQ_34MHZ 0x22 #define I2C_CR2_FREQ_35MHZ 0x23 #define I2C_CR2_FREQ_36MHZ 0x24 +/**@}*/ /* --- I2Cx_OAR1 values ---------------------------------------------------- */ @@ -311,8 +341,14 @@ /* --- I2C const definitions ----------------------------------------------- */ +/****************************************************************************/ +/** @defgroup i2c_rw I2C Read/Write bit +@ingroup i2c_defines + +@{*/ #define I2C_WRITE 0 #define I2C_READ 1 +/**@}*/ /* --- I2C funtion prototypes----------------------------------------------- */ @@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data); END_DECLS #endif +/**@}*/ + diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index 11ba8206..f23df3af 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -1,3 +1,19 @@ +/** @defgroup spi_defines SPI Defines + +@ingroup STM32F_defines + +@brief libopencm3 Defined Constants and Types for the STM32 SPI + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + /* * This file is part of the libopencm3 project. * @@ -23,13 +39,21 @@ #include #include +/**@{*/ + /* Registers can be accessed as 16bit or 32bit values. */ /* --- Convenience macros -------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup spi_reg_base SPI Register base address +@ingroup spi_defines + +@{*/ #define SPI1 SPI1_BASE #define SPI2 SPI2_I2S_BASE #define SPI3 SPI3_I2S_BASE +/**@}*/ /* --- SPI registers ------------------------------------------------------- */ @@ -110,8 +134,14 @@ #define SPI_CR1_CRCNEXT (1 << 12) /* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines + +@{*/ #define SPI_CR1_DFF_8BIT (0 << 11) #define SPI_CR1_DFF_16BIT (1 << 11) +/**@}*/ #define SPI_CR1_DFF (1 << 11) /* RXONLY: Receive only */ @@ -124,13 +154,24 @@ #define SPI_CR1_SSI (1 << 8) /* LSBFIRST: Frame format */ +/****************************************************************************/ +/** @defgroup spi_lsbfirst SPI lsb/msb first +@ingroup spi_defines + +@{*/ #define SPI_CR1_MSBFIRST (0 << 7) #define SPI_CR1_LSBFIRST (1 << 7) +/**@}*/ /* SPE: SPI enable */ #define SPI_CR1_SPE (1 << 6) /* BR[2:0]: Baud rate control */ +/****************************************************************************/ +/** @defgroup spi_baudrate SPI peripheral baud rates +@ingroup spi_defines + +@{*/ #define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) @@ -139,6 +180,12 @@ #define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +/**@}*/ +/****************************************************************************/ +/** @defgroup spi_br_pre SPI peripheral baud rate prescale values +@ingroup spi_defines + +@{*/ #define SPI_CR1_BR_FPCLK_DIV_2 0x0 #define SPI_CR1_BR_FPCLK_DIV_4 0x1 #define SPI_CR1_BR_FPCLK_DIV_8 0x2 @@ -147,18 +194,31 @@ #define SPI_CR1_BR_FPCLK_DIV_64 0x5 #define SPI_CR1_BR_FPCLK_DIV_128 0x6 #define SPI_CR1_BR_FPCLK_DIV_256 0x7 +/**@}*/ /* MSTR: Master selection */ #define SPI_CR1_MSTR (1 << 2) /* CPOL: Clock polarity */ +/****************************************************************************/ +/** @defgroup spi_cpol SPI clock polarity +@ingroup spi_defines + +@{*/ #define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) #define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +/**@}*/ #define SPI_CR1_CPOL (1 << 1) /* CPHA: Clock phase */ +/****************************************************************************/ +/** @defgroup spi_cpha SPI clock phase +@ingroup spi_defines + +@{*/ #define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) #define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +/**@}*/ #define SPI_CR1_CPHA (1 << 0) /* --- SPI_CR2 values ------------------------------------------------------ */ @@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi); END_DECLS +/**@}*/ + #endif diff --git a/lib/stm32/crc.c b/lib/stm32/crc.c index bbbe1fd2..bd9e8d2b 100644 --- a/lib/stm32/crc.c +++ b/lib/stm32/crc.c @@ -1,3 +1,17 @@ +/** @defgroup crc_file CRC + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx CRC + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 15 October 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -19,11 +33,30 @@ #include +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Reset. + +Reset the CRC unit and forces the data register to all 1s. + +*/ + void crc_reset(void) { CRC_CR |= CRC_CR_RESET; } +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate. + +Writes a data word to the register, the write operation stalling until the +computation is complete. + +@param[in] data Unsigned int32. +@returns int32 Computed CRC result +*/ + u32 crc_calculate(u32 data) { CRC_DR = data; @@ -31,6 +64,16 @@ u32 crc_calculate(u32 data) return CRC_DR; } +/*-----------------------------------------------------------------------------*/ +/** @brief CRC Calculate of a Block of Data. + +Writes data words consecutively to the register, the write operation stalling +until the computation of each word is complete. + +@param[in] datap Unsigned int32. pointer to an array of 32 bit data words. +@returns int32 Final computed CRC result +*/ + u32 crc_calculate_block(u32 *datap, int size) { int i; @@ -39,6 +82,5 @@ u32 crc_calculate_block(u32 *datap, int size) } return CRC_DR; } - - +/**@}*/ diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c index 87d90619..e1d3a095 100644 --- a/lib/stm32/i2c.c +++ b/lib/stm32/i2c.c @@ -1,3 +1,28 @@ +/** @defgroup i2c_file I2C + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx I2C + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to two I2C peripherals. The peripherals support SMBus and +PMBus variants. + +A peripheral begins after reset in Slave mode. To become a Master a start +condition must be generated. The peripheral will remain in Master mode unless +a multimaster contention is lost or a stop condition is generated. + +@todo all sorts of lovely stuff like DMA, Interrupts, SMBus variant, Status +register access, Error conditions + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +45,17 @@ #include #include +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Reset. + +The I2C peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. +*/ + void i2c_reset(u32 i2c) { switch (i2c) { @@ -34,26 +70,69 @@ void i2c_reset(u32 i2c) } } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Enable. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_peripheral_enable(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_PE; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Peripheral Disable. + +This must not be reset while in Master mode until a communication has finished. +In Slave mode, the peripheral is disabled only after communication has ended. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_peripheral_disable(u32 i2c) { I2C_CR1(i2c) &= ~I2C_CR1_PE; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Start Condition. + +If in Master mode this will cause a restart condition to occur at the end of the +current transmission. If in Slave mode, this will initiate a start condition +when the current bus activity is completed. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_send_start(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_START; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Stop Condition. + +After the current byte transfer this will initiate a stop condition if in Master +mode, or simply release the bus if in Slave mode. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_send_stop(u32 i2c) { I2C_CR1(i2c) |= I2C_CR1_STOP; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 7 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 7 bit form. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int8. Slave address 0...127. +*/ + void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) { I2C_OAR1(i2c) = (u16)(slave << 1); @@ -61,21 +140,61 @@ void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the 10 bit Slave Address for the Peripheral. + +This sets an address for Slave mode operation, in 10 bit form. + +@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +*/ + void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) { I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Fast Mode. + +Set the clock frequency to the high clock rate mode (up to 400kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_set_fast_mode(u32 i2c) { I2C_CCR(i2c) |= I2C_CCR_FS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Standard Mode. + +Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual +clock frequency must be set with @ref i2c_set_clock_frequency + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +*/ + void i2c_set_standard_mode(u32 i2c) { I2C_CCR(i2c) &= ~I2C_CCR_FS; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Peripheral Clock Frequency. + +Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that +this is not the I2C bus clock. This is set in conjunction with the Clock +Control register to generate the Master bus clock, see @ref i2c_set_ccr + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. +*/ + void i2c_set_clock_frequency(u32 i2c, u8 freq) { u16 reg16; @@ -84,6 +203,21 @@ void i2c_set_clock_frequency(u32 i2c, u8 freq) I2C_CR2(i2c) = reg16; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set Bus Clock Frequency. + +Set the bus clock frequency. This is a 12 bit number (0...4095) calculated +from the formulae given in the STM32F1 reference manual in the description +of the CCR field. It is a divisor of the peripheral clock frequency +@ref i2c_set_clock_frequency modified by the fast mode setting +@ref i2c_set_fast_mode + +@todo provide additional API assitance to set the clock, eg macros + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095. +*/ + void i2c_set_ccr(u32 i2c, u16 freq) { u16 reg16; @@ -92,17 +226,48 @@ void i2c_set_ccr(u32 i2c, u16 freq) I2C_CCR(i2c) = reg16; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Set the Rise Time. + +Set the maximum rise time on the bus according to the I2C specification, as 1 +more than the specified rise time in peripheral clock cycles. This is a 6 bit +number. + +@todo provide additional APIP assistance. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] trise Unsigned int16. Rise Time Setting 0...63. +*/ + void i2c_set_trise(u32 i2c, u16 trise) { I2C_TRISE(i2c) = trise; } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send the 7-bit Slave Address. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] slave Unsigned int16. Slave address 0...1023. +@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. +*/ + void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) { I2C_DR(i2c) = (u8)((slave << 1) | readwrite); } +/*-----------------------------------------------------------------------------*/ +/** @brief I2C Send Data. + +@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. +@param[in] data Unsigned int8. Byte to send. +*/ + void i2c_send_data(u32 i2c, u8 data) { I2C_DR(i2c) = data; } + +/**@}*/ + diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c index 828e1238..90675b30 100644 --- a/lib/stm32/spi.c +++ b/lib/stm32/spi.c @@ -1,3 +1,43 @@ +/** @defgroup spi_file SPI + +@ingroup STM32F_files + +@brief libopencm3 STM32Fxxx SPI + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 15 October 2012 + +Devices can have up to three SPI peripherals. The common 4-wire full-duplex +mode of operation is supported, along with 3-wire variants using unidirectional +communication modes or half-duplex bidirectional communication. A variety of +options allows many of the SPI variants to be supported. Multimaster operation +is also supported. A CRC can be generated and checked in hardware. + +@note Some JTAG pins need to be remapped if SPI is to be used. + +@note The I2S protocol shares the SPI hardware so the two protocols cannot be +used at the same time on the same peripheral. + +Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, +LSB first. +@code + spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + SPI_CR1_LSBFIRST); + spi_write(SPI1, 0x55); // 8-bit write + spi_write(SPI1, 0xaa88); // 16-bit write + reg8 = spi_read(SPI1); // 8-bit read + reg16 = spi_read(SPI1); // 16-bit read +@endcode + +@todo need additional functions to aid ISRs in retrieving status + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -41,6 +81,17 @@ * reg16 = spi_read(SPI1); // 16-bit read */ +/**@{*/ + +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Reset. + +The SPI peripheral and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. + +@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_reset(u32 spi_peripheral) { switch (spi_peripheral) { @@ -59,6 +110,25 @@ void spi_reset(u32 spi_peripheral) } } +/*-----------------------------------------------------------------------------*/ +/** @brief Configure the SPI as Master. + +The SPI peripheral is configured as a master with communication parameters +baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity +and phase. The SPI enable, CRC enable and CRC next controls are not affected. +These must be controlled separately. + +@todo NSS pin handling. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. +@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. +@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. +@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. +@returns int. Error code. +*/ + int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) { u32 reg32 = SPI_CR1(spi); @@ -82,28 +152,66 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) } /* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable. + +The SPI peripheral is enabled. + +@todo Error handling? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */ } /* TODO: Error handling? */ +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable. + +The SPI peripheral is disabled. + +@todo Follow procedure from section 23.3.8 in the TRM. +(possibly create a "clean disable" function separately) + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable(u32 spi) { u32 reg32; - /* TODO: Follow procedure from section 23.3.8 in the TRM. */ reg32 = SPI_CR1(spi); reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */ SPI_CR1(spi) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write. + +Data is written to the SPI interface. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + void spi_write(u32 spi, u16 data) { /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write with Blocking. + +Data is written to the SPI interface after the previous write transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +*/ + void spi_send(u32 spi, u16 data) { /* Wait for transfer finished. */ @@ -114,6 +222,15 @@ void spi_send(u32 spi, u16 data) SPI_DR(spi) = data; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Read. + +Data is read from the SPI interface after the incoming transfer has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + u16 spi_read(u32 spi) { /* Wait for transfer finished. */ @@ -124,6 +241,17 @@ u16 spi_read(u32 spi) return SPI_DR(spi); } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Data Write and Read Exchange. + +Data is written to the SPI interface, then a read is done after the incoming transfer +has finished. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] data Unsigned int16. 8 or 16 bit data to be written. +@returns data Unsigned int16. 8 or 16 bit data. +*/ + u16 spi_xfer(u32 spi, u16 data) { spi_write(spi, data); @@ -136,98 +264,251 @@ u16 spi_xfer(u32 spi, u16 data) return SPI_DR(spi); } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Unidirectional Mode. + +The SPI peripheral is set for unidirectional transfers. This is used in full duplex +mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a +unidirectional data wire. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_unidirectional_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a receive state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_receive_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Bidirectional Simplex Receive Only Mode. + +The SPI peripheral is set for bidirectional transfers in two-wire simplex mode +(using a clock wire and a bidirectional data wire), and is placed in a transmit state. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_bidirectional_transmit_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_BIDIMODE; SPI_CR1(spi) |= SPI_CR1_BIDIOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the CRC. + +The SPI peripheral is set to use a CRC field for transmit and receive. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_crc(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CRCEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the CRC. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_crc(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a Data Word + +The next transmission to take place is a data word from the transmit buffer. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_next_tx_from_buffer(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Next Transmit is a CRC Word + +The next transmission to take place is a crc word from the hardware crc unit. +This must be called before transmission to distinguish between sending +of a data or CRC word. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_next_tx_from_crc(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CRCNEXT; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 8 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_dff_8bit(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_DFF; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 16 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_dff_16bit(u32 spi) { SPI_CR1(spi) |= SPI_CR1_DFF; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Full Duplex (3-wire) Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_full_duplex_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_RXONLY; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_receive_only_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_RXONLY; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Hardware + +In slave mode the NSS hardware input is used as a select enable for the slave. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_software_slave_management(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_SSM; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Slave Management by Software + +In slave mode the NSS hardware input is replaced by an internal software +enable/disable of the slave (@ref spi_set_nss_high). + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_software_slave_management(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SSM; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal High + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select enable signal. + +@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_nss_high(u32 spi) { SPI_CR1(spi) |= SPI_CR1_SSI; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Software NSS Signal Low + +In slave mode, and only when software slave management is used, this replaces +the NSS signal with a slave select disable signal. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_nss_low(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_SSI; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send LSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_send_lsb_first(u32 spi) { SPI_CR1(spi) |= SPI_CR1_LSBFIRST; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Send MSB First + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_send_msb_first(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Baudrate Prescaler + +@todo Why is this specification different to the spi_init_master baudrate values? + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. +*/ + void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) { u32 reg32; @@ -240,92 +521,217 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) SPI_CR1(spi) = reg32; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Master Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_master_mode(u32 spi) { SPI_CR1(spi) |= SPI_CR1_MSTR; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set to Slave Mode + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_slave_mode(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_MSTR; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to High when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_polarity_1(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CPOL; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Polarity to Low when Idle + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_polarity_0(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CPOL; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Trailing Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_phase_1(u32 spi) { SPI_CR1(spi) |= SPI_CR1_CPHA; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the Clock Phase to Capture on Leading Edge + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_set_clock_phase_0(u32 spi) { SPI_CR1(spi) &= ~SPI_CR1_CPHA; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_tx_buffer_empty_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_TXEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Transmit Buffer Empty Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_tx_buffer_empty_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_TXEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_RXNEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Receive Buffer Ready Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_error_interrupt(u32 spi) { SPI_CR2(spi) |= SPI_CR2_ERRIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable the Error Interrupt + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_error_interrupt(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_ERRIE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Output + +Normally used in master mode to allows the master to place all devices on the +SPI bus into slave mode. Multimaster mode is not possible. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_ss_output(u32 spi) { SPI_CR2(spi) |= SPI_CR2_SSOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Set the NSS Pin as an Input + +In master mode this allows the master to sense the presence of other masters. If +NSS is then pulled low the master is placed into slave mode. In slave mode NSS +becomes a slave enable. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_ss_output(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_SSOE; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Transmit Transfers via DMA + +This allows transmissions to proceed unattended using DMA to move data to the +transmit buffer as it becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_tx_dma(u32 spi) { SPI_CR2(spi) |= SPI_CR2_TXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Transmit Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_tx_dma(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Enable Receive Transfers via DMA + +This allows received data streams to proceed unattended using DMA to move data from +the receive buffer as data becomes available. The DMA channels provided for each +SPI peripheral are given in the Technical Manual DMA section. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_enable_rx_dma(u32 spi) { SPI_CR2(spi) |= SPI_CR2_RXDMAEN; } +/*-----------------------------------------------------------------------------*/ +/** @brief SPI Disable Receive Transfers via DMA + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + void spi_disable_rx_dma(u32 spi) { SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN; } + +/**@}*/ From b7ebe6e705b42030a4a6ff0002b7542464917e38 Mon Sep 17 00:00:00 2001 From: Felix Ruess Date: Sat, 13 Oct 2012 15:35:19 +0200 Subject: [PATCH 23/35] fix clean target for example makefiles if the compiler is not in PATH --- Makefile | 2 +- examples/lm3s/Makefile.include | 6 +++++- examples/lpc13xx/Makefile.include | 6 +++++- examples/lpc17xx/Makefile.include | 6 +++++- examples/lpc43xx/Makefile.include | 6 +++++- examples/stm32/f1/Makefile.include | 8 ++++++-- examples/stm32/f2/Makefile.include | 6 +++++- examples/stm32/f4/Makefile.include | 6 +++++- 8 files changed, 37 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 37c0c404..492b618e 100644 --- a/Makefile +++ b/Makefile @@ -26,7 +26,7 @@ SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install SRCLIBDIR = $(shell pwd)/lib -TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s +TARGETS = stm32/f1 stm32/f2 stm32/f4 lpc13xx lpc17xx lpc43xx lm3s # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/examples/lm3s/Makefile.include b/examples/lm3s/Makefile.include index 0e18bd62..f5190638 100644 --- a/examples/lm3s/Makefile.include +++ b/examples/lm3s/Makefile.include @@ -24,14 +24,18 @@ CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump + +TOOLCHAIN_DIR ?= ../../../.. ifeq ($(wildcard ../../../../lib/libopencm3_lm3s.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../.. endif + CFLAGS += -O0 -g3 -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld diff --git a/examples/lpc13xx/Makefile.include b/examples/lpc13xx/Makefile.include index cc668f89..d8aeff09 100644 --- a/examples/lpc13xx/Makefile.include +++ b/examples/lpc13xx/Makefile.include @@ -24,14 +24,18 @@ CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump + +TOOLCHAIN_DIR ?= ../../../.. ifeq ($(wildcard ../../../../lib/libopencm3_lpc13xx.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../.. endif + CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld diff --git a/examples/lpc17xx/Makefile.include b/examples/lpc17xx/Makefile.include index 66688d32..6d7bbfe5 100644 --- a/examples/lpc17xx/Makefile.include +++ b/examples/lpc17xx/Makefile.include @@ -24,14 +24,18 @@ CC = $(PREFIX)-gcc LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump + +TOOLCHAIN_DIR ?= ../../../.. ifeq ($(wildcard ../../../../lib/libopencm3_lpc17xx.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../.. endif + CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m3 -mthumb -MD LDSCRIPT ?= $(BINARY).ld diff --git a/examples/lpc43xx/Makefile.include b/examples/lpc43xx/Makefile.include index 4b1a092f..15e523b4 100644 --- a/examples/lpc43xx/Makefile.include +++ b/examples/lpc43xx/Makefile.include @@ -27,14 +27,18 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb + +TOOLCHAIN_DIR ?= ../../../.. ifeq ($(wildcard ../../../../lib/libopencm3_lpc43xx.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../.. endif + CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \ -mcpu=cortex-m4 -mthumb -MD \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 diff --git a/examples/stm32/f1/Makefile.include b/examples/stm32/f1/Makefile.include index 60f44e7e..6b87b982 100644 --- a/examples/stm32/f1/Makefile.include +++ b/examples/stm32/f1/Makefile.include @@ -25,14 +25,18 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb + +TOOLCHAIN_DIR ?= ../../../../.. ifeq ($(wildcard ../../../../../lib/libopencm3_stm32f1.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) -$(info We seem to be building the example in the source directory. Using local library!) +$(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../../.. endif + ARCH_FLAGS = -mthumb -mcpu=cortex-m3 -msoft-float CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common $(ARCH_FLAGS) -MD -DSTM32F1 diff --git a/examples/stm32/f2/Makefile.include b/examples/stm32/f2/Makefile.include index 690f8c4a..10eed796 100644 --- a/examples/stm32/f2/Makefile.include +++ b/examples/stm32/f2/Makefile.include @@ -26,14 +26,18 @@ LD = $(PREFIX)-gcc OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb + +TOOLCHAIN_DIR ?= ../../../../.. ifeq ($(wildcard ../../../../../lib/libopencm3_stm32f2.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../../.. endif + CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common -mcpu=cortex-m3 -mthumb -msoft-float -MD -DSTM32F2 LDSCRIPT ?= $(BINARY).ld diff --git a/examples/stm32/f4/Makefile.include b/examples/stm32/f4/Makefile.include index f436bc8e..815f3759 100644 --- a/examples/stm32/f4/Makefile.include +++ b/examples/stm32/f4/Makefile.include @@ -27,14 +27,18 @@ OBJCOPY = $(PREFIX)-objcopy OBJDUMP = $(PREFIX)-objdump GDB = $(PREFIX)-gdb FLASH = $(shell which st-flash) + +TOOLCHAIN_DIR ?= ../../../../.. ifeq ($(wildcard ../../../../../lib/libopencm3_stm32f4.a),) +ifneq ($(strip $(shell which $(CC))),) TOOLCHAIN_DIR := $(shell dirname `which $(CC)`)/../$(PREFIX) +endif else ifeq ($(V),1) $(info We seem to be building the example in the source directory. Using local library!) endif -TOOLCHAIN_DIR := ../../../../.. endif + CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include \ -fno-common -mcpu=cortex-m4 -mthumb \ -mfloat-abi=hard -mfpu=fpv4-sp-d16 -MD -DSTM32F4 From 0a483449654e18189ff017f70d6b97888cdba382 Mon Sep 17 00:00:00 2001 From: Felix Ruess Date: Sat, 13 Oct 2012 15:47:06 +0200 Subject: [PATCH 24/35] add the copied ld scripts in lib dir to gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index d5fb0657..8625d7d3 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,7 @@ *.srec *.a *.elf +lib/*.ld *.swp \#* .\#* From 837de3ff9771ea03b5b54dda8ba7f77d404bdcdf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 10:27:51 +0200 Subject: [PATCH 25/35] nvic.h factored out (incomplete) --- include/libopencm3/cm3/nvic.h | 123 +++++++++++++++++++++++++++++ include/libopencm3/lpc43xx/nvic.h | 85 -------------------- include/libopencm3/stm32/nvic.h | 124 ------------------------------ 3 files changed, 123 insertions(+), 209 deletions(-) create mode 100644 include/libopencm3/cm3/nvic.h diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h new file mode 100644 index 00000000..3a3aa2f4 --- /dev/null +++ b/include/libopencm3/cm3/nvic.h @@ -0,0 +1,123 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_nvic_defines NVIC Defines + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@ingroup CM3_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/**@{*/ + +#ifndef LIBOPENCM3_NVIC_H +#define LIBOPENCM3_NVIC_H + +#include +#include + +/* --- NVIC Registers ------------------------------------------------------ */ + +/* ISER: Interrupt Set Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) + +/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ + +/* ICER: Interrupt Clear Enable Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) + +/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ + +/* ISPR: Interrupt Set Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) + +/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ + +/* ICPR: Interrupt Clear Pending Registers */ +/* Note: 8 32bit Registers */ +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) + +/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ + +/* IABR: Interrupt Active Bit Register */ +/* Note: 8 32bit Registers */ +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) + +/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ + +/* IPR: Interrupt Priority Registers */ +/* Note: 240 8bit Registers */ +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) + +/* STIR: Software Trigger Interrupt Register */ +#define NVIC_STIR MMIO32(STIR_BASE) + +/* --- IRQ channel numbers-------------------------------------------------- */ + +/* Cortex M3 and M4 System Interrupts */ +/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts +@ingroup CM3_nvic_defines + +IRQ numbers -3 and -6 to -9 are reserved +@{*/ +#define NVIC_NMI_IRQ -14 +#define NVIC_HARD_FAULT_IRQ -13 +#define NVIC_MEM_MANAGE_IRQ -12 +#define NVIC_BUS_FAULT_IRQ -11 +#define NVIC_USAGE_FAULT_IRQ -10 +/* irq numbers -6 to -9 are reserved */ +#define NVIC_SV_CALL_IRQ -5 +#define DEBUG_MONITOR_IRQ -4 +/* irq number -3 reserved */ +#define NVIC_PENDSV_IRQ -2 +#define NVIC_SYSTICK_IRQ -1 +/**@}*/ + +/* Note: User interrupts are family specific and are defined in a family + * specific header file in the corresponding subfolder. + */ + +/* --- NVIC functions ------------------------------------------------------ */ + +BEGIN_DECLS + +void nvic_enable_irq(u8 irqn); +void nvic_disable_irq(u8 irqn); +u8 nvic_get_pending_irq(u8 irqn); +void nvic_set_pending_irq(u8 irqn); +void nvic_clear_pending_irq(u8 irqn); +u8 nvic_get_active_irq(u8 irqn); +u8 nvic_get_irq_enabled(u8 irqn); +void nvic_set_priority(u8 irqn, u8 priority); +void nvic_generate_software_interrupt(u16 irqn); + +END_DECLS + +#endif diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index cdbf0702..597e21a5 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -1,70 +1,3 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LPC43XX_NVIC_H -#define LPC43XX_NVIC_H - -#include -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M4 System Interrupts */ @@ -131,21 +64,3 @@ /* LPC43xx M0 specific user interrupts */ //TODO - -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u8 irqn); - -END_DECLS - -#endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h index 694fab88..b8c22a29 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/stm32/nvic.h @@ -1,108 +1,3 @@ -/** @defgroup STM32F_nvic_defines NVIC Defines - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@ingroup STM32F_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -/**@{*/ - -#ifndef LIBOPENCM3_NVIC_H -#define LIBOPENCM3_NVIC_H - -#include -#include - -/* --- NVIC Registers ------------------------------------------------------ */ - -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) - -/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ - -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) - -/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ - -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) - -/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ - -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) - -/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ - -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) - -/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ - -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) - -/* STIR: Software Trigger Interrupt Register */ -#define NVIC_STIR MMIO32(STIR_BASE) - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M3 System Interrupts */ -/** @defgroup nvic_sysint Cortex M3 System Interrupts -@ingroup STM32F_nvic_defines - -IRQ numbers -3 and -6 to -9 are reserved -@{*/ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 -/**@}*/ - - -/* Note: User interrupts are family specific and are defined in a family - * specific header file in the corresponding subfolder. - */ - #if defined(STM32F1) # include #elif defined(STM32F2) @@ -114,22 +9,3 @@ IRQ numbers -3 and -6 to -9 are reserved #endif -/* --- NVIC functions ------------------------------------------------------ */ - -BEGIN_DECLS - -void nvic_enable_irq(u8 irqn); -void nvic_disable_irq(u8 irqn); -u8 nvic_get_pending_irq(u8 irqn); -void nvic_set_pending_irq(u8 irqn); -void nvic_clear_pending_irq(u8 irqn); -u8 nvic_get_active_irq(u8 irqn); -u8 nvic_get_irq_enabled(u8 irqn); -void nvic_set_priority(u8 irqn, u8 priority); -void nvic_generate_software_interrupt(u16 irqn); - -END_DECLS - -#endif -/**@}*/ - From a7f5f9f576977f97988b739fd98ff7f164edf156 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:26:41 +0200 Subject: [PATCH 26/35] merge irq and nvic code using a script --- include/libopencm3/efm32/tinygecko/Makefile | 2 + include/libopencm3/efm32/tinygecko/irq.h | 130 ------------------ include/libopencm3/efm32/tinygecko/irq.yaml | 28 ++++ include/libopencm3/efm32/tinygecko/irq2nvic_h | 92 +++++++++++++ 4 files changed, 122 insertions(+), 130 deletions(-) create mode 100644 include/libopencm3/efm32/tinygecko/Makefile delete mode 100644 include/libopencm3/efm32/tinygecko/irq.h create mode 100644 include/libopencm3/efm32/tinygecko/irq.yaml create mode 100755 include/libopencm3/efm32/tinygecko/irq2nvic_h diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile new file mode 100644 index 00000000..4ac53477 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/Makefile @@ -0,0 +1,2 @@ +nvic.h: irq.yaml + ./irq2nvic_h diff --git a/include/libopencm3/efm32/tinygecko/irq.h b/include/libopencm3/efm32/tinygecko/irq.h deleted file mode 100644 index f5263aee..00000000 --- a/include/libopencm3/efm32/tinygecko/irq.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/** @file - * - * Definitions of interrupt names on EFM32 Tiny Gecko systems - * - * The names and numbers are taken from d0034_efm32tg_reference_manual.pdf table 4.1. - */ - -#ifndef LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H -#define LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H - -#define IRQ_DMA 0 -#define IRQ_GPIO_EVEN 1 -#define IRQ_TIMER0 2 -#define IRQ_USART0_RX 3 -#define IRQ_USART0_TX 4 -#define IRQ_ACMP01 5 -#define IRQ_ADC0 6 -#define IRQ_DAC0 7 -#define IRQ_I2C0 8 -#define IRQ_GPIO_ODD 9 -#define IRQ_TIMER1 10 -#define IRQ_USART1_RX 11 -#define IRQ_USART1_TX 12 -#define IRQ_LESENSE 13 -#define IRQ_LEUART0 14 -#define IRQ_LETIMER0 15 -#define IRQ_PCNT0 16 -#define IRQ_RTC 17 -#define IRQ_CMU 18 -#define IRQ_VCMP 19 -#define IRQ_LCD 20 -#define IRQ_MSC 21 -#define IRQ_AES 22 -#define IRQ_COUNT 23 /**< See also d0002_efm32_cortex-m3_reference_manual.pdf's table 1.1's "number of interrupts" line, which shows that there are really no more interrupts and it is sufficient to allocate only 23 slots. */ - -#define WEAK __attribute__ ((weak)) - -void WEAK dma_isr(void); -void WEAK gpio_even_isr(void); -void WEAK timer0_isr(void); -void WEAK usart0_rx_isr(void); -void WEAK usart0_tx_isr(void); -void WEAK acmp01_isr(void); -void WEAK adc0_isr(void); -void WEAK dac0_isr(void); -void WEAK i2c0_isr(void); -void WEAK gpio_odd_isr(void); -void WEAK timer1_isr(void); -void WEAK usart1_rx_isr(void); -void WEAK usart1_tx_isr(void); -void WEAK lesense_isr(void); -void WEAK leuart0_isr(void); -void WEAK letimer0_isr(void); -void WEAK pcnt0_isr(void); -void WEAK rtc_isr(void); -void WEAK cmu_isr(void); -void WEAK vcmp_isr(void); -void WEAK lcd_isr(void); -void WEAK msc_isr(void); -void WEAK aes_isr(void); - -#pragma weak dma_isr = blocking_handler -#pragma weak gpio_even_isr = blocking_handler -#pragma weak timer0_isr = blocking_handler -#pragma weak usart0_rx_isr = blocking_handler -#pragma weak usart0_tx_isr = blocking_handler -#pragma weak acmp01_isr = blocking_handler -#pragma weak adc0_isr = blocking_handler -#pragma weak dac0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak gpio_odd_isr = blocking_handler -#pragma weak timer1_isr = blocking_handler -#pragma weak usart1_rx_isr = blocking_handler -#pragma weak usart1_tx_isr = blocking_handler -#pragma weak lesense_isr = blocking_handler -#pragma weak leuart0_isr = blocking_handler -#pragma weak letimer0_isr = blocking_handler -#pragma weak pcnt0_isr = blocking_handler -#pragma weak rtc_isr = blocking_handler -#pragma weak cmu_isr = blocking_handler -#pragma weak vcmp_isr = blocking_handler -#pragma weak lcd_isr = blocking_handler -#pragma weak msc_isr = blocking_handler -#pragma weak aes_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_DMA] = dma_isr, \ - [IRQ_GPIO_EVEN] = gpio_even_isr, \ - [IRQ_TIMER0] = timer0_isr, \ - [IRQ_USART0_RX] = usart0_rx_isr, \ - [IRQ_USART0_TX] = usart0_tx_isr, \ - [IRQ_ACMP01] = acmp01_isr, \ - [IRQ_ADC0] = adc0_isr, \ - [IRQ_DAC0] = dac0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_GPIO_ODD] = gpio_odd_isr, \ - [IRQ_TIMER1] = timer1_isr, \ - [IRQ_USART1_RX] = usart1_rx_isr, \ - [IRQ_USART1_TX] = usart1_tx_isr, \ - [IRQ_LESENSE] = lesense_isr, \ - [IRQ_LEUART0] = leuart0_isr, \ - [IRQ_LETIMER0] = letimer0_isr, \ - [IRQ_PCNT0] = pcnt0_isr, \ - [IRQ_RTC] = rtc_isr, \ - [IRQ_CMU] = cmu_isr, \ - [IRQ_VCMP] = vcmp_isr, \ - [IRQ_LCD] = lcd_isr, \ - [IRQ_MSC] = msc_isr, \ - [IRQ_AES] = aes_isr, - -#endif diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml new file mode 100644 index 00000000..16fa69c5 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -0,0 +1,28 @@ +includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +partname_humanreadable: EFM32 Tiny Gecko series +partname_doxygen: EFM32TG +# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. +irqs: + - dma + - gpio_even + - timer0 + - usart0_rx + - usart0_tx + - acmp01 + - adc0 + - dac0 + - i2c0 + - gpio_odd + - timer1 + - usart1_rx + - usart1_tx + - lesense + - leuart0 + - letimer0 + - pcnt0 + - rtc + - cmu + - vcmp + - lcd + - msc + - aes diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/include/libopencm3/efm32/tinygecko/irq2nvic_h new file mode 100755 index 00000000..a7df16e6 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/irq2nvic_h @@ -0,0 +1,92 @@ +#!/usr/bin/env python + +# This file is part of the libopencm3 project. +# +# Copyright (C) 2012 chrysn +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see . + +import sys +import yaml + +template = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + */ + +#ifndef {includeguard} +#define {includeguard} + +/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} + @ingroup CM3_nvic_defines + + @{{*/ + +{irqdefinitions} + +#define NVIC_IRQ_COUNT {irqcount} + +/**@}}*/ + +#define WEAK __attribute__ ((weak)) + +/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} + @ingroup CM3_nvic_isrprototypes + + @{{*/ + +{isrprototypes} + +/**@}}*/ + +/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} + @ingroup CM3_nvic_isrpragmas + + @{{*/ + +{isrpragmas} + +/**@}}*/ + +/* Initialization template for the interrupt vector table. This definition is + * used by the startup code generator (vector.c) to set the initial values for + * the interrupt handling routines to the chip family specific _isr weak + * symbols. */ + +#define IRQ_HANDLERS \\ + {vectortableinitialization} + +#endif /* {includeguard} */ +''' + +def convert(infile, outfile): + data = yaml.load(infile) + + irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) + irqnames = [v for (k,v) in irq2name] + + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) + data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? + data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) + data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) + data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) + + outfile.write(template.format(**data)) + +def main(): + convert(open('irq.yaml'), open('nvic.h', 'w')) + +if __name__ == "__main__": + main() From f705d1cd6ec77f6610046c3d9a009c263b526f25 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 12:46:30 +0200 Subject: [PATCH 27/35] dispatch for chip specific nvic --- include/libopencm3/cm3/nvic.h | 2 ++ include/libopencm3/cm3/vector.h | 5 ++--- include/libopencm3/{stm32 => dispatch}/nvic.h | 11 ++++++++--- 3 files changed, 12 insertions(+), 6 deletions(-) rename include/libopencm3/{stm32 => dispatch}/nvic.h (56%) diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 3a3aa2f4..3f832856 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -104,6 +104,8 @@ IRQ numbers -3 and -6 to -9 are reserved * specific header file in the corresponding subfolder. */ +#include + /* --- NVIC functions ------------------------------------------------------ */ BEGIN_DECLS diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index 198992b0..f78e9d84 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -38,8 +38,7 @@ #define LIBOPENCM3_VECTOR_H #include - -// #include "irq.h" /* we'll nede some definitions */ +#include /** Type of an interrupt function. Only used to avoid hard-to-read function * pointers in the efm32_vector_table_t struct. */ @@ -59,7 +58,7 @@ typedef struct { vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; - vector_table_entry_t irq[IRQ_COUNT]; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; } vector_table_t; #endif diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/dispatch/nvic.h similarity index 56% rename from include/libopencm3/stm32/nvic.h rename to include/libopencm3/dispatch/nvic.h index b8c22a29..322ec29f 100644 --- a/include/libopencm3/stm32/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -4,8 +4,13 @@ # include #elif defined(STM32F4) # include + +#elif defined(TINYGECKO) +# include + +#elif defined(LPC43XX) +# include + #else -# error "stm32 family not defined." +# error "no chipset defined." #endif - - From a8a6eb39e9dfa25a9934298c6321b912337c0621 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:19:55 +0200 Subject: [PATCH 28/35] add irq cound to existing nvic.h files --- include/libopencm3/lpc43xx/nvic.h | 2 ++ include/libopencm3/stm32/f1/nvic_f1.h | 2 ++ include/libopencm3/stm32/f2/nvic_f2.h | 2 ++ include/libopencm3/stm32/f4/nvic_f4.h | 2 ++ 4 files changed, 8 insertions(+) diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h index 597e21a5..0fc5cc67 100644 --- a/include/libopencm3/lpc43xx/nvic.h +++ b/include/libopencm3/lpc43xx/nvic.h @@ -62,5 +62,7 @@ #define NVIC_M4_C_CAN0_IRQ 51 #define NVIC_M4_QEI_IRQ 52 +#define NVIC_IRQ_COUNT 53 + /* LPC43xx M0 specific user interrupts */ //TODO diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h index 5223bb6b..1544e4fc 100644 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ b/include/libopencm3/stm32/f1/nvic_f1.h @@ -109,6 +109,8 @@ LGPL License Terms @ref lgpl_license #define NVIC_CAN2_RX1_IRQ 65 #define NVIC_CAN2_SCE_IRQ 66 #define NVIC_OTG_FS_IRQ 67 + +#define NVIC_IRQ_COUNT 68 /**@}*/ #endif diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h index 2bf29971..65a990db 100644 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ b/include/libopencm3/stm32/f2/nvic_f2.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h index 91b6c251..013e3b5d 100644 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ b/include/libopencm3/stm32/f4/nvic_f4.h @@ -109,4 +109,6 @@ #define NVIC_CRYP_IRQ 79 #define NVIC_HASH_RNG_IRQ 80 +#define NVIC_IRQ_COUNT 81 + #endif From 9c13299f25c617974e7851283b51fbb0307d3e1c Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:20:56 +0200 Subject: [PATCH 29/35] unified nvic.c --- lib/{stm32 => cm3}/nvic.c | 62 ++++++++++++++++++-------------- lib/lpc43xx/nvic.c | 76 --------------------------------------- 2 files changed, 36 insertions(+), 102 deletions(-) rename lib/{stm32 => cm3}/nvic.c (85%) delete mode 100644 lib/lpc43xx/nvic.c diff --git a/lib/stm32/nvic.c b/lib/cm3/nvic.c similarity index 85% rename from lib/stm32/nvic.c rename to lib/cm3/nvic.c index 84fa6749..db187b36 100644 --- a/lib/stm32/nvic.c +++ b/lib/cm3/nvic.c @@ -1,31 +1,9 @@ -/** @defgroup STM32F_nvic_file NVIC - -@ingroup STM32F_files - -@brief libopencm3 STM32F Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Fergus Noble - -@date 18 August 2012 - -The STM32F series provides up to 68 maskable user interrupts for the STM32F10x -series, and 87 for the STM32F2xx and STM32F4xx series. - -The NVIC registers are defined by the ARM standards but the STM32F series have some -additional limitations -@see Cortex-M3 Devices Generic User Guide -@see STM32F10xxx Cortex-M3 programming manual - -LGPL License Terms @ref lgpl_license -*/ /* * This file is part of the libopencm3 project. * * Copyright (C) 2010 Thomas Otto * Copyright (C) 2012 Fergus Noble + * Copyright (C) 2012 Benjamin Vernoux * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -40,10 +18,32 @@ LGPL License Terms @ref lgpl_license * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ +/** @defgroup CM3_nvic_file NVIC +@ingroup CM3_files + +@brief libopencm3 Cortex Nested Vectored Interrupt Controller + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto +@author @htmlonly © @endhtmlonly 2012 Fergus Noble + +@date 18 August 2012 + +Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, +systicks etc.) and varying numbers of implementation defined interrupts +(typically peripherial interrupts and DMA). + +@see Cortex-M3 Devices Generic User Guide +@see STM32F10xxx Cortex-M3 programming manual + +LGPL License Terms @ref lgpl_license +*/ /**@{*/ -#include +#include +#include /*-----------------------------------------------------------------------------*/ /** @brief NVIC Enable Interrupt @@ -153,7 +153,18 @@ Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping. void nvic_set_priority(u8 irqn, u8 priority) { - NVIC_IPR(irqn) = priority; + /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the + * negative interrupt numbers assigned to the system interrupts. better + * handling would mean signed integers. */ + if(irqn>=NVIC_IRQ_COUNT) + { + /* Cortex-M system interrupts */ + SCS_SHPR( (irqn&0xF)-4 ) = priority; + }else + { + /* Device specific interrupts */ + NVIC_IPR(irqn) = priority; + } } /*-----------------------------------------------------------------------------*/ @@ -171,4 +182,3 @@ void nvic_generate_software_interrupt(u16 irqn) NVIC_STIR |= irqn; } /**@}*/ - diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c deleted file mode 100644 index 47933127..00000000 --- a/lib/lpc43xx/nvic.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Thomas Otto - * Copyright (C) 2012 Fergus Noble - * Copyright (C) 2012 Benjamin Vernoux - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ -#include -#include - -void nvic_enable_irq(u8 irqn) -{ - NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); -} - -void nvic_disable_irq(u8 irqn) -{ - NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); -} - -u8 nvic_get_pending_irq(u8 irqn) -{ - return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -void nvic_set_pending_irq(u8 irqn) -{ - NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); -} - -void nvic_clear_pending_irq(u8 irqn) -{ - NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); -} - -u8 nvic_get_active_irq(u8 irqn) -{ - return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -u8 nvic_get_irq_enabled(u8 irqn) -{ - return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} - -void nvic_set_priority(u8 irqn, u8 priority) -{ - if(irqn>NVIC_M4_QEI_IRQ) - { - /* Cortex-M system interrupts */ - SCS_SHPR( (irqn&0xF)-4 ) = priority; - }else - { - /* Device specific interrupts */ - NVIC_IPR(irqn) = priority; - } -} - -void nvic_generate_software_interrupt(u8 irqn) -{ - if (irqn <= 239) - NVIC_STIR |= irqn; -} From 1684ffe18d4f8e54ebcec204b965bd1052ad7885 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:27:33 +0200 Subject: [PATCH 30/35] fallback for unknown chips --- include/libopencm3/dispatch/nvic.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 322ec29f..a405b5df 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -12,5 +12,9 @@ # include #else -# error "no chipset defined." +# warning"no chipset defined; user interrupts are disabled" + +#define NVIC_IRQ_COUNT 0 +#define IRQ_HANDLERS + #endif From 94ce82396bd69dfde8807dad27e23f30913247aa Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 13:28:03 +0200 Subject: [PATCH 31/35] modified examples to use libopencm3/cm3/nvic.h instead of /stm32/ --- examples/stm32/f1/lisa-m-1/can/can.c | 2 +- .../f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c | 2 +- .../adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c | 2 +- examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c | 2 +- examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c | 2 +- examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c | 2 +- examples/stm32/f1/obldc/can/can.c | 2 +- examples/stm32/f1/obldc/systick/systick.c | 2 +- examples/stm32/f1/obldc/usart_irq/usart_irq.c | 2 +- examples/stm32/f1/other/dogm128/main.c | 2 +- examples/stm32/f1/other/rtc/rtc.c | 2 +- examples/stm32/f1/other/systick/systick.c | 2 +- examples/stm32/f1/other/timer_interrupt/timer.c | 2 +- examples/stm32/f1/stm32-h103/button/button.c | 2 +- examples/stm32/f1/stm32-h103/exti_both/exti_both.c | 2 +- .../f1/stm32-h103/exti_rising_falling/exti_rising_falling.c | 2 +- examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c | 2 +- examples/stm32/f1/stm32-h103/timer/timer.c | 2 +- examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c | 2 +- .../stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c | 2 +- examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c | 2 +- examples/stm32/f1/stm32vl-discovery/rtc/rtc.c | 2 +- examples/stm32/f2/jobygps/spi_test/spi_test.c | 2 +- examples/stm32/f2/jobygps/usart_printf/usart_printf.c | 2 +- 25 files changed, 25 insertions(+), 25 deletions(-) diff --git a/examples/stm32/f1/lisa-m-1/can/can.c b/examples/stm32/f1/lisa-m-1/can/can.c index 6201547d..92ebd85f 100644 --- a/examples/stm32/f1/lisa-m-1/can/can.c +++ b/examples/stm32/f1/lisa-m-1/can/can.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c index bda1d9dc..674343d0 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include volatile u16 temperature = 0; diff --git a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c index 13341841..cbff97dc 100644 --- a/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c +++ b/examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include volatile u16 temperature = 0; volatile u16 v_refint = 0; diff --git a/examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c b/examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c index ac3bb3ca..369c5390 100644 --- a/examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c +++ b/examples/stm32/f1/lisa-m-2/usart_dma/usart_dma.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c b/examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c index dbe9140a..e5d9e686 100644 --- a/examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c +++ b/examples/stm32/f1/lisa-m-2/usart_irq/usart_irq.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c index 6b1096ed..e4e01279 100644 --- a/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/lisa-m-2/usart_irq_printf/usart_irq_printf.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c b/examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c index a66bcbc6..bd245ffa 100644 --- a/examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c +++ b/examples/stm32/f1/lisa-m-2/usart_printf/usart_printf.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/obldc/can/can.c b/examples/stm32/f1/obldc/can/can.c index d26be508..a29d8d73 100644 --- a/examples/stm32/f1/obldc/can/can.c +++ b/examples/stm32/f1/obldc/can/can.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/obldc/systick/systick.c b/examples/stm32/f1/obldc/systick/systick.c index e854f85d..7abdd546 100644 --- a/examples/stm32/f1/obldc/systick/systick.c +++ b/examples/stm32/f1/obldc/systick/systick.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include u32 temp32; diff --git a/examples/stm32/f1/obldc/usart_irq/usart_irq.c b/examples/stm32/f1/obldc/usart_irq/usart_irq.c index 3925565f..e13dd812 100644 --- a/examples/stm32/f1/obldc/usart_irq/usart_irq.c +++ b/examples/stm32/f1/obldc/usart_irq/usart_irq.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f1/other/dogm128/main.c b/examples/stm32/f1/other/dogm128/main.c index 5838af42..7889794a 100644 --- a/examples/stm32/f1/other/dogm128/main.c +++ b/examples/stm32/f1/other/dogm128/main.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include "./dogm128.h" diff --git a/examples/stm32/f1/other/rtc/rtc.c b/examples/stm32/f1/other/rtc/rtc.c index ee2a4272..41c5d89f 100644 --- a/examples/stm32/f1/other/rtc/rtc.c +++ b/examples/stm32/f1/other/rtc/rtc.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f1/other/systick/systick.c b/examples/stm32/f1/other/systick/systick.c index b2df1710..9aa2e94c 100644 --- a/examples/stm32/f1/other/systick/systick.c +++ b/examples/stm32/f1/other/systick/systick.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include u32 temp32; diff --git a/examples/stm32/f1/other/timer_interrupt/timer.c b/examples/stm32/f1/other/timer_interrupt/timer.c index 21a0caa4..94505488 100644 --- a/examples/stm32/f1/other/timer_interrupt/timer.c +++ b/examples/stm32/f1/other/timer_interrupt/timer.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include void gpio_setup(void) { diff --git a/examples/stm32/f1/stm32-h103/button/button.c b/examples/stm32/f1/stm32-h103/button/button.c index 814fbfbe..9d9a5e9a 100644 --- a/examples/stm32/f1/stm32-h103/button/button.c +++ b/examples/stm32/f1/stm32-h103/button/button.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include u16 exti_line_state; diff --git a/examples/stm32/f1/stm32-h103/exti_both/exti_both.c b/examples/stm32/f1/stm32-h103/exti_both/exti_both.c index 3bafcc92..c871c357 100644 --- a/examples/stm32/f1/stm32-h103/exti_both/exti_both.c +++ b/examples/stm32/f1/stm32-h103/exti_both/exti_both.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include u16 exti_line_state; diff --git a/examples/stm32/f1/stm32-h103/exti_rising_falling/exti_rising_falling.c b/examples/stm32/f1/stm32-h103/exti_rising_falling/exti_rising_falling.c index c5dfe3ba..f847847e 100644 --- a/examples/stm32/f1/stm32-h103/exti_rising_falling/exti_rising_falling.c +++ b/examples/stm32/f1/stm32-h103/exti_rising_falling/exti_rising_falling.c @@ -20,7 +20,7 @@ #include #include -#include +#include #include #define FALLING 0 diff --git a/examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c index 65854ace..deb0ff0e 100644 --- a/examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c +++ b/examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #define FALLING 0 diff --git a/examples/stm32/f1/stm32-h103/timer/timer.c b/examples/stm32/f1/stm32-h103/timer/timer.c index 07f668b6..210e5921 100644 --- a/examples/stm32/f1/stm32-h103/timer/timer.c +++ b/examples/stm32/f1/stm32-h103/timer/timer.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include u16 frequency_sequence[18] = { diff --git a/examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c b/examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c index 009c6d77..ae95df8c 100644 --- a/examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c +++ b/examples/stm32/f1/stm32-h103/usart_irq/usart_irq.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c index 2143461b..5effb28d 100644 --- a/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c +++ b/examples/stm32/f1/stm32-h103/usart_irq_printf/usart_irq_printf.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c b/examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c index bc9fbd3c..a275d83a 100644 --- a/examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c +++ b/examples/stm32/f1/stm32-h103/usart_printf/usart_printf.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c b/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c index d447e9b7..b3c698bc 100644 --- a/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c +++ b/examples/stm32/f1/stm32vl-discovery/rtc/rtc.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include void clock_setup(void) { diff --git a/examples/stm32/f2/jobygps/spi_test/spi_test.c b/examples/stm32/f2/jobygps/spi_test/spi_test.c index 8775db8e..95ba0216 100644 --- a/examples/stm32/f2/jobygps/spi_test/spi_test.c +++ b/examples/stm32/f2/jobygps/spi_test/spi_test.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/examples/stm32/f2/jobygps/usart_printf/usart_printf.c b/examples/stm32/f2/jobygps/usart_printf/usart_printf.c index 67a7d7f6..d490e397 100644 --- a/examples/stm32/f2/jobygps/usart_printf/usart_printf.c +++ b/examples/stm32/f2/jobygps/usart_printf/usart_printf.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include void clock_setup(void) From 5afa53f01abb3f19e1140d1a6407c43e8b3947cf Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 16:29:58 +0200 Subject: [PATCH 32/35] drop two-line vector.c dispatchers in favor of central dispatch --- lib/cm3/vector.c | 6 ++++++ lib/dispatch/vector.c | 11 +++++++++++ lib/efm32/tinygecko/vector.c | 2 -- lib/lm3s/vector.c | 2 -- lib/lpc17xx/vector.c | 2 -- lib/lpc43xx/vector.c | 8 +------- lib/stm32/f1/vector.c | 2 -- lib/stm32/f2/vector.c | 2 -- lib/stm32/f4/vector.c | 8 +------- 9 files changed, 19 insertions(+), 24 deletions(-) create mode 100644 lib/dispatch/vector.c delete mode 100644 lib/efm32/tinygecko/vector.c delete mode 100644 lib/lm3s/vector.c delete mode 100644 lib/lpc17xx/vector.c delete mode 100644 lib/stm32/f1/vector.c delete mode 100644 lib/stm32/f2/vector.c diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 200e8e58..7b660f90 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -20,6 +20,9 @@ #include +/* load optional platform dependent initialization routines */ +#include "../dispatch/vector.c" + #define WEAK __attribute__ ((weak)) /* Symbols exported by the linker script(s): */ @@ -70,6 +73,9 @@ void WEAK reset_handler(void) while (dest < &_ebss) *dest++ = 0; + /* might be provided by platform specific vector.c */ + pre_main(); + /* Call the application's entry point. */ main(); } diff --git a/lib/dispatch/vector.c b/lib/dispatch/vector.c new file mode 100644 index 00000000..baab436c --- /dev/null +++ b/lib/dispatch/vector.c @@ -0,0 +1,11 @@ +#if defined(STM32F4) +# include "../stm32/f4/vector.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector.c" + +#else + +static void pre_main(void) {} + +#endif diff --git a/lib/efm32/tinygecko/vector.c b/lib/efm32/tinygecko/vector.c deleted file mode 100644 index d6da5a2b..00000000 --- a/lib/efm32/tinygecko/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/lm3s/vector.c b/lib/lm3s/vector.c deleted file mode 100644 index e9e7e064..00000000 --- a/lib/lm3s/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../cm3/vector.c" diff --git a/lib/lpc17xx/vector.c b/lib/lpc17xx/vector.c deleted file mode 100644 index 61342f45..00000000 --- a/lib/lpc17xx/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../cm3/vector.c" diff --git a/lib/lpc43xx/vector.c b/lib/lpc43xx/vector.c index 66e9b639..0463a65c 100644 --- a/lib/lpc43xx/vector.c +++ b/lib/lpc43xx/vector.c @@ -18,17 +18,13 @@ * along with this library. If not, see . */ -#include -#define reset_handler original_reset_handler -#include "../cm3/vector.c" -#undef reset_handler #include extern unsigned _etext_ram, _text_ram, _etext_rom; #define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) ) -void WEAK reset_handler(void) +static void pre_main(void) { volatile unsigned *src, *dest; @@ -49,6 +45,4 @@ void WEAK reset_handler(void) /* Continue Execution in RAM */ } - - original_reset_handler(); } diff --git a/lib/stm32/f1/vector.c b/lib/stm32/f1/vector.c deleted file mode 100644 index 795773b1..00000000 --- a/lib/stm32/f1/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/stm32/f2/vector.c b/lib/stm32/f2/vector.c deleted file mode 100644 index 24d11851..00000000 --- a/lib/stm32/f2/vector.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../../cm3/vector.c" diff --git a/lib/stm32/f4/vector.c b/lib/stm32/f4/vector.c index a5017b36..53042992 100644 --- a/lib/stm32/f4/vector.c +++ b/lib/stm32/f4/vector.c @@ -18,16 +18,10 @@ * along with this library. If not, see . */ -#include -#define reset_handler original_reset_handler -#include "../../cm3/vector.c" -#undef reset_handler #include -void WEAK reset_handler(void) +static void pre_main(void) { /* Enable access to Floating-Point coprocessor. */ SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11); - - original_reset_handler(); } From 5ceb377a378203c80580fbe5160000fca998b635 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 16:52:48 +0200 Subject: [PATCH 33/35] switch all interrupt lists to yaml format --- include/libopencm3/dispatch/nvic.h | 6 +- include/libopencm3/efm32/tinygecko/irq.yaml | 2 +- include/libopencm3/lm3s/irq.h | 505 ------------------ include/libopencm3/lm3s/irq.yaml | 120 +++++ include/libopencm3/lpc17xx/irq.h | 33 -- include/libopencm3/lpc43xx/irq.h | 234 -------- include/libopencm3/lpc43xx/irq.yaml | 55 ++ include/libopencm3/lpc43xx/nvic.h | 68 --- include/libopencm3/stm32/f1/irq.h | 306 ----------- include/libopencm3/stm32/f1/irq.yaml | 72 +++ include/libopencm3/stm32/f1/nvic_f1.h | 116 ---- include/libopencm3/stm32/f2/irq.h | 359 ------------- include/libopencm3/stm32/f2/irq.yaml | 85 +++ include/libopencm3/stm32/f2/nvic_f2.h | 114 ---- include/libopencm3/stm32/f4/irq.h | 359 ------------- include/libopencm3/stm32/f4/irq.yaml | 85 +++ include/libopencm3/stm32/f4/nvic_f4.h | 114 ---- .../efm32/tinygecko => scripts}/irq2nvic_h | 15 +- 18 files changed, 435 insertions(+), 2213 deletions(-) delete mode 100644 include/libopencm3/lm3s/irq.h create mode 100644 include/libopencm3/lm3s/irq.yaml delete mode 100644 include/libopencm3/lpc17xx/irq.h delete mode 100644 include/libopencm3/lpc43xx/irq.h create mode 100644 include/libopencm3/lpc43xx/irq.yaml delete mode 100644 include/libopencm3/lpc43xx/nvic.h delete mode 100644 include/libopencm3/stm32/f1/irq.h create mode 100644 include/libopencm3/stm32/f1/irq.yaml delete mode 100644 include/libopencm3/stm32/f1/nvic_f1.h delete mode 100644 include/libopencm3/stm32/f2/irq.h create mode 100644 include/libopencm3/stm32/f2/irq.yaml delete mode 100644 include/libopencm3/stm32/f2/nvic_f2.h delete mode 100644 include/libopencm3/stm32/f4/irq.h create mode 100644 include/libopencm3/stm32/f4/irq.yaml delete mode 100644 include/libopencm3/stm32/f4/nvic_f4.h rename {include/libopencm3/efm32/tinygecko => scripts}/irq2nvic_h (81%) diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index a405b5df..67ba5448 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -1,9 +1,9 @@ #if defined(STM32F1) -# include +# include #elif defined(STM32F2) -# include +# include #elif defined(STM32F4) -# include +# include #elif defined(TINYGECKO) # include diff --git a/include/libopencm3/efm32/tinygecko/irq.yaml b/include/libopencm3/efm32/tinygecko/irq.yaml index 16fa69c5..da954f60 100644 --- a/include/libopencm3/efm32/tinygecko/irq.yaml +++ b/include/libopencm3/efm32/tinygecko/irq.yaml @@ -1,4 +1,4 @@ -includeguard: LIBOPENCM3_EFM32_TINYGECKO_VECTOR_H +includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H partname_humanreadable: EFM32 Tiny Gecko series partname_doxygen: EFM32TG # The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1. diff --git a/include/libopencm3/lm3s/irq.h b/include/libopencm3/lm3s/irq.h deleted file mode 100644 index 331ee513..00000000 --- a/include/libopencm3/lm3s/irq.h +++ /dev/null @@ -1,505 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Gareth McMullin - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LM3S_IRQ_H -#define LIBOPENCM3_LM3S_IRQ_H - -#define IRQ_GPIOA 0 -#define IRQ_GPIOB 1 -#define IRQ_GPIOC 2 -#define IRQ_GPIOD 3 -#define IRQ_GPIOE 4 -#define IRQ_UART0 5 -#define IRQ_UART1 6 -#define IRQ_SSI0 7 -#define IRQ_I2C0 8 -#define IRQ_PWM0_FAULT 9 -#define IRQ_PWM0_0 10 -#define IRQ_PWM0_1 11 -#define IRQ_PWM0_2 12 -#define IRQ_QEI0 13 -#define IRQ_ADC0SS0 14 -#define IRQ_ADC0SS1 15 -#define IRQ_ADC0SS2 16 -#define IRQ_ADC0SS3 17 -#define IRQ_WATCHDOG 18 -#define IRQ_TIMER0A 19 -#define IRQ_TIMER0B 20 -#define IRQ_TIMER1A 21 -#define IRQ_TIMER1B 22 -#define IRQ_TIMER2A 23 -#define IRQ_TIMER2B 24 -#define IRQ_COMP0 25 -#define IRQ_COMP1 26 -#define IRQ_COMP2 27 -#define IRQ_SYSCTL 28 -#define IRQ_FLASH 29 -#define IRQ_GPIOF 30 -#define IRQ_GPIOG 31 -#define IRQ_GPIOH 32 -#define IRQ_UART2 33 -#define IRQ_SSI1 34 -#define IRQ_TIMER3A 35 -#define IRQ_TIMER3B 36 -#define IRQ_I2C1 37 -#define IRQ_QEI1 38 -#define IRQ_CAN0 39 -#define IRQ_CAN1 40 -#define IRQ_CAN2 41 -#define IRQ_ETH 42 -#define IRQ_HIBERNATE 43 -#define IRQ_USB0 44 -#define IRQ_PWM0_3 45 -#define IRQ_UDMA 46 -#define IRQ_UDMAERR 47 -#define IRQ_ADC1SS0 48 -#define IRQ_ADC1SS1 49 -#define IRQ_ADC1SS2 50 -#define IRQ_ADC1SS3 51 -#define IRQ_I2S0 52 -#define IRQ_EPI0 53 -#define IRQ_GPIOJ 54 -#define IRQ_GPIOK 55 -#define IRQ_GPIOL 56 -#define IRQ_SSI2 57 -#define IRQ_SSI3 58 -#define IRQ_UART3 59 -#define IRQ_UART4 60 -#define IRQ_UART5 61 -#define IRQ_UART6 62 -#define IRQ_UART7 63 -/* undefined: slot 64 */ -/* undefined: slot 65 */ -/* undefined: slot 66 */ -/* undefined: slot 67 */ -#define IRQ_I2C2 68 -#define IRQ_I2C3 69 -#define IRQ_TIMER4A 70 -#define IRQ_TIMER4B 71 -/* undefined: slot 72 */ -/* undefined: slot 73 */ -/* undefined: slot 74 */ -/* undefined: slot 75 */ -/* undefined: slot 76 */ -/* undefined: slot 77 */ -/* undefined: slot 78 */ -/* undefined: slot 79 */ -/* undefined: slot 80 */ -/* undefined: slot 81 */ -/* undefined: slot 82 */ -/* undefined: slot 83 */ -/* undefined: slot 84 */ -/* undefined: slot 85 */ -/* undefined: slot 86 */ -/* undefined: slot 87 */ -/* undefined: slot 88 */ -/* undefined: slot 89 */ -/* undefined: slot 90 */ -/* undefined: slot 91 */ -#define IRQ_TIMER5A 92 -#define IRQ_TIMER5B 93 -#define IRQ_WTIMER0A 94 -#define IRQ_WTIMER0B 95 -#define IRQ_WTIMER1A 96 -#define IRQ_WTIMER1B 97 -#define IRQ_WTIMER2A 98 -#define IRQ_WTIMER2B 99 -#define IRQ_WTIMER3A 100 -#define IRQ_WTIMER3B 101 -#define IRQ_WTIMER4A 102 -#define IRQ_WTIMER4B 103 -#define IRQ_WTIMER5A 104 -#define IRQ_WTIMER5B 105 -#define IRQ_SYSEXC 106 -#define IRQ_PECI0 107 -#define IRQ_LPC0 108 -#define IRQ_I2C4 109 -#define IRQ_I2C5 110 -#define IRQ_GPIOM 111 -#define IRQ_GPION 112 -/* undefined: slot 113 */ -#define IRQ_FAN0 114 -/* undefined: slot 115 */ -#define IRQ_GPIOP0 116 -#define IRQ_GPIOP1 117 -#define IRQ_GPIOP2 118 -#define IRQ_GPIOP3 119 -#define IRQ_GPIOP4 120 -#define IRQ_GPIOP5 121 -#define IRQ_GPIOP6 122 -#define IRQ_GPIOP7 123 -#define IRQ_GPIOQ0 124 -#define IRQ_GPIOQ1 125 -#define IRQ_GPIOQ2 126 -#define IRQ_GPIOQ3 127 -#define IRQ_GPIOQ4 128 -#define IRQ_GPIOQ5 129 -#define IRQ_GPIOQ6 130 -#define IRQ_GPIOQ7 131 -/* undefined: slot 132 */ -/* undefined: slot 133 */ -#define IRQ_PWM1_0 134 -#define IRQ_PWM1_1 135 -#define IRQ_PWM1_2 136 -#define IRQ_PWM1_3 137 -#define IRQ_PWM1_FAULT 138 - -#define IRQ_COUNT 139 - -#define WEAK __attribute__ ((weak)) - -void WEAK gpioa_isr(void); -void WEAK gpiob_isr(void); -void WEAK gpioc_isr(void); -void WEAK gpiod_isr(void); -void WEAK gpioe_isr(void); -void WEAK uart0_isr(void); -void WEAK uart1_isr(void); -void WEAK ssi0_isr(void); -void WEAK i2c0_isr(void); -void WEAK pwm0_fault_isr(void); -void WEAK pwm0_0_isr(void); -void WEAK pwm0_1_isr(void); -void WEAK pwm0_2_isr(void); -void WEAK qei0_isr(void); -void WEAK adc0ss0_isr(void); -void WEAK adc0ss1_isr(void); -void WEAK adc0ss2_isr(void); -void WEAK adc0ss3_isr(void); -void WEAK watchdog_isr(void); -void WEAK timer0a_isr(void); -void WEAK timer0b_isr(void); -void WEAK timer1a_isr(void); -void WEAK timer1b_isr(void); -void WEAK timer2a_isr(void); -void WEAK timer2b_isr(void); -void WEAK comp0_isr(void); -void WEAK comp1_isr(void); -void WEAK comp2_isr(void); -void WEAK sysctl_isr(void); -void WEAK flash_isr(void); -void WEAK gpiof_isr(void); -void WEAK gpiog_isr(void); -void WEAK gpioh_isr(void); -void WEAK uart2_isr(void); -void WEAK ssi1_isr(void); -void WEAK timer3a_isr(void); -void WEAK timer3b_isr(void); -void WEAK i2c1_isr(void); -void WEAK qei1_isr(void); -void WEAK can0_isr(void); -void WEAK can1_isr(void); -void WEAK can2_isr(void); -void WEAK eth_isr(void); -void WEAK hibernate_isr(void); -void WEAK usb0_isr(void); -void WEAK pwm0_3_isr(void); -void WEAK udma_isr(void); -void WEAK udmaerr_isr(void); -void WEAK adc1ss0_isr(void); -void WEAK adc1ss1_isr(void); -void WEAK adc1ss2_isr(void); -void WEAK adc1ss3_isr(void); -void WEAK i2s0_isr(void); -void WEAK epi0_isr(void); -void WEAK gpioj_isr(void); -void WEAK gpiok_isr(void); -void WEAK gpiol_isr(void); -void WEAK ssi2_isr(void); -void WEAK ssi3_isr(void); -void WEAK uart3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK uart6_isr(void); -void WEAK uart7_isr(void); -void WEAK i2c2_isr(void); -void WEAK i2c3_isr(void); -void WEAK timer4a_isr(void); -void WEAK timer4b_isr(void); -void WEAK timer5a_isr(void); -void WEAK timer5b_isr(void); -void WEAK wtimer0a_isr(void); -void WEAK wtimer0b_isr(void); -void WEAK wtimer1a_isr(void); -void WEAK wtimer1b_isr(void); -void WEAK wtimer2a_isr(void); -void WEAK wtimer2b_isr(void); -void WEAK wtimer3a_isr(void); -void WEAK wtimer3b_isr(void); -void WEAK wtimer4a_isr(void); -void WEAK wtimer4b_isr(void); -void WEAK wtimer5a_isr(void); -void WEAK wtimer5b_isr(void); -void WEAK sysexc_isr(void); -void WEAK peci0_isr(void); -void WEAK lpc0_isr(void); -void WEAK i2c4_isr(void); -void WEAK i2c5_isr(void); -void WEAK gpiom_isr(void); -void WEAK gpion_isr(void); -void WEAK fan0_isr(void); -void WEAK gpiop0_isr(void); -void WEAK gpiop1_isr(void); -void WEAK gpiop2_isr(void); -void WEAK gpiop3_isr(void); -void WEAK gpiop4_isr(void); -void WEAK gpiop5_isr(void); -void WEAK gpiop6_isr(void); -void WEAK gpiop7_isr(void); -void WEAK gpioq0_isr(void); -void WEAK gpioq1_isr(void); -void WEAK gpioq2_isr(void); -void WEAK gpioq3_isr(void); -void WEAK gpioq4_isr(void); -void WEAK gpioq5_isr(void); -void WEAK gpioq6_isr(void); -void WEAK gpioq7_isr(void); -void WEAK pwm1_0_isr(void); -void WEAK pwm1_1_isr(void); -void WEAK pwm1_2_isr(void); -void WEAK pwm1_3_isr(void); -void WEAK pwm1_fault_isr(void); - -#pragma weak gpioa_isr = blocking_handler -#pragma weak gpiob_isr = blocking_handler -#pragma weak gpioc_isr = blocking_handler -#pragma weak gpiod_isr = blocking_handler -#pragma weak gpioe_isr = blocking_handler -#pragma weak uart0_isr = blocking_handler -#pragma weak uart1_isr = blocking_handler -#pragma weak ssi0_isr = blocking_handler -#pragma weak i2c0_isr = blocking_handler -#pragma weak pwm0_fault_isr = blocking_handler -#pragma weak pwm0_0_isr = blocking_handler -#pragma weak pwm0_1_isr = blocking_handler -#pragma weak pwm0_2_isr = blocking_handler -#pragma weak qei0_isr = blocking_handler -#pragma weak adc0ss0_isr = blocking_handler -#pragma weak adc0ss1_isr = blocking_handler -#pragma weak adc0ss2_isr = blocking_handler -#pragma weak adc0ss3_isr = blocking_handler -#pragma weak watchdog_isr = blocking_handler -#pragma weak timer0a_isr = blocking_handler -#pragma weak timer0b_isr = blocking_handler -#pragma weak timer1a_isr = blocking_handler -#pragma weak timer1b_isr = blocking_handler -#pragma weak timer2a_isr = blocking_handler -#pragma weak timer2b_isr = blocking_handler -#pragma weak comp0_isr = blocking_handler -#pragma weak comp1_isr = blocking_handler -#pragma weak comp2_isr = blocking_handler -#pragma weak sysctl_isr = blocking_handler -#pragma weak flash_isr = blocking_handler -#pragma weak gpiof_isr = blocking_handler -#pragma weak gpiog_isr = blocking_handler -#pragma weak gpioh_isr = blocking_handler -#pragma weak uart2_isr = blocking_handler -#pragma weak ssi1_isr = blocking_handler -#pragma weak timer3a_isr = blocking_handler -#pragma weak timer3b_isr = blocking_handler -#pragma weak i2c1_isr = blocking_handler -#pragma weak qei1_isr = blocking_handler -#pragma weak can0_isr = blocking_handler -#pragma weak can1_isr = blocking_handler -#pragma weak can2_isr = blocking_handler -#pragma weak eth_isr = blocking_handler -#pragma weak hibernate_isr = blocking_handler -#pragma weak usb0_isr = blocking_handler -#pragma weak pwm0_3_isr = blocking_handler -#pragma weak udma_isr = blocking_handler -#pragma weak udmaerr_isr = blocking_handler -#pragma weak adc1ss0_isr = blocking_handler -#pragma weak adc1ss1_isr = blocking_handler -#pragma weak adc1ss2_isr = blocking_handler -#pragma weak adc1ss3_isr = blocking_handler -#pragma weak i2s0_isr = blocking_handler -#pragma weak epi0_isr = blocking_handler -#pragma weak gpioj_isr = blocking_handler -#pragma weak gpiok_isr = blocking_handler -#pragma weak gpiol_isr = blocking_handler -#pragma weak ssi2_isr = blocking_handler -#pragma weak ssi3_isr = blocking_handler -#pragma weak uart3_isr = blocking_handler -#pragma weak uart4_isr = blocking_handler -#pragma weak uart5_isr = blocking_handler -#pragma weak uart6_isr = blocking_handler -#pragma weak uart7_isr = blocking_handler -#pragma weak i2c2_isr = blocking_handler -#pragma weak i2c3_isr = blocking_handler -#pragma weak timer4a_isr = blocking_handler -#pragma weak timer4b_isr = blocking_handler -#pragma weak timer5a_isr = blocking_handler -#pragma weak timer5b_isr = blocking_handler -#pragma weak wtimer0a_isr = blocking_handler -#pragma weak wtimer0b_isr = blocking_handler -#pragma weak wtimer1a_isr = blocking_handler -#pragma weak wtimer1b_isr = blocking_handler -#pragma weak wtimer2a_isr = blocking_handler -#pragma weak wtimer2b_isr = blocking_handler -#pragma weak wtimer3a_isr = blocking_handler -#pragma weak wtimer3b_isr = blocking_handler -#pragma weak wtimer4a_isr = blocking_handler -#pragma weak wtimer4b_isr = blocking_handler -#pragma weak wtimer5a_isr = blocking_handler -#pragma weak wtimer5b_isr = blocking_handler -#pragma weak sysexc_isr = blocking_handler -#pragma weak peci0_isr = blocking_handler -#pragma weak lpc0_isr = blocking_handler -#pragma weak i2c4_isr = blocking_handler -#pragma weak i2c5_isr = blocking_handler -#pragma weak gpiom_isr = blocking_handler -#pragma weak gpion_isr = blocking_handler -#pragma weak fan0_isr = blocking_handler -#pragma weak gpiop0_isr = blocking_handler -#pragma weak gpiop1_isr = blocking_handler -#pragma weak gpiop2_isr = blocking_handler -#pragma weak gpiop3_isr = blocking_handler -#pragma weak gpiop4_isr = blocking_handler -#pragma weak gpiop5_isr = blocking_handler -#pragma weak gpiop6_isr = blocking_handler -#pragma weak gpiop7_isr = blocking_handler -#pragma weak gpioq0_isr = blocking_handler -#pragma weak gpioq1_isr = blocking_handler -#pragma weak gpioq2_isr = blocking_handler -#pragma weak gpioq3_isr = blocking_handler -#pragma weak gpioq4_isr = blocking_handler -#pragma weak gpioq5_isr = blocking_handler -#pragma weak gpioq6_isr = blocking_handler -#pragma weak gpioq7_isr = blocking_handler -#pragma weak pwm1_0_isr = blocking_handler -#pragma weak pwm1_1_isr = blocking_handler -#pragma weak pwm1_2_isr = blocking_handler -#pragma weak pwm1_3_isr = blocking_handler -#pragma weak pwm1_fault_isr = blocking_handler - -#define IRQ_HANDLERS \ - [IRQ_GPIOA] = gpioa_isr, \ - [IRQ_GPIOB] = gpiob_isr, \ - [IRQ_GPIOC] = gpioc_isr, \ - [IRQ_GPIOD] = gpiod_isr, \ - [IRQ_GPIOE] = gpioe_isr, \ - [IRQ_UART0] = uart0_isr, \ - [IRQ_UART1] = uart1_isr, \ - [IRQ_SSI0] = ssi0_isr, \ - [IRQ_I2C0] = i2c0_isr, \ - [IRQ_PWM0_FAULT] = pwm0_fault_isr, \ - [IRQ_PWM0_0] = pwm0_0_isr, \ - [IRQ_PWM0_1] = pwm0_1_isr, \ - [IRQ_PWM0_2] = pwm0_2_isr, \ - [IRQ_QEI0] = qei0_isr, \ - [IRQ_ADC0SS0] = adc0ss0_isr, \ - [IRQ_ADC0SS1] = adc0ss1_isr, \ - [IRQ_ADC0SS2] = adc0ss2_isr, \ - [IRQ_ADC0SS3] = adc0ss3_isr, \ - [IRQ_WATCHDOG] = watchdog_isr, \ - [IRQ_TIMER0A] = timer0a_isr, \ - [IRQ_TIMER0B] = timer0b_isr, \ - [IRQ_TIMER1A] = timer1a_isr, \ - [IRQ_TIMER1B] = timer1b_isr, \ - [IRQ_TIMER2A] = timer2a_isr, \ - [IRQ_TIMER2B] = timer2b_isr, \ - [IRQ_COMP0] = comp0_isr, \ - [IRQ_COMP1] = comp1_isr, \ - [IRQ_COMP2] = comp2_isr, \ - [IRQ_SYSCTL] = sysctl_isr, \ - [IRQ_FLASH] = flash_isr, \ - [IRQ_GPIOF] = gpiof_isr, \ - [IRQ_GPIOG] = gpiog_isr, \ - [IRQ_GPIOH] = gpioh_isr, \ - [IRQ_UART2] = uart2_isr, \ - [IRQ_SSI1] = ssi1_isr, \ - [IRQ_TIMER3A] = timer3a_isr, \ - [IRQ_TIMER3B] = timer3b_isr, \ - [IRQ_I2C1] = i2c1_isr, \ - [IRQ_QEI1] = qei1_isr, \ - [IRQ_CAN0] = can0_isr, \ - [IRQ_CAN1] = can1_isr, \ - [IRQ_CAN2] = can2_isr, \ - [IRQ_ETH] = eth_isr, \ - [IRQ_HIBERNATE] = hibernate_isr, \ - [IRQ_USB0] = usb0_isr, \ - [IRQ_PWM0_3] = pwm0_3_isr, \ - [IRQ_UDMA] = udma_isr, \ - [IRQ_UDMAERR] = udmaerr_isr, \ - [IRQ_ADC1SS0] = adc1ss0_isr, \ - [IRQ_ADC1SS1] = adc1ss1_isr, \ - [IRQ_ADC1SS2] = adc1ss2_isr, \ - [IRQ_ADC1SS3] = adc1ss3_isr, \ - [IRQ_I2S0] = i2s0_isr, \ - [IRQ_EPI0] = epi0_isr, \ - [IRQ_GPIOJ] = gpioj_isr, \ - [IRQ_GPIOK] = gpiok_isr, \ - [IRQ_GPIOL] = gpiol_isr, \ - [IRQ_SSI2] = ssi2_isr, \ - [IRQ_SSI3] = ssi3_isr, \ - [IRQ_UART3] = uart3_isr, \ - [IRQ_UART4] = uart4_isr, \ - [IRQ_UART5] = uart5_isr, \ - [IRQ_UART6] = uart6_isr, \ - [IRQ_UART7] = uart7_isr, \ - [IRQ_I2C2] = i2c2_isr, \ - [IRQ_I2C3] = i2c3_isr, \ - [IRQ_TIMER4A] = timer4a_isr, \ - [IRQ_TIMER4B] = timer4b_isr, \ - [IRQ_TIMER5A] = timer5a_isr, \ - [IRQ_TIMER5B] = timer5b_isr, \ - [IRQ_WTIMER0A] = wtimer0a_isr, \ - [IRQ_WTIMER0B] = wtimer0b_isr, \ - [IRQ_WTIMER1A] = wtimer1a_isr, \ - [IRQ_WTIMER1B] = wtimer1b_isr, \ - [IRQ_WTIMER2A] = wtimer2a_isr, \ - [IRQ_WTIMER2B] = wtimer2b_isr, \ - [IRQ_WTIMER3A] = wtimer3a_isr, \ - [IRQ_WTIMER3B] = wtimer3b_isr, \ - [IRQ_WTIMER4A] = wtimer4a_isr, \ - [IRQ_WTIMER4B] = wtimer4b_isr, \ - [IRQ_WTIMER5A] = wtimer5a_isr, \ - [IRQ_WTIMER5B] = wtimer5b_isr, \ - [IRQ_SYSEXC] = sysexc_isr, \ - [IRQ_PECI0] = peci0_isr, \ - [IRQ_LPC0] = lpc0_isr, \ - [IRQ_I2C4] = i2c4_isr, \ - [IRQ_I2C5] = i2c5_isr, \ - [IRQ_GPIOM] = gpiom_isr, \ - [IRQ_GPION] = gpion_isr, \ - [IRQ_FAN0] = fan0_isr, \ - [IRQ_GPIOP0] = gpiop0_isr, \ - [IRQ_GPIOP1] = gpiop1_isr, \ - [IRQ_GPIOP2] = gpiop2_isr, \ - [IRQ_GPIOP3] = gpiop3_isr, \ - [IRQ_GPIOP4] = gpiop4_isr, \ - [IRQ_GPIOP5] = gpiop5_isr, \ - [IRQ_GPIOP6] = gpiop6_isr, \ - [IRQ_GPIOP7] = gpiop7_isr, \ - [IRQ_GPIOQ0] = gpioq0_isr, \ - [IRQ_GPIOQ1] = gpioq1_isr, \ - [IRQ_GPIOQ2] = gpioq2_isr, \ - [IRQ_GPIOQ3] = gpioq3_isr, \ - [IRQ_GPIOQ4] = gpioq4_isr, \ - [IRQ_GPIOQ5] = gpioq5_isr, \ - [IRQ_GPIOQ6] = gpioq6_isr, \ - [IRQ_GPIOQ7] = gpioq7_isr, \ - [IRQ_PWM1_0] = pwm1_0_isr, \ - [IRQ_PWM1_1] = pwm1_1_isr, \ - [IRQ_PWM1_2] = pwm1_2_isr, \ - [IRQ_PWM1_3] = pwm1_3_isr, \ - [IRQ_PWM1_FAULT] = pwm1_fault_isr, - -#endif diff --git a/include/libopencm3/lm3s/irq.yaml b/include/libopencm3/lm3s/irq.yaml new file mode 100644 index 00000000..7d5ff3a5 --- /dev/null +++ b/include/libopencm3/lm3s/irq.yaml @@ -0,0 +1,120 @@ +includeguard: LIBOPENCM3_LM3S_NVIC_H +partname_humanreadable: LM3S series +partname_doxygen: LM3S +irqs: + 0: GPIOA + 1: GPIOB + 2: GPIOC + 3: GPIOD + 4: GPIOE + 5: UART0 + 6: UART1 + 7: SSI0 + 8: I2C0 + 9: PWM0_FAULT + 10: PWM0_0 + 11: PWM0_1 + 12: PWM0_2 + 13: QEI0 + 14: ADC0SS0 + 15: ADC0SS1 + 16: ADC0SS2 + 17: ADC0SS3 + 18: WATCHDOG + 19: TIMER0A + 20: TIMER0B + 21: TIMER1A + 22: TIMER1B + 23: TIMER2A + 24: TIMER2B + 25: COMP0 + 26: COMP1 + 27: COMP2 + 28: SYSCTL + 29: FLASH + 30: GPIOF + 31: GPIOG + 32: GPIOH + 33: UART2 + 34: SSI1 + 35: TIMER3A + 36: TIMER3B + 37: I2C1 + 38: QEI1 + 39: CAN0 + 40: CAN1 + 41: CAN2 + 42: ETH + 43: HIBERNATE + 44: USB0 + 45: PWM0_3 + 46: UDMA + 47: UDMAERR + 48: ADC1SS0 + 49: ADC1SS1 + 50: ADC1SS2 + 51: ADC1SS3 + 52: I2S0 + 53: EPI0 + 54: GPIOJ + 55: GPIOK + 56: GPIOL + 57: SSI2 + 58: SSI3 + 59: UART3 + 60: UART4 + 61: UART5 + 62: UART6 + 63: UART7 +# undefined: slot 64 - 67 + 68: I2C2 + 69: I2C3 + 70: TIMER4A + 71: TIMER4B +# undefined: slot 72 - 91 + 92: TIMER5A + 93: TIMER5B + 94: WTIMER0A + 95: WTIMER0B + 96: WTIMER1A + 97: WTIMER1B + 98: WTIMER2A + 99: WTIMER2B + 100: WTIMER3A + 101: WTIMER3B + 102: WTIMER4A + 103: WTIMER4B + 104: WTIMER5A + 105: WTIMER5B + 106: SYSEXC + 107: PECI0 + 108: LPC0 + 109: I2C4 + 110: I2C5 + 111: GPIOM + 112: GPION +# undefined: slot 113 + 114: FAN0 +# undefined: slot 115 + 116: GPIOP0 + 117: GPIOP1 + 118: GPIOP2 + 119: GPIOP3 + 120: GPIOP4 + 121: GPIOP5 + 122: GPIOP6 + 123: GPIOP7 + 124: GPIOQ0 + 125: GPIOQ1 + 126: GPIOQ2 + 127: GPIOQ3 + 128: GPIOQ4 + 129: GPIOQ5 + 130: GPIOQ6 + 131: GPIOQ7 +# undefined: slot 132 - 133 + 134: PWM1_0 + 135: PWM1_1 + 136: PWM1_2 + 137: PWM1_3 + 138: PWM1_FAULT diff --git a/include/libopencm3/lpc17xx/irq.h b/include/libopencm3/lpc17xx/irq.h deleted file mode 100644 index 9c31267b..00000000 --- a/include/libopencm3/lpc17xx/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC17xx_IRQ_H -#define LIBOPENCM3_LPC17xx_IRQ_H - -/* TODO: Interrupt definitions */ -#define IRQ_COUNT 0 - -/* TODO: Interrupt handler prototypes */ - -/* TODO: Interrupt handler weak aliases */ - -#define IRQ_HANDLERS - -#endif diff --git a/include/libopencm3/lpc43xx/irq.h b/include/libopencm3/lpc43xx/irq.h deleted file mode 100644 index a83a8d77..00000000 --- a/include/libopencm3/lpc43xx/irq.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 Michael Ossmann - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_LPC43XX_IRQ_H -#define LIBOPENCM3_LPC43XX_IRQ_H - -#define IRQ_DAC 0 -#define IRQ_M0CORE 1 -#define IRQ_DMA 2 -/* reserved: 3 */ -/* reserved: 4 */ -#define IRQ_ETHERNET 5 -#define IRQ_SDIO 6 -#define IRQ_LCD 7 -#define IRQ_USB0 8 -#define IRQ_USB1 9 -#define IRQ_SCT 10 -#define IRQ_RITIMER 11 -#define IRQ_TIMER0 12 -#define IRQ_TIMER1 13 -#define IRQ_TIMER2 14 -#define IRQ_TIMER3 15 -#define IRQ_MCPWM 16 -#define IRQ_ADC0 17 -#define IRQ_I2C0 18 -#define IRQ_I2C1 19 -#define IRQ_SPI 20 -#define IRQ_ADC1 21 -#define IRQ_SSP0 22 -#define IRQ_SSP1 23 -#define IRQ_USART0 24 -#define IRQ_UART1 25 -#define IRQ_USART2 26 -#define IRQ_USART3 27 -#define IRQ_I2S0 28 -#define IRQ_I2S1 29 -#define IRQ_SPIFI 30 -#define IRQ_SGPIO 31 -#define IRQ_PIN_INT0 32 -#define IRQ_PIN_INT1 33 -#define IRQ_PIN_INT2 34 -#define IRQ_PIN_INT3 35 -#define IRQ_PIN_INT4 36 -#define IRQ_PIN_INT5 37 -#define IRQ_PIN_INT6 38 -#define IRQ_PIN_INT7 39 -#define IRQ_GINT0 40 -#define IRQ_GINT1 41 -#define IRQ_EVENTROUTER 42 -#define IRQ_C_CAN1 43 -/* reserved: 44 */ -/* reserved: 45 */ -#define IRQ_ATIMER 46 -#define IRQ_RTC 47 -/* reserved: 48 */ -#define IRQ_WWDT 49 -/* reserved: 50 */ -#define IRQ_C_CAN0 51 -#define IRQ_QEI 52 - -#define IRQ_COUNT 53 - -#define WEAK __attribute__ ((weak)) - -void WEAK dac_irqhandler(void); -void WEAK m0core_irqhandler(void); -void WEAK dma_irqhandler(void); -void WEAK ethernet_irqhandler(void); -void WEAK sdio_irqhandler(void); -void WEAK lcd_irqhandler(void); -void WEAK usb0_irqhandler(void); -void WEAK usb1_irqhandler(void); -void WEAK sct_irqhandler(void); -void WEAK ritimer_irqhandler(void); -void WEAK timer0_irqhandler(void); -void WEAK timer1_irqhandler(void); -void WEAK timer2_irqhandler(void); -void WEAK timer3_irqhandler(void); -void WEAK mcpwm_irqhandler(void); -void WEAK adc0_irqhandler(void); -void WEAK i2c0_irqhandler(void); -void WEAK i2c1_irqhandler(void); -void WEAK spi_irqhandler(void); -void WEAK adc1_irqhandler(void); -void WEAK ssp0_irqhandler(void); -void WEAK ssp1_irqhandler(void); -void WEAK usart0_irqhandler(void); -void WEAK uart1_irqhandler(void); -void WEAK usart2_irqhandler(void); -void WEAK usart3_irqhandler(void); -void WEAK i2s0_irqhandler(void); -void WEAK i2s1_irqhandler(void); -void WEAK spifi_irqhandler(void); -void WEAK sgpio_irqhandler(void); -void WEAK pin_int0_irqhandler(void); -void WEAK pin_int1_irqhandler(void); -void WEAK pin_int2_irqhandler(void); -void WEAK pin_int3_irqhandler(void); -void WEAK pin_int4_irqhandler(void); -void WEAK pin_int5_irqhandler(void); -void WEAK pin_int6_irqhandler(void); -void WEAK pin_int7_irqhandler(void); -void WEAK gint0_irqhandler(void); -void WEAK gint1_irqhandler(void); -void WEAK eventrouter_irqhandler(void); -void WEAK c_can1_irqhandler(void); -void WEAK atimer_irqhandler(void); -void WEAK rtc_irqhandler(void); -void WEAK wwdt_irqhandler(void); -void WEAK c_can0_irqhandler(void); -void WEAK qei_irqhandler(void); - -#pragma weak dac_irqhandler = null_handler -#pragma weak m0core_irqhandler = null_handler -#pragma weak dma_irqhandler = null_handler -#pragma weak ethernet_irqhandler = null_handler -#pragma weak sdio_irqhandler = null_handler -#pragma weak lcd_irqhandler = null_handler -#pragma weak usb0_irqhandler = null_handler -#pragma weak usb1_irqhandler = null_handler -#pragma weak sct_irqhandler = null_handler -#pragma weak ritimer_irqhandler = null_handler -#pragma weak timer0_irqhandler = null_handler -#pragma weak timer1_irqhandler = null_handler -#pragma weak timer2_irqhandler = null_handler -#pragma weak timer3_irqhandler = null_handler -#pragma weak mcpwm_irqhandler = null_handler -#pragma weak adc0_irqhandler = null_handler -#pragma weak i2c0_irqhandler = null_handler -#pragma weak i2c1_irqhandler = null_handler -#pragma weak spi_irqhandler = null_handler -#pragma weak adc1_irqhandler = null_handler -#pragma weak ssp0_irqhandler = null_handler -#pragma weak ssp1_irqhandler = null_handler -#pragma weak usart0_irqhandler = null_handler -#pragma weak uart1_irqhandler = null_handler -#pragma weak usart2_irqhandler = null_handler -#pragma weak usart3_irqhandler = null_handler -#pragma weak i2s0_irqhandler = null_handler -#pragma weak i2s1_irqhandler = null_handler -#pragma weak spifi_irqhandler = null_handler -#pragma weak sgpio_irqhandler = null_handler -#pragma weak pin_int0_irqhandler = null_handler -#pragma weak pin_int1_irqhandler = null_handler -#pragma weak pin_int2_irqhandler = null_handler -#pragma weak pin_int3_irqhandler = null_handler -#pragma weak pin_int4_irqhandler = null_handler -#pragma weak pin_int5_irqhandler = null_handler -#pragma weak pin_int6_irqhandler = null_handler -#pragma weak pin_int7_irqhandler = null_handler -#pragma weak gint0_irqhandler = null_handler -#pragma weak gint1_irqhandler = null_handler -#pragma weak eventrouter_irqhandler = null_handler -#pragma weak c_can1_irqhandler = null_handler -#pragma weak atimer_irqhandler = null_handler -#pragma weak rtc_irqhandler = null_handler -#pragma weak wwdt_irqhandler = null_handler -#pragma weak c_can0_irqhandler = null_handler -#pragma weak qei_irqhandler = null_handler - -#define IRQ_HANDLERS \ - dac_irqhandler, \ - m0core_irqhandler, \ - dma_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - ethernet_irqhandler, \ - sdio_irqhandler, \ - lcd_irqhandler, \ - usb0_irqhandler, \ - usb1_irqhandler, \ - sct_irqhandler, \ - ritimer_irqhandler, \ - timer0_irqhandler, \ - timer1_irqhandler, \ - timer2_irqhandler, \ - timer3_irqhandler, \ - mcpwm_irqhandler, \ - adc0_irqhandler, \ - i2c0_irqhandler, \ - i2c1_irqhandler, \ - spi_irqhandler, \ - adc1_irqhandler, \ - ssp0_irqhandler, \ - ssp1_irqhandler, \ - usart0_irqhandler, \ - uart1_irqhandler, \ - usart2_irqhandler, \ - usart3_irqhandler, \ - i2s0_irqhandler, \ - i2s1_irqhandler, \ - spifi_irqhandler, \ - sgpio_irqhandler, \ - pin_int0_irqhandler, \ - pin_int1_irqhandler, \ - pin_int2_irqhandler, \ - pin_int3_irqhandler, \ - pin_int4_irqhandler, \ - pin_int5_irqhandler, \ - pin_int6_irqhandler, \ - pin_int7_irqhandler, \ - gint0_irqhandler, \ - gint1_irqhandler, \ - eventrouter_irqhandler, \ - c_can1_irqhandler, \ - 0, /* reserved */ \ - 0, /* reserved */ \ - atimer_irqhandler, \ - rtc_irqhandler, \ - 0, /* reserved */ \ - wwdt_irqhandler, \ - 0, /* reserved */ \ - c_can0_irqhandler, \ - qei_irqhandler, - -#endif diff --git a/include/libopencm3/lpc43xx/irq.yaml b/include/libopencm3/lpc43xx/irq.yaml new file mode 100644 index 00000000..bc9536b0 --- /dev/null +++ b/include/libopencm3/lpc43xx/irq.yaml @@ -0,0 +1,55 @@ +includeguard: LIBOPENCM3_LPC43xx_NVIC_H +partname_humanreadable: LPC 43xx series +partname_doxygen: LPC43xx +irqs: + 0: dac + 1: m0core + 2: dma +# reserved: 3, 4 + 5: ethernet + 6: sdio + 7: lcd + 8: usb0 + 9: usb1 + 10: sct + 11: ritimer + 12: timer0 + 13: timer1 + 14: timer2 + 15: timer3 + 16: mcpwm + 17: adc0 + 18: i2c0 + 19: i2c1 + 20: spi + 21: adc1 + 22: ssp0 + 23: ssp1 + 24: usart0 + 25: uart1 + 26: usart2 + 27: usart3 + 28: i2s0 + 29: i2s1 + 30: spifi + 31: sgpio + 32: pin_int0 + 33: pin_int1 + 34: pin_int2 + 35: pin_int3 + 36: pin_int4 + 37: pin_int5 + 38: pin_int6 + 39: pin_int7 + 40: gint0 + 41: gint1 + 42: eventrouter + 43: c_can1 +# reserved: 44, 45 + 46: atimer + 47: rtc +# reserved: 48 + 49: wwdt +# reserved: 50 + 51: c_can0 + 52: qei diff --git a/include/libopencm3/lpc43xx/nvic.h b/include/libopencm3/lpc43xx/nvic.h deleted file mode 100644 index 0fc5cc67..00000000 --- a/include/libopencm3/lpc43xx/nvic.h +++ /dev/null @@ -1,68 +0,0 @@ -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Cortex M4 System Interrupts */ -#define NVIC_NMI_IRQ -14 -#define NVIC_HARD_FAULT_IRQ -13 -#define NVIC_MEM_MANAGE_IRQ -12 -#define NVIC_BUS_FAULT_IRQ -11 -#define NVIC_USAGE_FAULT_IRQ -10 -/* irq numbers -6 to -9 are reserved */ -#define NVIC_SV_CALL_IRQ -5 -#define DEBUG_MONITOR_IRQ -4 -/* irq number -3 reserved */ -#define NVIC_PENDSV_IRQ -2 -#define NVIC_SYSTICK_IRQ -1 - -/* LPC43xx M4 specific user interrupts */ -#define NVIC_M4_DAC_IRQ 0 -#define NVIC_M4_M0CORE_IRQ 1 -#define NVIC_M4_DMA_IRQ 2 -#define NVIC_M4_ETHERNET_IRQ 5 -#define NVIC_M4_SDIO_IRQ 6 -#define NVIC_M4_LCD_IRQ 7 -#define NVIC_M4_USB0_IRQ 8 -#define NVIC_M4_USB1_IRQ 9 -#define NVIC_M4_SCT_IRQ 10 -#define NVIC_M4_RITIMER_IRQ 11 -#define NVIC_M4_TIMER0_IRQ 12 -#define NVIC_M4_TIMER1_IRQ 13 -#define NVIC_M4_TIMER2_IRQ 14 -#define NVIC_M4_TIMER3_IRQ 15 -#define NVIC_M4_MCPWM_IRQ 16 -#define NVIC_M4_ADC0_IRQ 17 -#define NVIC_M4_I2C0_IRQ 18 -#define NVIC_M4_I2C1_IRQ 19 -#define NVIC_M4_SPI_IRQ 20 -#define NVIC_M4_ADC1_IRQ 21 -#define NVIC_M4_SSP0_IRQ 22 -#define NVIC_M4_SSP1_IRQ 23 -#define NVIC_M4_USART0_IRQ 24 -#define NVIC_M4_UART1_IRQ 25 -#define NVIC_M4_USART2_IRQ 26 -#define NVIC_M4_USART3_IRQ 27 -#define NVIC_M4_I2S0_IRQ 28 -#define NVIC_M4_I2S1_IRQ 29 -#define NVIC_M4_SPIFI_IRQ 30 -#define NVIC_M4_SGPIO_IRQ 31 -#define NVIC_M4_PIN_INT0_IRQ 32 -#define NVIC_M4_PIN_INT1_IRQ 33 -#define NVIC_M4_PIN_INT2_IRQ 34 -#define NVIC_M4_PIN_INT3_IRQ 35 -#define NVIC_M4_PIN_INT4_IRQ 36 -#define NVIC_M4_PIN_INT5_IRQ 37 -#define NVIC_M4_PIN_INT6_IRQ 38 -#define NVIC_M4_PIN_INT7_IRQ 39 -#define NVIC_M4_GINT0_IRQ 40 -#define NVIC_M4_GINT1_IRQ 41 -#define NVIC_M4_EVENTROUTER_IRQ 42 -#define NVIC_M4_C_CAN1_IRQ 43 -#define NVIC_M4_ATIMER_IRQ 46 -#define NVIC_M4_RTC_IRQ 47 -#define NVIC_M4_WWDT_IRQ 49 -#define NVIC_M4_C_CAN0_IRQ 51 -#define NVIC_M4_QEI_IRQ 52 - -#define NVIC_IRQ_COUNT 53 - -/* LPC43xx M0 specific user interrupts */ -//TODO diff --git a/include/libopencm3/stm32/f1/irq.h b/include/libopencm3/stm32/f1/irq.h deleted file mode 100644 index cfa07f1a..00000000 --- a/include/libopencm3/stm32/f1/irq.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F1_IRQ_H -#define LIBOPENCM3_STM32_F1_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMPER 2 -#define IRQ_RTC 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_CHANNEL1 11 -#define IRQ_DMA1_CHANNEL2 12 -#define IRQ_DMA1_CHANNEL3 13 -#define IRQ_DMA1_CHANNEL4 14 -#define IRQ_DMA1_CHANNEL5 15 -#define IRQ_DMA1_CHANNEL6 16 -#define IRQ_DMA1_CHANNEL7 17 -#define IRQ_ADC1_2 18 -#define IRQ_USB_HP_CAN_TX 19 -#define IRQ_USB_LP_CAN_RX0 20 -#define IRQ_CAN_RX1 21 -#define IRQ_CAN_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK 24 -#define IRQ_TIM1_UP 25 -#define IRQ_TIM1_TRG_COM 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_WAKEUP 42 -#define IRQ_TIM8_BRK 43 -#define IRQ_TIM8_UP 44 -#define IRQ_TIM8_TRG_COM 45 -#define IRQ_TIM8_CC 46 -#define IRQ_ADC3 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_CHANNEL1 56 -#define IRQ_DMA2_CHANNEL2 57 -#define IRQ_DMA2_CHANNEL3 58 -#define IRQ_DMA2_CHANNEL4_5 59 -#define IRQ_DMA2_CHANNEL5 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 - -/* FIXME: number from list in lib/stm32/f1/vector.c, might miss irqs */ -#define IRQ_COUNT 68 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamper_isr(void); -void WEAK rtc_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_channel1_isr(void); -void WEAK dma1_channel2_isr(void); -void WEAK dma1_channel3_isr(void); -void WEAK dma1_channel4_isr(void); -void WEAK dma1_channel5_isr(void); -void WEAK dma1_channel6_isr(void); -void WEAK dma1_channel7_isr(void); -void WEAK adc1_2_isr(void); -void WEAK usb_hp_can_tx_isr(void); -void WEAK usb_lp_can_rx0_isr(void); -void WEAK can_rx1_isr(void); -void WEAK can_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_isr(void); -void WEAK tim1_up_isr(void); -void WEAK tim1_trg_com_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_wakeup_isr(void); -void WEAK tim8_brk_isr(void); -void WEAK tim8_up_isr(void); -void WEAK tim8_trg_com_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK adc3_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_channel1_isr(void); -void WEAK dma2_channel2_isr(void); -void WEAK dma2_channel3_isr(void); -void WEAK dma2_channel4_5_isr(void); -void WEAK dma2_channel5_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamper_isr = null_handler -#pragma weak rtc_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_channel1_isr = null_handler -#pragma weak dma1_channel2_isr = null_handler -#pragma weak dma1_channel3_isr = null_handler -#pragma weak dma1_channel4_isr = null_handler -#pragma weak dma1_channel5_isr = null_handler -#pragma weak dma1_channel6_isr = null_handler -#pragma weak dma1_channel7_isr = null_handler -#pragma weak adc1_2_isr = null_handler -#pragma weak usb_hp_can_tx_isr = null_handler -#pragma weak usb_lp_can_rx0_isr = null_handler -#pragma weak can_rx1_isr = null_handler -#pragma weak can_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_isr = null_handler -#pragma weak tim1_up_isr = null_handler -#pragma weak tim1_trg_com_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_wakeup_isr = null_handler -#pragma weak tim8_brk_isr = null_handler -#pragma weak tim8_up_isr = null_handler -#pragma weak tim8_trg_com_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak adc3_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_channel1_isr = null_handler -#pragma weak dma2_channel2_isr = null_handler -#pragma weak dma2_channel3_isr = null_handler -#pragma weak dma2_channel4_5_isr = null_handler -#pragma weak dma2_channel5_isr -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamper_isr, \ - rtc_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_channel1_isr, \ - dma1_channel2_isr, \ - dma1_channel3_isr, \ - dma1_channel4_isr, \ - dma1_channel5_isr, \ - dma1_channel6_isr, \ - dma1_channel7_isr, \ - adc1_2_isr, \ - usb_hp_can_tx_isr, \ - usb_lp_can_rx0_isr, \ - can_rx1_isr, \ - can_sce_isr, \ - exti9_5_isr, \ - tim1_brk_isr, \ - tim1_up_isr, \ - tim1_trg_com_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_wakeup_isr, \ - tim8_brk_isr, \ - tim8_up_isr, \ - tim8_trg_com_isr, \ - tim8_cc_isr, \ - adc3_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_isr, \ - tim7_isr, \ - dma2_channel1_isr, \ - dma2_channel2_isr, \ - dma2_channel3_isr, \ - dma2_channel4_5_isr, \ - dma2_channel5_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - -#endif diff --git a/include/libopencm3/stm32/f1/irq.yaml b/include/libopencm3/stm32/f1/irq.yaml new file mode 100644 index 00000000..14cbcc03 --- /dev/null +++ b/include/libopencm3/stm32/f1/irq.yaml @@ -0,0 +1,72 @@ +includeguard: LIBOPENCM3_STM32_F1_NVIC_H +partname_humanreadable: STM32 F1 series +partname_doxygen: STM32F1 +irqs: + - wwdg + - pvd + - tamper + - rtc + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_channel1 + - dma1_channel2 + - dma1_channel3 + - dma1_channel4 + - dma1_channel5 + - dma1_channel6 + - dma1_channel7 + - adc1_2 + - usb_hp_can_tx + - usb_lp_can_rx0 + - can_rx1 + - can_sce + - exti9_5 + - tim1_brk + - tim1_up + - tim1_trg_com + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_wakeup + - tim8_brk + - tim8_up + - tim8_trg_com + - tim8_cc + - adc3 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6 + - tim7 + - dma2_channel1 + - dma2_channel2 + - dma2_channel3 + - dma2_channel4_5 + - dma2_channel5 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs diff --git a/include/libopencm3/stm32/f1/nvic_f1.h b/include/libopencm3/stm32/f1/nvic_f1.h deleted file mode 100644 index 1544e4fc..00000000 --- a/include/libopencm3/stm32/f1/nvic_f1.h +++ /dev/null @@ -1,116 +0,0 @@ -/** @brief Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F1_H -#define LIBOPENCM3_NVIC_F1_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F1 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts -@ingroup STM32F_nvic_defines - -@{*/ -#define NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMPER_IRQ 2 -#define NVIC_RTC_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_CHANNEL1_IRQ 11 -#define NVIC_DMA1_CHANNEL2_IRQ 12 -#define NVIC_DMA1_CHANNEL3_IRQ 13 -#define NVIC_DMA1_CHANNEL4_IRQ 14 -#define NVIC_DMA1_CHANNEL5_IRQ 15 -#define NVIC_DMA1_CHANNEL6_IRQ 16 -#define NVIC_DMA1_CHANNEL7_IRQ 17 -#define NVIC_ADC1_2_IRQ 18 -#define NVIC_USB_HP_CAN_TX_IRQ 19 -#define NVIC_USB_LP_CAN_RX0_IRQ 20 -#define NVIC_CAN_RX1_IRQ 21 -#define NVIC_CAN_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_IRQ 24 -#define NVIC_TIM1_UP_IRQ 25 -#define NVIC_TIM1_TRG_COM_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_WAKEUP_IRQ 42 -#define NVIC_TIM8_BRK_IRQ 43 -#define NVIC_TIM8_UP_IRQ 44 -#define NVIC_TIM8_TRG_COM_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_ADC3_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_CHANNEL1_IRQ 56 -#define NVIC_DMA2_CHANNEL2_IRQ 57 -#define NVIC_DMA2_CHANNEL3_IRQ 58 -#define NVIC_DMA2_CHANNEL4_5_IRQ 59 -#define NVIC_DMA2_CHANNEL5_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 - -#define NVIC_IRQ_COUNT 68 -/**@}*/ - -#endif diff --git a/include/libopencm3/stm32/f2/irq.h b/include/libopencm3/stm32/f2/irq.h deleted file mode 100644 index 7aec1421..00000000 --- a/include/libopencm3/stm32/f2/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F2_IRQ_H -#define LIBOPENCM3_STM32_F2_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f2/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f2/irq.yaml b/include/libopencm3/stm32/f2/irq.yaml new file mode 100644 index 00000000..c3600b36 --- /dev/null +++ b/include/libopencm3/stm32/f2/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F2_NVIC_H +partname_humanreadable: STM32 F2 series +partname_doxygen: STM32F2 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f2/nvic_f2.h b/include/libopencm3/stm32/f2/nvic_f2.h deleted file mode 100644 index 65a990db..00000000 --- a/include/libopencm3/stm32/f2/nvic_f2.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F2_H -#define LIBOPENCM3_NVIC_F2_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F2 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/include/libopencm3/stm32/f4/irq.h b/include/libopencm3/stm32/f4/irq.h deleted file mode 100644 index 4f4f5e54..00000000 --- a/include/libopencm3/stm32/f4/irq.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Piotr Esden-Tempski - * Copyright (C) 2011 Fergus Noble - * Copyright (C) 2012 chrysn - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_STM32_F4_IRQ_H -#define LIBOPENCM3_STM32_F4_IRQ_H - -#define IRQ_WWDG 0 -#define IRQ_PVD 1 -#define IRQ_TAMP_STAMP 2 -#define IRQ_RTC_WKUP 3 -#define IRQ_FLASH 4 -#define IRQ_RCC 5 -#define IRQ_EXTI0 6 -#define IRQ_EXTI1 7 -#define IRQ_EXTI2 8 -#define IRQ_EXTI3 9 -#define IRQ_EXTI4 10 -#define IRQ_DMA1_STREAM0 11 -#define IRQ_DMA1_STREAM1 12 -#define IRQ_DMA1_STREAM2 13 -#define IRQ_DMA1_STREAM3 14 -#define IRQ_DMA1_STREAM4 15 -#define IRQ_DMA1_STREAM5 16 -#define IRQ_DMA1_STREAM6 17 -#define IRQ_ADC 18 -#define IRQ_CAN1_TX 19 -#define IRQ_CAN1_RX0 20 -#define IRQ_CAN1_RX1 21 -#define IRQ_CAN1_SCE 22 -#define IRQ_EXTI9_5 23 -#define IRQ_TIM1_BRK_TIM9 24 -#define IRQ_TIM1_UP_TIM10 25 -#define IRQ_TIM1_TRG_COM_TIM11 26 -#define IRQ_TIM1_CC 27 -#define IRQ_TIM2 28 -#define IRQ_TIM3 29 -#define IRQ_TIM4 30 -#define IRQ_I2C1_EV 31 -#define IRQ_I2C1_ER 32 -#define IRQ_I2C2_EV 33 -#define IRQ_I2C2_ER 34 -#define IRQ_SPI1 35 -#define IRQ_SPI2 36 -#define IRQ_USART1 37 -#define IRQ_USART2 38 -#define IRQ_USART3 39 -#define IRQ_EXTI15_10 40 -#define IRQ_RTC_ALARM 41 -#define IRQ_USB_FS_WKUP 42 -#define IRQ_TIM8_BRK_TIM12 43 -#define IRQ_TIM8_UP_TIM13 44 -#define IRQ_TIM8_TRG_COM_TIM14 45 -#define IRQ_TIM8_CC 46 -#define IRQ_DMA1_STREAM7 47 -#define IRQ_FSMC 48 -#define IRQ_SDIO 49 -#define IRQ_TIM5 50 -#define IRQ_SPI3 51 -#define IRQ_UART4 52 -#define IRQ_UART5 53 -#define IRQ_TIM6_DAC 54 -#define IRQ_TIM7 55 -#define IRQ_DMA2_STREAM0 56 -#define IRQ_DMA2_STREAM1 57 -#define IRQ_DMA2_STREAM2 58 -#define IRQ_DMA2_STREAM3 59 -#define IRQ_DMA2_STREAM4 60 -#define IRQ_ETH 61 -#define IRQ_ETH_WKUP 62 -#define IRQ_CAN2_TX 63 -#define IRQ_CAN2_RX0 64 -#define IRQ_CAN2_RX1 65 -#define IRQ_CAN2_SCE 66 -#define IRQ_OTG_FS 67 -#define IRQ_DMA2_STREAM5 68 -#define IRQ_DMA2_STREAM6 69 -#define IRQ_DMA2_STREAM7 70 -#define IRQ_USART6 71 -#define IRQ_I2C3_EV 72 -#define IRQ_I2C3_ER 73 -#define IRQ_OTG_HS_EP1_OUT 74 -#define IRQ_OTG_HS_EP1_IN 75 -#define IRQ_OTG_HS_WKUP 76 -#define IRQ_OTG_HS 77 -#define IRQ_DCMI 78 -#define IRQ_CRYP 79 -#define IRQ_HASH_RNG 80 - -/* FIXME: number from list in lib/stm32/f4/vector.c, might miss irqs */ -#define IRQ_COUNT 81 - -#define WEAK __attribute__ ((weak)) - -void WEAK wwdg_isr(void); -void WEAK pvd_isr(void); -void WEAK tamp_stamp_isr(void); -void WEAK rtc_wkup_isr(void); -void WEAK flash_isr(void); -void WEAK rcc_isr(void); -void WEAK exti0_isr(void); -void WEAK exti1_isr(void); -void WEAK exti2_isr(void); -void WEAK exti3_isr(void); -void WEAK exti4_isr(void); -void WEAK dma1_stream0_isr(void); -void WEAK dma1_stream1_isr(void); -void WEAK dma1_stream2_isr(void); -void WEAK dma1_stream3_isr(void); -void WEAK dma1_stream4_isr(void); -void WEAK dma1_stream5_isr(void); -void WEAK dma1_stream6_isr(void); -void WEAK adc_isr(void); -void WEAK can1_tx_isr(void); -void WEAK can1_rx0_isr(void); -void WEAK can1_rx1_isr(void); -void WEAK can1_sce_isr(void); -void WEAK exti9_5_isr(void); -void WEAK tim1_brk_tim9_isr(void); -void WEAK tim1_up_tim10_isr(void); -void WEAK tim1_trg_com_tim11_isr(void); -void WEAK tim1_cc_isr(void); -void WEAK tim2_isr(void); -void WEAK tim3_isr(void); -void WEAK tim4_isr(void); -void WEAK i2c1_ev_isr(void); -void WEAK i2c1_er_isr(void); -void WEAK i2c2_ev_isr(void); -void WEAK i2c2_er_isr(void); -void WEAK spi1_isr(void); -void WEAK spi2_isr(void); -void WEAK usart1_isr(void); -void WEAK usart2_isr(void); -void WEAK usart3_isr(void); -void WEAK exti15_10_isr(void); -void WEAK rtc_alarm_isr(void); -void WEAK usb_fs_wkup_isr(void); -void WEAK tim8_brk_tim12_isr(void); -void WEAK tim8_up_tim13_isr(void); -void WEAK tim8_trg_com_tim14_isr(void); -void WEAK tim8_cc_isr(void); -void WEAK dma1_stream7_isr(void); -void WEAK fsmc_isr(void); -void WEAK sdio_isr(void); -void WEAK tim5_isr(void); -void WEAK spi3_isr(void); -void WEAK uart4_isr(void); -void WEAK uart5_isr(void); -void WEAK tim6_dac_isr(void); -void WEAK tim7_isr(void); -void WEAK dma2_stream0_isr(void); -void WEAK dma2_stream1_isr(void); -void WEAK dma2_stream2_isr(void); -void WEAK dma2_stream3_isr(void); -void WEAK dma2_stream4_isr(void); -void WEAK eth_isr(void); -void WEAK eth_wkup_isr(void); -void WEAK can2_tx_isr(void); -void WEAK can2_rx0_isr(void); -void WEAK can2_rx1_isr(void); -void WEAK can2_sce_isr(void); -void WEAK otg_fs_isr(void); -void WEAK dma2_stream5_isr(void); -void WEAK dma2_stream6_isr(void); -void WEAK dma2_stream7_isr(void); -void WEAK usart6_isr(void); -void WEAK i2c3_ev_isr(void); -void WEAK i2c3_er_isr(void); -void WEAK otg_hs_ep1_out_isr(void); -void WEAK otg_hs_ep1_in_isr(void); -void WEAK otg_hs_wkup_isr(void); -void WEAK otg_hs_isr(void); -void WEAK dcmi_isr(void); -void WEAK cryp_isr(void); -void WEAK hash_rng_isr(void); - -#pragma weak wwdg_isr = null_handler -#pragma weak pvd_isr = null_handler -#pragma weak tamp_stamp_isr = null_handler -#pragma weak rtc_wkup_isr = null_handler -#pragma weak flash_isr = null_handler -#pragma weak rcc_isr = null_handler -#pragma weak exti0_isr = null_handler -#pragma weak exti1_isr = null_handler -#pragma weak exti2_isr = null_handler -#pragma weak exti3_isr = null_handler -#pragma weak exti4_isr = null_handler -#pragma weak dma1_stream0_isr = null_handler -#pragma weak dma1_stream1_isr = null_handler -#pragma weak dma1_stream2_isr = null_handler -#pragma weak dma1_stream3_isr = null_handler -#pragma weak dma1_stream4_isr = null_handler -#pragma weak dma1_stream5_isr = null_handler -#pragma weak dma1_stream6_isr = null_handler -#pragma weak adc_isr = null_handler -#pragma weak can1_tx_isr = null_handler -#pragma weak can1_rx0_isr = null_handler -#pragma weak can1_rx1_isr = null_handler -#pragma weak can1_sce_isr = null_handler -#pragma weak exti9_5_isr = null_handler -#pragma weak tim1_brk_tim9_isr = null_handler -#pragma weak tim1_up_tim10_isr = null_handler -#pragma weak tim1_trg_com_tim11_isr = null_handler -#pragma weak tim1_cc_isr = null_handler -#pragma weak tim2_isr = null_handler -#pragma weak tim3_isr = null_handler -#pragma weak tim4_isr = null_handler -#pragma weak i2c1_ev_isr = null_handler -#pragma weak i2c1_er_isr = null_handler -#pragma weak i2c2_ev_isr = null_handler -#pragma weak i2c2_er_isr = null_handler -#pragma weak spi1_isr = null_handler -#pragma weak spi2_isr = null_handler -#pragma weak usart1_isr = null_handler -#pragma weak usart2_isr = null_handler -#pragma weak usart3_isr = null_handler -#pragma weak exti15_10_isr = null_handler -#pragma weak rtc_alarm_isr = null_handler -#pragma weak usb_fs_wkup_isr = null_handler -#pragma weak tim8_brk_tim12_isr = null_handler -#pragma weak tim8_up_tim13_isr = null_handler -#pragma weak tim8_trg_com_tim14_isr = null_handler -#pragma weak tim8_cc_isr = null_handler -#pragma weak dma1_stream7_isr = null_handler -#pragma weak fsmc_isr = null_handler -#pragma weak sdio_isr = null_handler -#pragma weak tim5_isr = null_handler -#pragma weak spi3_isr = null_handler -#pragma weak uart4_isr = null_handler -#pragma weak uart5_isr = null_handler -#pragma weak tim6_dac_isr = null_handler -#pragma weak tim7_isr = null_handler -#pragma weak dma2_stream0_isr = null_handler -#pragma weak dma2_stream1_isr = null_handler -#pragma weak dma2_stream2_isr = null_handler -#pragma weak dma2_stream3_isr = null_handler -#pragma weak dma2_stream4_isr = null_handler -#pragma weak eth_isr = null_handler -#pragma weak eth_wkup_isr = null_handler -#pragma weak can2_tx_isr = null_handler -#pragma weak can2_rx0_isr = null_handler -#pragma weak can2_rx1_isr = null_handler -#pragma weak can2_sce_isr = null_handler -#pragma weak otg_fs_isr = null_handler -#pragma weak dma2_stream5_isr = null_handler -#pragma weak dma2_stream6_isr = null_handler -#pragma weak dma2_stream7_isr = null_handler -#pragma weak usart6_isr = null_handler -#pragma weak i2c3_ev_isr = null_handler -#pragma weak i2c3_er_isr = null_handler -#pragma weak otg_hs_ep1_out_isr = null_handler -#pragma weak otg_hs_ep1_in_isr = null_handler -#pragma weak otg_hs_wkup_isr = null_handler -#pragma weak otg_hs_isr = null_handler -#pragma weak dcmi_isr = null_handler -#pragma weak cryp_isr = null_handler -#pragma weak hash_rng_isr = null_handler - -#define IRQ_HANDLERS \ - wwdg_isr, \ - pvd_isr, \ - tamp_stamp_isr, \ - rtc_wkup_isr, \ - flash_isr, \ - rcc_isr, \ - exti0_isr, \ - exti1_isr, \ - exti2_isr, \ - exti3_isr, \ - exti4_isr, \ - dma1_stream0_isr, \ - dma1_stream1_isr, \ - dma1_stream2_isr, \ - dma1_stream3_isr, \ - dma1_stream4_isr, \ - dma1_stream5_isr, \ - dma1_stream6_isr, \ - adc_isr, \ - can1_tx_isr, \ - can1_rx0_isr, \ - can1_rx1_isr, \ - can1_sce_isr, \ - exti9_5_isr, \ - tim1_brk_tim9_isr, \ - tim1_up_tim10_isr, \ - tim1_trg_com_tim11_isr, \ - tim1_cc_isr, \ - tim2_isr, \ - tim3_isr, \ - tim4_isr, \ - i2c1_ev_isr, \ - i2c1_er_isr, \ - i2c2_ev_isr, \ - i2c2_er_isr, \ - spi1_isr, \ - spi2_isr, \ - usart1_isr, \ - usart2_isr, \ - usart3_isr, \ - exti15_10_isr, \ - rtc_alarm_isr, \ - usb_fs_wkup_isr, \ - tim8_brk_tim12_isr, \ - tim8_up_tim13_isr, \ - tim8_trg_com_tim14_isr, \ - tim8_cc_isr, \ - dma1_stream7_isr, \ - fsmc_isr, \ - sdio_isr, \ - tim5_isr, \ - spi3_isr, \ - uart4_isr, \ - uart5_isr, \ - tim6_dac_isr, \ - tim7_isr, \ - dma2_stream0_isr, \ - dma2_stream1_isr, \ - dma2_stream2_isr, \ - dma2_stream3_isr, \ - dma2_stream4_isr, \ - eth_isr, \ - eth_wkup_isr, \ - can2_tx_isr, \ - can2_rx0_isr, \ - can2_rx1_isr, \ - can2_sce_isr, \ - otg_fs_isr, \ - dma2_stream5_isr, \ - dma2_stream6_isr, \ - dma2_stream7_isr, \ - usart6_isr, \ - i2c3_ev_isr, \ - i2c3_er_isr, \ - otg_hs_ep1_out_isr, \ - otg_hs_ep1_in_isr, \ - otg_hs_wkup_isr, \ - otg_hs_isr, \ - dcmi_isr, \ - cryp_isr, \ - hash_rng_isr, - -#endif diff --git a/include/libopencm3/stm32/f4/irq.yaml b/include/libopencm3/stm32/f4/irq.yaml new file mode 100644 index 00000000..2d4bae9e --- /dev/null +++ b/include/libopencm3/stm32/f4/irq.yaml @@ -0,0 +1,85 @@ +includeguard: LIBOPENCM3_STM32_F4_NVIC_H +partname_humanreadable: STM32 F4 series +partname_doxygen: STM32F4 +irqs: + - nvic_wwdg + - pvd + - tamp_stamp + - rtc_wkup + - flash + - rcc + - exti0 + - exti1 + - exti2 + - exti3 + - exti4 + - dma1_stream0 + - dma1_stream1 + - dma1_stream2 + - dma1_stream3 + - dma1_stream4 + - dma1_stream5 + - dma1_stream6 + - adc + - can1_tx + - can1_rx0 + - can1_rx1 + - can1_sce + - exti9_5 + - tim1_brk_tim9 + - tim1_up_tim10 + - tim1_trg_com_tim11 + - tim1_cc + - tim2 + - tim3 + - tim4 + - i2c1_ev + - i2c1_er + - i2c2_ev + - i2c2_er + - spi1 + - spi2 + - usart1 + - usart2 + - usart3 + - exti15_10 + - rtc_alarm + - usb_fs_wkup + - tim8_brk_tim12 + - tim8_up_tim13 + - tim8_trg_com_tim14 + - tim8_cc + - dma1_stream7 + - fsmc + - sdio + - tim5 + - spi3 + - uart4 + - uart5 + - tim6_dac + - tim7 + - dma2_stream0 + - dma2_stream1 + - dma2_stream2 + - dma2_stream3 + - dma2_stream4 + - eth + - eth_wkup + - can2_tx + - can2_rx0 + - can2_rx1 + - can2_sce + - otg_fs + - dma2_stream5 + - dma2_stream6 + - dma2_stream7 + - usart6 + - i2c3_ev + - i2c3_er + - otg_hs_ep1_out + - otg_hs_ep1_in + - otg_hs_wkup + - otg_hs + - dcmi + - cryp + - hash_rng diff --git a/include/libopencm3/stm32/f4/nvic_f4.h b/include/libopencm3/stm32/f4/nvic_f4.h deleted file mode 100644 index 013e3b5d..00000000 --- a/include/libopencm3/stm32/f4/nvic_f4.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2011 Fergus Noble - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_NVIC_F4_H -#define LIBOPENCM3_NVIC_F4_H - -/* --- IRQ channel numbers-------------------------------------------------- */ - -/* Note: These F4 specific user interrupt definitions supplement the - * general NVIC definitions in ../nvic.h - */ - -/* User Interrupts */ -#define NVIC_NVIC_WWDG_IRQ 0 -#define NVIC_PVD_IRQ 1 -#define NVIC_TAMP_STAMP_IRQ 2 -#define NVIC_RTC_WKUP_IRQ 3 -#define NVIC_FLASH_IRQ 4 -#define NVIC_RCC_IRQ 5 -#define NVIC_EXTI0_IRQ 6 -#define NVIC_EXTI1_IRQ 7 -#define NVIC_EXTI2_IRQ 8 -#define NVIC_EXTI3_IRQ 9 -#define NVIC_EXTI4_IRQ 10 -#define NVIC_DMA1_STREAM0_IRQ 11 -#define NVIC_DMA1_STREAM1_IRQ 12 -#define NVIC_DMA1_STREAM2_IRQ 13 -#define NVIC_DMA1_STREAM3_IRQ 14 -#define NVIC_DMA1_STREAM4_IRQ 15 -#define NVIC_DMA1_STREAM5_IRQ 16 -#define NVIC_DMA1_STREAM6_IRQ 17 -#define NVIC_ADC_IRQ 18 -#define NVIC_CAN1_TX_IRQ 19 -#define NVIC_CAN1_RX0_IRQ 20 -#define NVIC_CAN1_RX1_IRQ 21 -#define NVIC_CAN1_SCE_IRQ 22 -#define NVIC_EXTI9_5_IRQ 23 -#define NVIC_TIM1_BRK_TIM9_IRQ 24 -#define NVIC_TIM1_UP_TIM10_IRQ 25 -#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26 -#define NVIC_TIM1_CC_IRQ 27 -#define NVIC_TIM2_IRQ 28 -#define NVIC_TIM3_IRQ 29 -#define NVIC_TIM4_IRQ 30 -#define NVIC_I2C1_EV_IRQ 31 -#define NVIC_I2C1_ER_IRQ 32 -#define NVIC_I2C2_EV_IRQ 33 -#define NVIC_I2C2_ER_IRQ 34 -#define NVIC_SPI1_IRQ 35 -#define NVIC_SPI2_IRQ 36 -#define NVIC_USART1_IRQ 37 -#define NVIC_USART2_IRQ 38 -#define NVIC_USART3_IRQ 39 -#define NVIC_EXTI15_10_IRQ 40 -#define NVIC_RTC_ALARM_IRQ 41 -#define NVIC_USB_FS_WKUP_IRQ 42 -#define NVIC_TIM8_BRK_TIM12_IRQ 43 -#define NVIC_TIM8_UP_TIM13_IRQ 44 -#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45 -#define NVIC_TIM8_CC_IRQ 46 -#define NVIC_DMA1_STREAM7_IRQ 47 -#define NVIC_FSMC_IRQ 48 -#define NVIC_SDIO_IRQ 49 -#define NVIC_TIM5_IRQ 50 -#define NVIC_SPI3_IRQ 51 -#define NVIC_UART4_IRQ 52 -#define NVIC_UART5_IRQ 53 -#define NVIC_TIM6_DAC_IRQ 54 -#define NVIC_TIM7_IRQ 55 -#define NVIC_DMA2_STREAM0_IRQ 56 -#define NVIC_DMA2_STREAM1_IRQ 57 -#define NVIC_DMA2_STREAM2_IRQ 58 -#define NVIC_DMA2_STREAM3_IRQ 59 -#define NVIC_DMA2_STREAM4_IRQ 60 -#define NVIC_ETH_IRQ 61 -#define NVIC_ETH_WKUP_IRQ 62 -#define NVIC_CAN2_TX_IRQ 63 -#define NVIC_CAN2_RX0_IRQ 64 -#define NVIC_CAN2_RX1_IRQ 65 -#define NVIC_CAN2_SCE_IRQ 66 -#define NVIC_OTG_FS_IRQ 67 -#define NVIC_DMA2_STREAM5_IRQ 68 -#define NVIC_DMA2_STREAM6_IRQ 69 -#define NVIC_DMA2_STREAM7_IRQ 70 -#define NVIC_USART6_IRQ 71 -#define NVIC_I2C3_EV_IRQ 72 -#define NVIC_I2C3_ER_IRQ 73 -#define NVIC_OTG_HS_EP1_OUT_IRQ 74 -#define NVIC_OTG_HS_EP1_IN_IRQ 75 -#define NVIC_OTG_HS_WKUP_IRQ 76 -#define NVIC_OTG_HS_IRQ 77 -#define NVIC_DCMI_IRQ 78 -#define NVIC_CRYP_IRQ 79 -#define NVIC_HASH_RNG_IRQ 80 - -#define NVIC_IRQ_COUNT 81 - -#endif diff --git a/include/libopencm3/efm32/tinygecko/irq2nvic_h b/scripts/irq2nvic_h similarity index 81% rename from include/libopencm3/efm32/tinygecko/irq2nvic_h rename to scripts/irq2nvic_h index a7df16e6..9346e9bf 100755 --- a/include/libopencm3/efm32/tinygecko/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -17,6 +17,15 @@ # You should have received a copy of the GNU Lesser General Public License # along with this library. If not, see . +"""Generate an nvic.h header from a small YAML file describing the interrupt +numbers. + +Code generation is chosen here because the resulting C code needs to be very +repetetive (definition of the IRQ numbers, function prototypes, weak fallback +definition and vector table definition), all being very repetitive. No portable +method to achive the same thing with C preprocessor is known to the author. +(Neither is any non-portable method, for that matter.)""" + import sys import yaml @@ -77,8 +86,12 @@ def convert(infile, outfile): irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) irqnames = [v for (k,v) in irq2name] + if isinstance(data['irqs'], list): + data['irqcount'] = len(irq2name) + else: + data['irqcount'] = max(data['irqs'].keys()) + 1 + data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name) - data['irqcount'] = len(irq2name) # FIXME: what if it's a sparse dictionary? data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames) data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) From ae832b4ee87f2cf94b29f790bc04d7b570109919 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:30:18 +0200 Subject: [PATCH 34/35] split irq.yaml output in nvic.h and vector_nvic.h the weak pragmas need to be used in the very compilation unit where their target is defined, requiring another dispatch --- include/libopencm3/dispatch/nvic.h | 1 - lib/cm3/vector.c | 2 ++ scripts/irq2nvic_h | 29 +++++++++++++++++++++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 67ba5448..d8e7889a 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -15,6 +15,5 @@ # warning"no chipset defined; user interrupts are disabled" #define NVIC_IRQ_COUNT 0 -#define IRQ_HANDLERS #endif diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 7b660f90..e0c29721 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -22,6 +22,8 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" +/* load the weak symbols for IRQ_HANDLERS */ +#include #define WEAK __attribute__ ((weak)) diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index 9346e9bf..fc5e5717 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -29,7 +29,7 @@ method to achive the same thing with C preprocessor is known to the author. import sys import yaml -template = '''\ +template_nvic_h = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -38,6 +38,8 @@ template = '''\ #ifndef {includeguard} #define {includeguard} +#include + /** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @@ -60,6 +62,19 @@ template = '''\ /**@}}*/ +#endif /* {includeguard} */ +''' + +template_vector_nvic_h = '''\ +/* This file is part of the libopencm3 project. + * + * It was generated by the irq2nvic_h script. + * + * This part needs to get included in the compilation unit where + * blocking_handler gets defined due to the way #pragma works. + */ + + /** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable} @ingroup CM3_nvic_isrpragmas @@ -76,11 +91,9 @@ template = '''\ #define IRQ_HANDLERS \\ {vectortableinitialization} - -#endif /* {includeguard} */ ''' -def convert(infile, outfile): +def convert(infile, outfile_nvic, outfile_vectornvic): data = yaml.load(infile) irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items()) @@ -96,10 +109,14 @@ def convert(infile, outfile): data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) - outfile.write(template.format(**data)) + outfile_nvic.write(template_nvic_h.format(**data)) + # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file + # in lib/, but that'd spread this mechanism over the whole library; just + # needs some thingking over + outfile_vectornvic.write(template_vector_nvic_h.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w')) + convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) if __name__ == "__main__": main() From c69916ffb6d515b1dd644830ba27daef4fc75b58 Mon Sep 17 00:00:00 2001 From: chrysn Date: Thu, 18 Oct 2012 17:57:59 +0200 Subject: [PATCH 35/35] integrate irq2nvic_h script in buildprocess --- Makefile | 8 +++++++- include/libopencm3/efm32/tinygecko/Makefile | 2 -- lib/cm3/vector.c | 2 +- lib/dispatch/vector_nvic.c | 19 +++++++++++++++++++ scripts/irq2nvic_h | 14 ++++++++------ 5 files changed, 35 insertions(+), 10 deletions(-) delete mode 100644 include/libopencm3/efm32/tinygecko/Makefile create mode 100644 lib/dispatch/vector_nvic.c diff --git a/Makefile b/Makefile index 492b618e..76c302d0 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,13 @@ all: build build: lib examples -lib: +generatedheaders: + @printf " UPDATING HEADERS\n" + $(Q)for yamlfile in `find -name 'irq.yaml'`; do \ + ./scripts/irq2nvic_h $$yamlfile ; \ + done + +lib: generatedheaders $(Q)for i in $(addprefix $@/,$(TARGETS)); do \ if [ -d $$i ]; then \ printf " BUILD $$i\n"; \ diff --git a/include/libopencm3/efm32/tinygecko/Makefile b/include/libopencm3/efm32/tinygecko/Makefile deleted file mode 100644 index 4ac53477..00000000 --- a/include/libopencm3/efm32/tinygecko/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -nvic.h: irq.yaml - ./irq2nvic_h diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index e0c29721..a6d2e934 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -23,7 +23,7 @@ /* load optional platform dependent initialization routines */ #include "../dispatch/vector.c" /* load the weak symbols for IRQ_HANDLERS */ -#include +#include "../dispatch/vector_nvic.c" #define WEAK __attribute__ ((weak)) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c new file mode 100644 index 00000000..fc5fdd2a --- /dev/null +++ b/lib/dispatch/vector_nvic.c @@ -0,0 +1,19 @@ +#if defined(STM32F1) +# include "../stm32/f1/vector_nvic.c" +#elif defined(STM32F2) +# include "../stm32/f2/vector_nvic.c" +#elif defined(STM32F4) +# include "../stm32/f4/vector_nvic.c" + +#elif defined(TINYGECKO) +# include "../efm32/tinygecko/vector_nvic.c" + +#elif defined(LPC43XX) +# include "../lpc43xx/vector_nvic.c" + +#else +# warning"no chipset defined; user interrupts are disabled" + +#define IRQ_HANDLERS + +#endif diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index fc5e5717..92d63b85 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -65,7 +65,7 @@ template_nvic_h = '''\ #endif /* {includeguard} */ ''' -template_vector_nvic_h = '''\ +template_vector_nvic_c = '''\ /* This file is part of the libopencm3 project. * * It was generated by the irq2nvic_h script. @@ -110,13 +110,15 @@ def convert(infile, outfile_nvic, outfile_vectornvic): data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) outfile_nvic.write(template_nvic_h.format(**data)) - # FIXME: the vector_nvic.h file could just as well be a vector_nvic.c file - # in lib/, but that'd spread this mechanism over the whole library; just - # needs some thingking over - outfile_vectornvic.write(template_vector_nvic_h.format(**data)) + outfile_vectornvic.write(template_vector_nvic_c.format(**data)) def main(): - convert(open('irq.yaml'), open('nvic.h', 'w'), open('vector_nvic.h', 'w')) + infile = sys.argv[1] + if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'): + raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml") + nvic_h = infile.replace('irq.yaml', 'nvic.h') + vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c') + convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w')) if __name__ == "__main__": main()